stm32h7 0.16.0

///Register `IV1LR` reader
pub type R = crate::R<IV1LRrs>;
///Register `IV1LR` writer
pub type W = crate::W<IV1LRrs>;
///Field `IV95` reader - IV95
pub type IV95_R = crate::BitReader;
///Field `IV95` writer - IV95
pub type IV95_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV94` reader - IV94
pub type IV94_R = crate::BitReader;
///Field `IV94` writer - IV94
pub type IV94_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV93` reader - IV93
pub type IV93_R = crate::BitReader;
///Field `IV93` writer - IV93
pub type IV93_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV92` reader - IV92
pub type IV92_R = crate::BitReader;
///Field `IV92` writer - IV92
pub type IV92_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV91` reader - IV91
pub type IV91_R = crate::BitReader;
///Field `IV91` writer - IV91
pub type IV91_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV90` reader - IV90
pub type IV90_R = crate::BitReader;
///Field `IV90` writer - IV90
pub type IV90_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV89` reader - IV89
pub type IV89_R = crate::BitReader;
///Field `IV89` writer - IV89
pub type IV89_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV88` reader - IV88
pub type IV88_R = crate::BitReader;
///Field `IV88` writer - IV88
pub type IV88_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV87` reader - IV87
pub type IV87_R = crate::BitReader;
///Field `IV87` writer - IV87
pub type IV87_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV86` reader - IV86
pub type IV86_R = crate::BitReader;
///Field `IV86` writer - IV86
pub type IV86_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV85` reader - IV85
pub type IV85_R = crate::BitReader;
///Field `IV85` writer - IV85
pub type IV85_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV84` reader - IV84
pub type IV84_R = crate::BitReader;
///Field `IV84` writer - IV84
pub type IV84_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV83` reader - IV83
pub type IV83_R = crate::BitReader;
///Field `IV83` writer - IV83
pub type IV83_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV82` reader - IV82
pub type IV82_R = crate::BitReader;
///Field `IV82` writer - IV82
pub type IV82_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV81` reader - IV81
pub type IV81_R = crate::BitReader;
///Field `IV81` writer - IV81
pub type IV81_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV80` reader - IV80
pub type IV80_R = crate::BitReader;
///Field `IV80` writer - IV80
pub type IV80_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV79` reader - IV79
pub type IV79_R = crate::BitReader;
///Field `IV79` writer - IV79
pub type IV79_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV78` reader - IV78
pub type IV78_R = crate::BitReader;
///Field `IV78` writer - IV78
pub type IV78_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV77` reader - IV77
pub type IV77_R = crate::BitReader;
///Field `IV77` writer - IV77
pub type IV77_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV76` reader - IV76
pub type IV76_R = crate::BitReader;
///Field `IV76` writer - IV76
pub type IV76_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV75` reader - IV75
pub type IV75_R = crate::BitReader;
///Field `IV75` writer - IV75
pub type IV75_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV74` reader - IV74
pub type IV74_R = crate::BitReader;
///Field `IV74` writer - IV74
pub type IV74_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV73` reader - IV73
pub type IV73_R = crate::BitReader;
///Field `IV73` writer - IV73
pub type IV73_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV72` reader - IV72
pub type IV72_R = crate::BitReader;
///Field `IV72` writer - IV72
pub type IV72_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV71` reader - IV71
pub type IV71_R = crate::BitReader;
///Field `IV71` writer - IV71
pub type IV71_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV70` reader - IV70
pub type IV70_R = crate::BitReader;
///Field `IV70` writer - IV70
pub type IV70_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV69` reader - IV69
pub type IV69_R = crate::BitReader;
///Field `IV69` writer - IV69
pub type IV69_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV68` reader - IV68
pub type IV68_R = crate::BitReader;
///Field `IV68` writer - IV68
pub type IV68_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV67` reader - IV67
pub type IV67_R = crate::BitReader;
///Field `IV67` writer - IV67
pub type IV67_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV66` reader - IV66
pub type IV66_R = crate::BitReader;
///Field `IV66` writer - IV66
pub type IV66_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV65` reader - IV65
pub type IV65_R = crate::BitReader;
///Field `IV65` writer - IV65
pub type IV65_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV64` reader - IV64
pub type IV64_R = crate::BitReader;
///Field `IV64` writer - IV64
pub type IV64_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - IV95
    #[inline(always)]
    pub fn iv95(&self) -> IV95_R {
        IV95_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - IV94
    #[inline(always)]
    pub fn iv94(&self) -> IV94_R {
        IV94_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - IV93
    #[inline(always)]
    pub fn iv93(&self) -> IV93_R {
        IV93_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - IV92
    #[inline(always)]
    pub fn iv92(&self) -> IV92_R {
        IV92_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - IV91
    #[inline(always)]
    pub fn iv91(&self) -> IV91_R {
        IV91_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - IV90
    #[inline(always)]
    pub fn iv90(&self) -> IV90_R {
        IV90_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - IV89
    #[inline(always)]
    pub fn iv89(&self) -> IV89_R {
        IV89_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - IV88
    #[inline(always)]
    pub fn iv88(&self) -> IV88_R {
        IV88_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - IV87
    #[inline(always)]
    pub fn iv87(&self) -> IV87_R {
        IV87_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - IV86
    #[inline(always)]
    pub fn iv86(&self) -> IV86_R {
        IV86_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - IV85
    #[inline(always)]
    pub fn iv85(&self) -> IV85_R {
        IV85_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - IV84
    #[inline(always)]
    pub fn iv84(&self) -> IV84_R {
        IV84_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - IV83
    #[inline(always)]
    pub fn iv83(&self) -> IV83_R {
        IV83_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - IV82
    #[inline(always)]
    pub fn iv82(&self) -> IV82_R {
        IV82_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - IV81
    #[inline(always)]
    pub fn iv81(&self) -> IV81_R {
        IV81_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - IV80
    #[inline(always)]
    pub fn iv80(&self) -> IV80_R {
        IV80_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - IV79
    #[inline(always)]
    pub fn iv79(&self) -> IV79_R {
        IV79_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - IV78
    #[inline(always)]
    pub fn iv78(&self) -> IV78_R {
        IV78_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - IV77
    #[inline(always)]
    pub fn iv77(&self) -> IV77_R {
        IV77_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - IV76
    #[inline(always)]
    pub fn iv76(&self) -> IV76_R {
        IV76_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - IV75
    #[inline(always)]
    pub fn iv75(&self) -> IV75_R {
        IV75_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - IV74
    #[inline(always)]
    pub fn iv74(&self) -> IV74_R {
        IV74_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - IV73
    #[inline(always)]
    pub fn iv73(&self) -> IV73_R {
        IV73_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - IV72
    #[inline(always)]
    pub fn iv72(&self) -> IV72_R {
        IV72_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - IV71
    #[inline(always)]
    pub fn iv71(&self) -> IV71_R {
        IV71_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - IV70
    #[inline(always)]
    pub fn iv70(&self) -> IV70_R {
        IV70_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - IV69
    #[inline(always)]
    pub fn iv69(&self) -> IV69_R {
        IV69_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - IV68
    #[inline(always)]
    pub fn iv68(&self) -> IV68_R {
        IV68_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - IV67
    #[inline(always)]
    pub fn iv67(&self) -> IV67_R {
        IV67_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - IV66
    #[inline(always)]
    pub fn iv66(&self) -> IV66_R {
        IV66_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - IV65
    #[inline(always)]
    pub fn iv65(&self) -> IV65_R {
        IV65_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - IV64
    #[inline(always)]
    pub fn iv64(&self) -> IV64_R {
        IV64_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IV1LR")
            .field("iv95", &self.iv95())
            .field("iv94", &self.iv94())
            .field("iv93", &self.iv93())
            .field("iv92", &self.iv92())
            .field("iv91", &self.iv91())
            .field("iv90", &self.iv90())
            .field("iv89", &self.iv89())
            .field("iv88", &self.iv88())
            .field("iv87", &self.iv87())
            .field("iv86", &self.iv86())
            .field("iv85", &self.iv85())
            .field("iv84", &self.iv84())
            .field("iv83", &self.iv83())
            .field("iv82", &self.iv82())
            .field("iv81", &self.iv81())
            .field("iv80", &self.iv80())
            .field("iv79", &self.iv79())
            .field("iv78", &self.iv78())
            .field("iv77", &self.iv77())
            .field("iv76", &self.iv76())
            .field("iv75", &self.iv75())
            .field("iv74", &self.iv74())
            .field("iv73", &self.iv73())
            .field("iv72", &self.iv72())
            .field("iv71", &self.iv71())
            .field("iv70", &self.iv70())
            .field("iv69", &self.iv69())
            .field("iv68", &self.iv68())
            .field("iv67", &self.iv67())
            .field("iv66", &self.iv66())
            .field("iv65", &self.iv65())
            .field("iv64", &self.iv64())
            .finish()
    }
}
impl W {
    ///Bit 0 - IV95
    #[inline(always)]
    pub fn iv95(&mut self) -> IV95_W<IV1LRrs> {
        IV95_W::new(self, 0)
    }
    ///Bit 1 - IV94
    #[inline(always)]
    pub fn iv94(&mut self) -> IV94_W<IV1LRrs> {
        IV94_W::new(self, 1)
    }
    ///Bit 2 - IV93
    #[inline(always)]
    pub fn iv93(&mut self) -> IV93_W<IV1LRrs> {
        IV93_W::new(self, 2)
    }
    ///Bit 3 - IV92
    #[inline(always)]
    pub fn iv92(&mut self) -> IV92_W<IV1LRrs> {
        IV92_W::new(self, 3)
    }
    ///Bit 4 - IV91
    #[inline(always)]
    pub fn iv91(&mut self) -> IV91_W<IV1LRrs> {
        IV91_W::new(self, 4)
    }
    ///Bit 5 - IV90
    #[inline(always)]
    pub fn iv90(&mut self) -> IV90_W<IV1LRrs> {
        IV90_W::new(self, 5)
    }
    ///Bit 6 - IV89
    #[inline(always)]
    pub fn iv89(&mut self) -> IV89_W<IV1LRrs> {
        IV89_W::new(self, 6)
    }
    ///Bit 7 - IV88
    #[inline(always)]
    pub fn iv88(&mut self) -> IV88_W<IV1LRrs> {
        IV88_W::new(self, 7)
    }
    ///Bit 8 - IV87
    #[inline(always)]
    pub fn iv87(&mut self) -> IV87_W<IV1LRrs> {
        IV87_W::new(self, 8)
    }
    ///Bit 9 - IV86
    #[inline(always)]
    pub fn iv86(&mut self) -> IV86_W<IV1LRrs> {
        IV86_W::new(self, 9)
    }
    ///Bit 10 - IV85
    #[inline(always)]
    pub fn iv85(&mut self) -> IV85_W<IV1LRrs> {
        IV85_W::new(self, 10)
    }
    ///Bit 11 - IV84
    #[inline(always)]
    pub fn iv84(&mut self) -> IV84_W<IV1LRrs> {
        IV84_W::new(self, 11)
    }
    ///Bit 12 - IV83
    #[inline(always)]
    pub fn iv83(&mut self) -> IV83_W<IV1LRrs> {
        IV83_W::new(self, 12)
    }
    ///Bit 13 - IV82
    #[inline(always)]
    pub fn iv82(&mut self) -> IV82_W<IV1LRrs> {
        IV82_W::new(self, 13)
    }
    ///Bit 14 - IV81
    #[inline(always)]
    pub fn iv81(&mut self) -> IV81_W<IV1LRrs> {
        IV81_W::new(self, 14)
    }
    ///Bit 15 - IV80
    #[inline(always)]
    pub fn iv80(&mut self) -> IV80_W<IV1LRrs> {
        IV80_W::new(self, 15)
    }
    ///Bit 16 - IV79
    #[inline(always)]
    pub fn iv79(&mut self) -> IV79_W<IV1LRrs> {
        IV79_W::new(self, 16)
    }
    ///Bit 17 - IV78
    #[inline(always)]
    pub fn iv78(&mut self) -> IV78_W<IV1LRrs> {
        IV78_W::new(self, 17)
    }
    ///Bit 18 - IV77
    #[inline(always)]
    pub fn iv77(&mut self) -> IV77_W<IV1LRrs> {
        IV77_W::new(self, 18)
    }
    ///Bit 19 - IV76
    #[inline(always)]
    pub fn iv76(&mut self) -> IV76_W<IV1LRrs> {
        IV76_W::new(self, 19)
    }
    ///Bit 20 - IV75
    #[inline(always)]
    pub fn iv75(&mut self) -> IV75_W<IV1LRrs> {
        IV75_W::new(self, 20)
    }
    ///Bit 21 - IV74
    #[inline(always)]
    pub fn iv74(&mut self) -> IV74_W<IV1LRrs> {
        IV74_W::new(self, 21)
    }
    ///Bit 22 - IV73
    #[inline(always)]
    pub fn iv73(&mut self) -> IV73_W<IV1LRrs> {
        IV73_W::new(self, 22)
    }
    ///Bit 23 - IV72
    #[inline(always)]
    pub fn iv72(&mut self) -> IV72_W<IV1LRrs> {
        IV72_W::new(self, 23)
    }
    ///Bit 24 - IV71
    #[inline(always)]
    pub fn iv71(&mut self) -> IV71_W<IV1LRrs> {
        IV71_W::new(self, 24)
    }
    ///Bit 25 - IV70
    #[inline(always)]
    pub fn iv70(&mut self) -> IV70_W<IV1LRrs> {
        IV70_W::new(self, 25)
    }
    ///Bit 26 - IV69
    #[inline(always)]
    pub fn iv69(&mut self) -> IV69_W<IV1LRrs> {
        IV69_W::new(self, 26)
    }
    ///Bit 27 - IV68
    #[inline(always)]
    pub fn iv68(&mut self) -> IV68_W<IV1LRrs> {
        IV68_W::new(self, 27)
    }
    ///Bit 28 - IV67
    #[inline(always)]
    pub fn iv67(&mut self) -> IV67_W<IV1LRrs> {
        IV67_W::new(self, 28)
    }
    ///Bit 29 - IV66
    #[inline(always)]
    pub fn iv66(&mut self) -> IV66_W<IV1LRrs> {
        IV66_W::new(self, 29)
    }
    ///Bit 30 - IV65
    #[inline(always)]
    pub fn iv65(&mut self) -> IV65_W<IV1LRrs> {
        IV65_W::new(self, 30)
    }
    ///Bit 31 - IV64
    #[inline(always)]
    pub fn iv64(&mut self) -> IV64_W<IV1LRrs> {
        IV64_W::new(self, 31)
    }
}
/**initialization vector registers

You can [`read`](crate::Reg::read) this register and get [`iv1lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv1lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct IV1LRrs;
impl crate::RegisterSpec for IV1LRrs {
    type Ux = u32;
}
///`read()` method returns [`iv1lr::R`](R) reader structure
impl crate::Readable for IV1LRrs {}
///`write(|w| ..)` method takes [`iv1lr::W`](W) writer structure
impl crate::Writable for IV1LRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets IV1LR to value 0
impl crate::Resettable for IV1LRrs {}