stm32h7 0.16.0

///Register `IV0RR` reader
pub type R = crate::R<IV0RRrs>;
///Register `IV0RR` writer
pub type W = crate::W<IV0RRrs>;
///Field `IV63` reader - IV63
pub type IV63_R = crate::BitReader;
///Field `IV63` writer - IV63
pub type IV63_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV62` reader - IV62
pub type IV62_R = crate::BitReader;
///Field `IV62` writer - IV62
pub type IV62_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV61` reader - IV61
pub type IV61_R = crate::BitReader;
///Field `IV61` writer - IV61
pub type IV61_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV60` reader - IV60
pub type IV60_R = crate::BitReader;
///Field `IV60` writer - IV60
pub type IV60_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV59` reader - IV59
pub type IV59_R = crate::BitReader;
///Field `IV59` writer - IV59
pub type IV59_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV58` reader - IV58
pub type IV58_R = crate::BitReader;
///Field `IV58` writer - IV58
pub type IV58_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV57` reader - IV57
pub type IV57_R = crate::BitReader;
///Field `IV57` writer - IV57
pub type IV57_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV56` reader - IV56
pub type IV56_R = crate::BitReader;
///Field `IV56` writer - IV56
pub type IV56_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV55` reader - IV55
pub type IV55_R = crate::BitReader;
///Field `IV55` writer - IV55
pub type IV55_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV54` reader - IV54
pub type IV54_R = crate::BitReader;
///Field `IV54` writer - IV54
pub type IV54_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV53` reader - IV53
pub type IV53_R = crate::BitReader;
///Field `IV53` writer - IV53
pub type IV53_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV52` reader - IV52
pub type IV52_R = crate::BitReader;
///Field `IV52` writer - IV52
pub type IV52_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV51` reader - IV51
pub type IV51_R = crate::BitReader;
///Field `IV51` writer - IV51
pub type IV51_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV50` reader - IV50
pub type IV50_R = crate::BitReader;
///Field `IV50` writer - IV50
pub type IV50_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV49` reader - IV49
pub type IV49_R = crate::BitReader;
///Field `IV49` writer - IV49
pub type IV49_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV48` reader - IV48
pub type IV48_R = crate::BitReader;
///Field `IV48` writer - IV48
pub type IV48_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV47` reader - IV47
pub type IV47_R = crate::BitReader;
///Field `IV47` writer - IV47
pub type IV47_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV46` reader - IV46
pub type IV46_R = crate::BitReader;
///Field `IV46` writer - IV46
pub type IV46_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV45` reader - IV45
pub type IV45_R = crate::BitReader;
///Field `IV45` writer - IV45
pub type IV45_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV44` reader - IV44
pub type IV44_R = crate::BitReader;
///Field `IV44` writer - IV44
pub type IV44_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV43` reader - IV43
pub type IV43_R = crate::BitReader;
///Field `IV43` writer - IV43
pub type IV43_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV42` reader - IV42
pub type IV42_R = crate::BitReader;
///Field `IV42` writer - IV42
pub type IV42_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV41` reader - IV41
pub type IV41_R = crate::BitReader;
///Field `IV41` writer - IV41
pub type IV41_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV40` reader - IV40
pub type IV40_R = crate::BitReader;
///Field `IV40` writer - IV40
pub type IV40_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV39` reader - IV39
pub type IV39_R = crate::BitReader;
///Field `IV39` writer - IV39
pub type IV39_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV38` reader - IV38
pub type IV38_R = crate::BitReader;
///Field `IV38` writer - IV38
pub type IV38_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV37` reader - IV37
pub type IV37_R = crate::BitReader;
///Field `IV37` writer - IV37
pub type IV37_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV36` reader - IV36
pub type IV36_R = crate::BitReader;
///Field `IV36` writer - IV36
pub type IV36_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV35` reader - IV35
pub type IV35_R = crate::BitReader;
///Field `IV35` writer - IV35
pub type IV35_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV34` reader - IV34
pub type IV34_R = crate::BitReader;
///Field `IV34` writer - IV34
pub type IV34_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV33` reader - IV33
pub type IV33_R = crate::BitReader;
///Field `IV33` writer - IV33
pub type IV33_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV32` reader - IV32
pub type IV32_R = crate::BitReader;
///Field `IV32` writer - IV32
pub type IV32_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - IV63
    #[inline(always)]
    pub fn iv63(&self) -> IV63_R {
        IV63_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - IV62
    #[inline(always)]
    pub fn iv62(&self) -> IV62_R {
        IV62_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - IV61
    #[inline(always)]
    pub fn iv61(&self) -> IV61_R {
        IV61_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - IV60
    #[inline(always)]
    pub fn iv60(&self) -> IV60_R {
        IV60_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - IV59
    #[inline(always)]
    pub fn iv59(&self) -> IV59_R {
        IV59_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - IV58
    #[inline(always)]
    pub fn iv58(&self) -> IV58_R {
        IV58_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - IV57
    #[inline(always)]
    pub fn iv57(&self) -> IV57_R {
        IV57_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - IV56
    #[inline(always)]
    pub fn iv56(&self) -> IV56_R {
        IV56_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - IV55
    #[inline(always)]
    pub fn iv55(&self) -> IV55_R {
        IV55_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - IV54
    #[inline(always)]
    pub fn iv54(&self) -> IV54_R {
        IV54_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - IV53
    #[inline(always)]
    pub fn iv53(&self) -> IV53_R {
        IV53_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - IV52
    #[inline(always)]
    pub fn iv52(&self) -> IV52_R {
        IV52_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - IV51
    #[inline(always)]
    pub fn iv51(&self) -> IV51_R {
        IV51_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - IV50
    #[inline(always)]
    pub fn iv50(&self) -> IV50_R {
        IV50_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - IV49
    #[inline(always)]
    pub fn iv49(&self) -> IV49_R {
        IV49_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - IV48
    #[inline(always)]
    pub fn iv48(&self) -> IV48_R {
        IV48_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - IV47
    #[inline(always)]
    pub fn iv47(&self) -> IV47_R {
        IV47_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - IV46
    #[inline(always)]
    pub fn iv46(&self) -> IV46_R {
        IV46_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - IV45
    #[inline(always)]
    pub fn iv45(&self) -> IV45_R {
        IV45_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - IV44
    #[inline(always)]
    pub fn iv44(&self) -> IV44_R {
        IV44_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - IV43
    #[inline(always)]
    pub fn iv43(&self) -> IV43_R {
        IV43_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - IV42
    #[inline(always)]
    pub fn iv42(&self) -> IV42_R {
        IV42_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - IV41
    #[inline(always)]
    pub fn iv41(&self) -> IV41_R {
        IV41_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - IV40
    #[inline(always)]
    pub fn iv40(&self) -> IV40_R {
        IV40_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - IV39
    #[inline(always)]
    pub fn iv39(&self) -> IV39_R {
        IV39_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - IV38
    #[inline(always)]
    pub fn iv38(&self) -> IV38_R {
        IV38_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - IV37
    #[inline(always)]
    pub fn iv37(&self) -> IV37_R {
        IV37_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - IV36
    #[inline(always)]
    pub fn iv36(&self) -> IV36_R {
        IV36_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - IV35
    #[inline(always)]
    pub fn iv35(&self) -> IV35_R {
        IV35_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - IV34
    #[inline(always)]
    pub fn iv34(&self) -> IV34_R {
        IV34_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - IV33
    #[inline(always)]
    pub fn iv33(&self) -> IV33_R {
        IV33_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - IV32
    #[inline(always)]
    pub fn iv32(&self) -> IV32_R {
        IV32_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IV0RR")
            .field("iv63", &self.iv63())
            .field("iv62", &self.iv62())
            .field("iv61", &self.iv61())
            .field("iv60", &self.iv60())
            .field("iv59", &self.iv59())
            .field("iv58", &self.iv58())
            .field("iv57", &self.iv57())
            .field("iv56", &self.iv56())
            .field("iv55", &self.iv55())
            .field("iv54", &self.iv54())
            .field("iv53", &self.iv53())
            .field("iv52", &self.iv52())
            .field("iv51", &self.iv51())
            .field("iv50", &self.iv50())
            .field("iv49", &self.iv49())
            .field("iv48", &self.iv48())
            .field("iv47", &self.iv47())
            .field("iv46", &self.iv46())
            .field("iv45", &self.iv45())
            .field("iv44", &self.iv44())
            .field("iv43", &self.iv43())
            .field("iv42", &self.iv42())
            .field("iv41", &self.iv41())
            .field("iv40", &self.iv40())
            .field("iv39", &self.iv39())
            .field("iv38", &self.iv38())
            .field("iv37", &self.iv37())
            .field("iv36", &self.iv36())
            .field("iv35", &self.iv35())
            .field("iv34", &self.iv34())
            .field("iv33", &self.iv33())
            .field("iv32", &self.iv32())
            .finish()
    }
}
impl W {
    ///Bit 0 - IV63
    #[inline(always)]
    pub fn iv63(&mut self) -> IV63_W<IV0RRrs> {
        IV63_W::new(self, 0)
    }
    ///Bit 1 - IV62
    #[inline(always)]
    pub fn iv62(&mut self) -> IV62_W<IV0RRrs> {
        IV62_W::new(self, 1)
    }
    ///Bit 2 - IV61
    #[inline(always)]
    pub fn iv61(&mut self) -> IV61_W<IV0RRrs> {
        IV61_W::new(self, 2)
    }
    ///Bit 3 - IV60
    #[inline(always)]
    pub fn iv60(&mut self) -> IV60_W<IV0RRrs> {
        IV60_W::new(self, 3)
    }
    ///Bit 4 - IV59
    #[inline(always)]
    pub fn iv59(&mut self) -> IV59_W<IV0RRrs> {
        IV59_W::new(self, 4)
    }
    ///Bit 5 - IV58
    #[inline(always)]
    pub fn iv58(&mut self) -> IV58_W<IV0RRrs> {
        IV58_W::new(self, 5)
    }
    ///Bit 6 - IV57
    #[inline(always)]
    pub fn iv57(&mut self) -> IV57_W<IV0RRrs> {
        IV57_W::new(self, 6)
    }
    ///Bit 7 - IV56
    #[inline(always)]
    pub fn iv56(&mut self) -> IV56_W<IV0RRrs> {
        IV56_W::new(self, 7)
    }
    ///Bit 8 - IV55
    #[inline(always)]
    pub fn iv55(&mut self) -> IV55_W<IV0RRrs> {
        IV55_W::new(self, 8)
    }
    ///Bit 9 - IV54
    #[inline(always)]
    pub fn iv54(&mut self) -> IV54_W<IV0RRrs> {
        IV54_W::new(self, 9)
    }
    ///Bit 10 - IV53
    #[inline(always)]
    pub fn iv53(&mut self) -> IV53_W<IV0RRrs> {
        IV53_W::new(self, 10)
    }
    ///Bit 11 - IV52
    #[inline(always)]
    pub fn iv52(&mut self) -> IV52_W<IV0RRrs> {
        IV52_W::new(self, 11)
    }
    ///Bit 12 - IV51
    #[inline(always)]
    pub fn iv51(&mut self) -> IV51_W<IV0RRrs> {
        IV51_W::new(self, 12)
    }
    ///Bit 13 - IV50
    #[inline(always)]
    pub fn iv50(&mut self) -> IV50_W<IV0RRrs> {
        IV50_W::new(self, 13)
    }
    ///Bit 14 - IV49
    #[inline(always)]
    pub fn iv49(&mut self) -> IV49_W<IV0RRrs> {
        IV49_W::new(self, 14)
    }
    ///Bit 15 - IV48
    #[inline(always)]
    pub fn iv48(&mut self) -> IV48_W<IV0RRrs> {
        IV48_W::new(self, 15)
    }
    ///Bit 16 - IV47
    #[inline(always)]
    pub fn iv47(&mut self) -> IV47_W<IV0RRrs> {
        IV47_W::new(self, 16)
    }
    ///Bit 17 - IV46
    #[inline(always)]
    pub fn iv46(&mut self) -> IV46_W<IV0RRrs> {
        IV46_W::new(self, 17)
    }
    ///Bit 18 - IV45
    #[inline(always)]
    pub fn iv45(&mut self) -> IV45_W<IV0RRrs> {
        IV45_W::new(self, 18)
    }
    ///Bit 19 - IV44
    #[inline(always)]
    pub fn iv44(&mut self) -> IV44_W<IV0RRrs> {
        IV44_W::new(self, 19)
    }
    ///Bit 20 - IV43
    #[inline(always)]
    pub fn iv43(&mut self) -> IV43_W<IV0RRrs> {
        IV43_W::new(self, 20)
    }
    ///Bit 21 - IV42
    #[inline(always)]
    pub fn iv42(&mut self) -> IV42_W<IV0RRrs> {
        IV42_W::new(self, 21)
    }
    ///Bit 22 - IV41
    #[inline(always)]
    pub fn iv41(&mut self) -> IV41_W<IV0RRrs> {
        IV41_W::new(self, 22)
    }
    ///Bit 23 - IV40
    #[inline(always)]
    pub fn iv40(&mut self) -> IV40_W<IV0RRrs> {
        IV40_W::new(self, 23)
    }
    ///Bit 24 - IV39
    #[inline(always)]
    pub fn iv39(&mut self) -> IV39_W<IV0RRrs> {
        IV39_W::new(self, 24)
    }
    ///Bit 25 - IV38
    #[inline(always)]
    pub fn iv38(&mut self) -> IV38_W<IV0RRrs> {
        IV38_W::new(self, 25)
    }
    ///Bit 26 - IV37
    #[inline(always)]
    pub fn iv37(&mut self) -> IV37_W<IV0RRrs> {
        IV37_W::new(self, 26)
    }
    ///Bit 27 - IV36
    #[inline(always)]
    pub fn iv36(&mut self) -> IV36_W<IV0RRrs> {
        IV36_W::new(self, 27)
    }
    ///Bit 28 - IV35
    #[inline(always)]
    pub fn iv35(&mut self) -> IV35_W<IV0RRrs> {
        IV35_W::new(self, 28)
    }
    ///Bit 29 - IV34
    #[inline(always)]
    pub fn iv34(&mut self) -> IV34_W<IV0RRrs> {
        IV34_W::new(self, 29)
    }
    ///Bit 30 - IV33
    #[inline(always)]
    pub fn iv33(&mut self) -> IV33_W<IV0RRrs> {
        IV33_W::new(self, 30)
    }
    ///Bit 31 - IV32
    #[inline(always)]
    pub fn iv32(&mut self) -> IV32_W<IV0RRrs> {
        IV32_W::new(self, 31)
    }
}
/**initialization vector registers

You can [`read`](crate::Reg::read) this register and get [`iv0rr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv0rr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct IV0RRrs;
impl crate::RegisterSpec for IV0RRrs {
    type Ux = u32;
}
///`read()` method returns [`iv0rr::R`](R) reader structure
impl crate::Readable for IV0RRrs {}
///`write(|w| ..)` method takes [`iv0rr::W`](W) writer structure
impl crate::Writable for IV0RRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets IV0RR to value 0
impl crate::Resettable for IV0RRrs {}