stm32h7 0.16.0

///Register `IV0LR` reader
pub type R = crate::R<IV0LRrs>;
///Register `IV0LR` writer
pub type W = crate::W<IV0LRrs>;
///Field `IV31` reader - IV31
pub type IV31_R = crate::BitReader;
///Field `IV31` writer - IV31
pub type IV31_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV30` reader - IV30
pub type IV30_R = crate::BitReader;
///Field `IV30` writer - IV30
pub type IV30_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV29` reader - IV29
pub type IV29_R = crate::BitReader;
///Field `IV29` writer - IV29
pub type IV29_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV28` reader - IV28
pub type IV28_R = crate::BitReader;
///Field `IV28` writer - IV28
pub type IV28_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV27` reader - IV27
pub type IV27_R = crate::BitReader;
///Field `IV27` writer - IV27
pub type IV27_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV26` reader - IV26
pub type IV26_R = crate::BitReader;
///Field `IV26` writer - IV26
pub type IV26_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV25` reader - IV25
pub type IV25_R = crate::BitReader;
///Field `IV25` writer - IV25
pub type IV25_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV24` reader - IV24
pub type IV24_R = crate::BitReader;
///Field `IV24` writer - IV24
pub type IV24_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV23` reader - IV23
pub type IV23_R = crate::BitReader;
///Field `IV23` writer - IV23
pub type IV23_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV22` reader - IV22
pub type IV22_R = crate::BitReader;
///Field `IV22` writer - IV22
pub type IV22_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV21` reader - IV21
pub type IV21_R = crate::BitReader;
///Field `IV21` writer - IV21
pub type IV21_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV20` reader - IV20
pub type IV20_R = crate::BitReader;
///Field `IV20` writer - IV20
pub type IV20_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV19` reader - IV19
pub type IV19_R = crate::BitReader;
///Field `IV19` writer - IV19
pub type IV19_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV18` reader - IV18
pub type IV18_R = crate::BitReader;
///Field `IV18` writer - IV18
pub type IV18_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV17` reader - IV17
pub type IV17_R = crate::BitReader;
///Field `IV17` writer - IV17
pub type IV17_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV16` reader - IV16
pub type IV16_R = crate::BitReader;
///Field `IV16` writer - IV16
pub type IV16_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV15` reader - IV15
pub type IV15_R = crate::BitReader;
///Field `IV15` writer - IV15
pub type IV15_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV14` reader - IV14
pub type IV14_R = crate::BitReader;
///Field `IV14` writer - IV14
pub type IV14_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV13` reader - IV13
pub type IV13_R = crate::BitReader;
///Field `IV13` writer - IV13
pub type IV13_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV12` reader - IV12
pub type IV12_R = crate::BitReader;
///Field `IV12` writer - IV12
pub type IV12_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV11` reader - IV11
pub type IV11_R = crate::BitReader;
///Field `IV11` writer - IV11
pub type IV11_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV10` reader - IV10
pub type IV10_R = crate::BitReader;
///Field `IV10` writer - IV10
pub type IV10_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV9` reader - IV9
pub type IV9_R = crate::BitReader;
///Field `IV9` writer - IV9
pub type IV9_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV8` reader - IV8
pub type IV8_R = crate::BitReader;
///Field `IV8` writer - IV8
pub type IV8_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV7` reader - IV7
pub type IV7_R = crate::BitReader;
///Field `IV7` writer - IV7
pub type IV7_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV6` reader - IV6
pub type IV6_R = crate::BitReader;
///Field `IV6` writer - IV6
pub type IV6_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV5` reader - IV5
pub type IV5_R = crate::BitReader;
///Field `IV5` writer - IV5
pub type IV5_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV4` reader - IV4
pub type IV4_R = crate::BitReader;
///Field `IV4` writer - IV4
pub type IV4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV3` reader - IV3
pub type IV3_R = crate::BitReader;
///Field `IV3` writer - IV3
pub type IV3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV2` reader - IV2
pub type IV2_R = crate::BitReader;
///Field `IV2` writer - IV2
pub type IV2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV1` reader - IV1
pub type IV1_R = crate::BitReader;
///Field `IV1` writer - IV1
pub type IV1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IV0` reader - IV0
pub type IV0_R = crate::BitReader;
///Field `IV0` writer - IV0
pub type IV0_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - IV31
    #[inline(always)]
    pub fn iv31(&self) -> IV31_R {
        IV31_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - IV30
    #[inline(always)]
    pub fn iv30(&self) -> IV30_R {
        IV30_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - IV29
    #[inline(always)]
    pub fn iv29(&self) -> IV29_R {
        IV29_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - IV28
    #[inline(always)]
    pub fn iv28(&self) -> IV28_R {
        IV28_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - IV27
    #[inline(always)]
    pub fn iv27(&self) -> IV27_R {
        IV27_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - IV26
    #[inline(always)]
    pub fn iv26(&self) -> IV26_R {
        IV26_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - IV25
    #[inline(always)]
    pub fn iv25(&self) -> IV25_R {
        IV25_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - IV24
    #[inline(always)]
    pub fn iv24(&self) -> IV24_R {
        IV24_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - IV23
    #[inline(always)]
    pub fn iv23(&self) -> IV23_R {
        IV23_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - IV22
    #[inline(always)]
    pub fn iv22(&self) -> IV22_R {
        IV22_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - IV21
    #[inline(always)]
    pub fn iv21(&self) -> IV21_R {
        IV21_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - IV20
    #[inline(always)]
    pub fn iv20(&self) -> IV20_R {
        IV20_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - IV19
    #[inline(always)]
    pub fn iv19(&self) -> IV19_R {
        IV19_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - IV18
    #[inline(always)]
    pub fn iv18(&self) -> IV18_R {
        IV18_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - IV17
    #[inline(always)]
    pub fn iv17(&self) -> IV17_R {
        IV17_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - IV16
    #[inline(always)]
    pub fn iv16(&self) -> IV16_R {
        IV16_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - IV15
    #[inline(always)]
    pub fn iv15(&self) -> IV15_R {
        IV15_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - IV14
    #[inline(always)]
    pub fn iv14(&self) -> IV14_R {
        IV14_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - IV13
    #[inline(always)]
    pub fn iv13(&self) -> IV13_R {
        IV13_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - IV12
    #[inline(always)]
    pub fn iv12(&self) -> IV12_R {
        IV12_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - IV11
    #[inline(always)]
    pub fn iv11(&self) -> IV11_R {
        IV11_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - IV10
    #[inline(always)]
    pub fn iv10(&self) -> IV10_R {
        IV10_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - IV9
    #[inline(always)]
    pub fn iv9(&self) -> IV9_R {
        IV9_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - IV8
    #[inline(always)]
    pub fn iv8(&self) -> IV8_R {
        IV8_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - IV7
    #[inline(always)]
    pub fn iv7(&self) -> IV7_R {
        IV7_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - IV6
    #[inline(always)]
    pub fn iv6(&self) -> IV6_R {
        IV6_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - IV5
    #[inline(always)]
    pub fn iv5(&self) -> IV5_R {
        IV5_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - IV4
    #[inline(always)]
    pub fn iv4(&self) -> IV4_R {
        IV4_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - IV3
    #[inline(always)]
    pub fn iv3(&self) -> IV3_R {
        IV3_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - IV2
    #[inline(always)]
    pub fn iv2(&self) -> IV2_R {
        IV2_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - IV1
    #[inline(always)]
    pub fn iv1(&self) -> IV1_R {
        IV1_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - IV0
    #[inline(always)]
    pub fn iv0(&self) -> IV0_R {
        IV0_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IV0LR")
            .field("iv31", &self.iv31())
            .field("iv30", &self.iv30())
            .field("iv29", &self.iv29())
            .field("iv28", &self.iv28())
            .field("iv27", &self.iv27())
            .field("iv26", &self.iv26())
            .field("iv25", &self.iv25())
            .field("iv24", &self.iv24())
            .field("iv23", &self.iv23())
            .field("iv22", &self.iv22())
            .field("iv21", &self.iv21())
            .field("iv20", &self.iv20())
            .field("iv19", &self.iv19())
            .field("iv18", &self.iv18())
            .field("iv17", &self.iv17())
            .field("iv16", &self.iv16())
            .field("iv15", &self.iv15())
            .field("iv14", &self.iv14())
            .field("iv13", &self.iv13())
            .field("iv12", &self.iv12())
            .field("iv11", &self.iv11())
            .field("iv10", &self.iv10())
            .field("iv9", &self.iv9())
            .field("iv8", &self.iv8())
            .field("iv7", &self.iv7())
            .field("iv6", &self.iv6())
            .field("iv5", &self.iv5())
            .field("iv4", &self.iv4())
            .field("iv3", &self.iv3())
            .field("iv2", &self.iv2())
            .field("iv1", &self.iv1())
            .field("iv0", &self.iv0())
            .finish()
    }
}
impl W {
    ///Bit 0 - IV31
    #[inline(always)]
    pub fn iv31(&mut self) -> IV31_W<IV0LRrs> {
        IV31_W::new(self, 0)
    }
    ///Bit 1 - IV30
    #[inline(always)]
    pub fn iv30(&mut self) -> IV30_W<IV0LRrs> {
        IV30_W::new(self, 1)
    }
    ///Bit 2 - IV29
    #[inline(always)]
    pub fn iv29(&mut self) -> IV29_W<IV0LRrs> {
        IV29_W::new(self, 2)
    }
    ///Bit 3 - IV28
    #[inline(always)]
    pub fn iv28(&mut self) -> IV28_W<IV0LRrs> {
        IV28_W::new(self, 3)
    }
    ///Bit 4 - IV27
    #[inline(always)]
    pub fn iv27(&mut self) -> IV27_W<IV0LRrs> {
        IV27_W::new(self, 4)
    }
    ///Bit 5 - IV26
    #[inline(always)]
    pub fn iv26(&mut self) -> IV26_W<IV0LRrs> {
        IV26_W::new(self, 5)
    }
    ///Bit 6 - IV25
    #[inline(always)]
    pub fn iv25(&mut self) -> IV25_W<IV0LRrs> {
        IV25_W::new(self, 6)
    }
    ///Bit 7 - IV24
    #[inline(always)]
    pub fn iv24(&mut self) -> IV24_W<IV0LRrs> {
        IV24_W::new(self, 7)
    }
    ///Bit 8 - IV23
    #[inline(always)]
    pub fn iv23(&mut self) -> IV23_W<IV0LRrs> {
        IV23_W::new(self, 8)
    }
    ///Bit 9 - IV22
    #[inline(always)]
    pub fn iv22(&mut self) -> IV22_W<IV0LRrs> {
        IV22_W::new(self, 9)
    }
    ///Bit 10 - IV21
    #[inline(always)]
    pub fn iv21(&mut self) -> IV21_W<IV0LRrs> {
        IV21_W::new(self, 10)
    }
    ///Bit 11 - IV20
    #[inline(always)]
    pub fn iv20(&mut self) -> IV20_W<IV0LRrs> {
        IV20_W::new(self, 11)
    }
    ///Bit 12 - IV19
    #[inline(always)]
    pub fn iv19(&mut self) -> IV19_W<IV0LRrs> {
        IV19_W::new(self, 12)
    }
    ///Bit 13 - IV18
    #[inline(always)]
    pub fn iv18(&mut self) -> IV18_W<IV0LRrs> {
        IV18_W::new(self, 13)
    }
    ///Bit 14 - IV17
    #[inline(always)]
    pub fn iv17(&mut self) -> IV17_W<IV0LRrs> {
        IV17_W::new(self, 14)
    }
    ///Bit 15 - IV16
    #[inline(always)]
    pub fn iv16(&mut self) -> IV16_W<IV0LRrs> {
        IV16_W::new(self, 15)
    }
    ///Bit 16 - IV15
    #[inline(always)]
    pub fn iv15(&mut self) -> IV15_W<IV0LRrs> {
        IV15_W::new(self, 16)
    }
    ///Bit 17 - IV14
    #[inline(always)]
    pub fn iv14(&mut self) -> IV14_W<IV0LRrs> {
        IV14_W::new(self, 17)
    }
    ///Bit 18 - IV13
    #[inline(always)]
    pub fn iv13(&mut self) -> IV13_W<IV0LRrs> {
        IV13_W::new(self, 18)
    }
    ///Bit 19 - IV12
    #[inline(always)]
    pub fn iv12(&mut self) -> IV12_W<IV0LRrs> {
        IV12_W::new(self, 19)
    }
    ///Bit 20 - IV11
    #[inline(always)]
    pub fn iv11(&mut self) -> IV11_W<IV0LRrs> {
        IV11_W::new(self, 20)
    }
    ///Bit 21 - IV10
    #[inline(always)]
    pub fn iv10(&mut self) -> IV10_W<IV0LRrs> {
        IV10_W::new(self, 21)
    }
    ///Bit 22 - IV9
    #[inline(always)]
    pub fn iv9(&mut self) -> IV9_W<IV0LRrs> {
        IV9_W::new(self, 22)
    }
    ///Bit 23 - IV8
    #[inline(always)]
    pub fn iv8(&mut self) -> IV8_W<IV0LRrs> {
        IV8_W::new(self, 23)
    }
    ///Bit 24 - IV7
    #[inline(always)]
    pub fn iv7(&mut self) -> IV7_W<IV0LRrs> {
        IV7_W::new(self, 24)
    }
    ///Bit 25 - IV6
    #[inline(always)]
    pub fn iv6(&mut self) -> IV6_W<IV0LRrs> {
        IV6_W::new(self, 25)
    }
    ///Bit 26 - IV5
    #[inline(always)]
    pub fn iv5(&mut self) -> IV5_W<IV0LRrs> {
        IV5_W::new(self, 26)
    }
    ///Bit 27 - IV4
    #[inline(always)]
    pub fn iv4(&mut self) -> IV4_W<IV0LRrs> {
        IV4_W::new(self, 27)
    }
    ///Bit 28 - IV3
    #[inline(always)]
    pub fn iv3(&mut self) -> IV3_W<IV0LRrs> {
        IV3_W::new(self, 28)
    }
    ///Bit 29 - IV2
    #[inline(always)]
    pub fn iv2(&mut self) -> IV2_W<IV0LRrs> {
        IV2_W::new(self, 29)
    }
    ///Bit 30 - IV1
    #[inline(always)]
    pub fn iv1(&mut self) -> IV1_W<IV0LRrs> {
        IV1_W::new(self, 30)
    }
    ///Bit 31 - IV0
    #[inline(always)]
    pub fn iv0(&mut self) -> IV0_W<IV0LRrs> {
        IV0_W::new(self, 31)
    }
}
/**initialization vector registers

You can [`read`](crate::Reg::read) this register and get [`iv0lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv0lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct IV0LRrs;
impl crate::RegisterSpec for IV0LRrs {
    type Ux = u32;
}
///`read()` method returns [`iv0lr::R`](R) reader structure
impl crate::Readable for IV0LRrs {}
///`write(|w| ..)` method takes [`iv0lr::W`](W) writer structure
impl crate::Writable for IV0LRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets IV0LR to value 0
impl crate::Resettable for IV0LRrs {}