cc430f5137 0.1.0

Peripheral access API for CC430F5137 microcontroller
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#[doc = "Register `UCSCTL8` reader"]
pub type R = crate::R<Ucsctl8Spec>;
#[doc = "Register `UCSCTL8` writer"]
pub type W = crate::W<Ucsctl8Spec>;
#[doc = "Field `ACLKREQEN` reader - ACLK Clock Request Enable"]
pub type AclkreqenR = crate::BitReader;
#[doc = "Field `ACLKREQEN` writer - ACLK Clock Request Enable"]
pub type AclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCLKREQEN` reader - MCLK Clock Request Enable"]
pub type MclkreqenR = crate::BitReader;
#[doc = "Field `MCLKREQEN` writer - MCLK Clock Request Enable"]
pub type MclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMCLKREQEN` reader - SMCLK Clock Request Enable"]
pub type SmclkreqenR = crate::BitReader;
#[doc = "Field `SMCLKREQEN` writer - SMCLK Clock Request Enable"]
pub type SmclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MODOSCREQEN` reader - MODOSC Clock Request Enable"]
pub type ModoscreqenR = crate::BitReader;
#[doc = "Field `MODOSCREQEN` writer - MODOSC Clock Request Enable"]
pub type ModoscreqenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - ACLK Clock Request Enable"]
    #[inline(always)]
    pub fn aclkreqen(&self) -> AclkreqenR {
        AclkreqenR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - MCLK Clock Request Enable"]
    #[inline(always)]
    pub fn mclkreqen(&self) -> MclkreqenR {
        MclkreqenR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - SMCLK Clock Request Enable"]
    #[inline(always)]
    pub fn smclkreqen(&self) -> SmclkreqenR {
        SmclkreqenR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - MODOSC Clock Request Enable"]
    #[inline(always)]
    pub fn modoscreqen(&self) -> ModoscreqenR {
        ModoscreqenR::new(((self.bits >> 3) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - ACLK Clock Request Enable"]
    #[inline(always)]
    pub fn aclkreqen(&mut self) -> AclkreqenW<'_, Ucsctl8Spec> {
        AclkreqenW::new(self, 0)
    }
    #[doc = "Bit 1 - MCLK Clock Request Enable"]
    #[inline(always)]
    pub fn mclkreqen(&mut self) -> MclkreqenW<'_, Ucsctl8Spec> {
        MclkreqenW::new(self, 1)
    }
    #[doc = "Bit 2 - SMCLK Clock Request Enable"]
    #[inline(always)]
    pub fn smclkreqen(&mut self) -> SmclkreqenW<'_, Ucsctl8Spec> {
        SmclkreqenW::new(self, 2)
    }
    #[doc = "Bit 3 - MODOSC Clock Request Enable"]
    #[inline(always)]
    pub fn modoscreqen(&mut self) -> ModoscreqenW<'_, Ucsctl8Spec> {
        ModoscreqenW::new(self, 3)
    }
}
#[doc = "UCS Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`ucsctl8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsctl8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucsctl8Spec;
impl crate::RegisterSpec for Ucsctl8Spec {
    type Ux = u16;
}
#[doc = "`read()` method returns [`ucsctl8::R`](R) reader structure"]
impl crate::Readable for Ucsctl8Spec {}
#[doc = "`write(|w| ..)` method takes [`ucsctl8::W`](W) writer structure"]
impl crate::Writable for Ucsctl8Spec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCSCTL8 to value 0"]
impl crate::Resettable for Ucsctl8Spec {}