#[doc = "Register `UCSCTL5` reader"]
pub type R = crate::R<Ucsctl5Spec>;
#[doc = "Register `UCSCTL5` writer"]
pub type W = crate::W<Ucsctl5Spec>;
#[doc = "MCLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Divm {
#[doc = "0: MCLK Source Divider 0"]
Divm0 = 0,
#[doc = "1: MCLK Source Divider 1"]
Divm1 = 1,
#[doc = "2: MCLK Source Divider 2"]
Divm2 = 2,
#[doc = "3: MCLK Source Divider 3"]
Divm3 = 3,
#[doc = "4: MCLK Source Divider 4"]
Divm4 = 4,
#[doc = "5: MCLK Source Divider 5"]
Divm5 = 5,
#[doc = "6: MCLK Source Divider 6"]
Divm6 = 6,
#[doc = "7: MCLK Source Divider 7"]
Divm7 = 7,
}
impl From<Divm> for u8 {
#[inline(always)]
fn from(variant: Divm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Divm {
type Ux = u8;
}
impl crate::IsEnum for Divm {}
#[doc = "Field `DIVM` reader - MCLK Divider Bit: 0"]
pub type DivmR = crate::FieldReader<Divm>;
impl DivmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Divm {
match self.bits {
0 => Divm::Divm0,
1 => Divm::Divm1,
2 => Divm::Divm2,
3 => Divm::Divm3,
4 => Divm::Divm4,
5 => Divm::Divm5,
6 => Divm::Divm6,
7 => Divm::Divm7,
_ => unreachable!(),
}
}
#[doc = "MCLK Source Divider 0"]
#[inline(always)]
pub fn is_divm_0(&self) -> bool {
*self == Divm::Divm0
}
#[doc = "MCLK Source Divider 1"]
#[inline(always)]
pub fn is_divm_1(&self) -> bool {
*self == Divm::Divm1
}
#[doc = "MCLK Source Divider 2"]
#[inline(always)]
pub fn is_divm_2(&self) -> bool {
*self == Divm::Divm2
}
#[doc = "MCLK Source Divider 3"]
#[inline(always)]
pub fn is_divm_3(&self) -> bool {
*self == Divm::Divm3
}
#[doc = "MCLK Source Divider 4"]
#[inline(always)]
pub fn is_divm_4(&self) -> bool {
*self == Divm::Divm4
}
#[doc = "MCLK Source Divider 5"]
#[inline(always)]
pub fn is_divm_5(&self) -> bool {
*self == Divm::Divm5
}
#[doc = "MCLK Source Divider 6"]
#[inline(always)]
pub fn is_divm_6(&self) -> bool {
*self == Divm::Divm6
}
#[doc = "MCLK Source Divider 7"]
#[inline(always)]
pub fn is_divm_7(&self) -> bool {
*self == Divm::Divm7
}
}
#[doc = "Field `DIVM` writer - MCLK Divider Bit: 0"]
pub type DivmW<'a, REG> = crate::FieldWriter<'a, REG, 3, Divm, crate::Safe>;
impl<'a, REG> DivmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "MCLK Source Divider 0"]
#[inline(always)]
pub fn divm_0(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm0)
}
#[doc = "MCLK Source Divider 1"]
#[inline(always)]
pub fn divm_1(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm1)
}
#[doc = "MCLK Source Divider 2"]
#[inline(always)]
pub fn divm_2(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm2)
}
#[doc = "MCLK Source Divider 3"]
#[inline(always)]
pub fn divm_3(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm3)
}
#[doc = "MCLK Source Divider 4"]
#[inline(always)]
pub fn divm_4(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm4)
}
#[doc = "MCLK Source Divider 5"]
#[inline(always)]
pub fn divm_5(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm5)
}
#[doc = "MCLK Source Divider 6"]
#[inline(always)]
pub fn divm_6(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm6)
}
#[doc = "MCLK Source Divider 7"]
#[inline(always)]
pub fn divm_7(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm7)
}
}
#[doc = "SMCLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Divs {
#[doc = "0: SMCLK Source Divider 0"]
Divs0 = 0,
#[doc = "1: SMCLK Source Divider 1"]
Divs1 = 1,
#[doc = "2: SMCLK Source Divider 2"]
Divs2 = 2,
#[doc = "3: SMCLK Source Divider 3"]
Divs3 = 3,
#[doc = "4: SMCLK Source Divider 4"]
Divs4 = 4,
#[doc = "5: SMCLK Source Divider 5"]
Divs5 = 5,
#[doc = "6: SMCLK Source Divider 6"]
Divs6 = 6,
#[doc = "7: SMCLK Source Divider 7"]
Divs7 = 7,
}
impl From<Divs> for u8 {
#[inline(always)]
fn from(variant: Divs) -> Self {
variant as _
}
}
impl crate::FieldSpec for Divs {
type Ux = u8;
}
impl crate::IsEnum for Divs {}
#[doc = "Field `DIVS` reader - SMCLK Divider Bit: 0"]
pub type DivsR = crate::FieldReader<Divs>;
impl DivsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Divs {
match self.bits {
0 => Divs::Divs0,
1 => Divs::Divs1,
2 => Divs::Divs2,
3 => Divs::Divs3,
4 => Divs::Divs4,
5 => Divs::Divs5,
6 => Divs::Divs6,
7 => Divs::Divs7,
_ => unreachable!(),
}
}
#[doc = "SMCLK Source Divider 0"]
#[inline(always)]
pub fn is_divs_0(&self) -> bool {
*self == Divs::Divs0
}
#[doc = "SMCLK Source Divider 1"]
#[inline(always)]
pub fn is_divs_1(&self) -> bool {
*self == Divs::Divs1
}
#[doc = "SMCLK Source Divider 2"]
#[inline(always)]
pub fn is_divs_2(&self) -> bool {
*self == Divs::Divs2
}
#[doc = "SMCLK Source Divider 3"]
#[inline(always)]
pub fn is_divs_3(&self) -> bool {
*self == Divs::Divs3
}
#[doc = "SMCLK Source Divider 4"]
#[inline(always)]
pub fn is_divs_4(&self) -> bool {
*self == Divs::Divs4
}
#[doc = "SMCLK Source Divider 5"]
#[inline(always)]
pub fn is_divs_5(&self) -> bool {
*self == Divs::Divs5
}
#[doc = "SMCLK Source Divider 6"]
#[inline(always)]
pub fn is_divs_6(&self) -> bool {
*self == Divs::Divs6
}
#[doc = "SMCLK Source Divider 7"]
#[inline(always)]
pub fn is_divs_7(&self) -> bool {
*self == Divs::Divs7
}
}
#[doc = "Field `DIVS` writer - SMCLK Divider Bit: 0"]
pub type DivsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Divs, crate::Safe>;
impl<'a, REG> DivsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SMCLK Source Divider 0"]
#[inline(always)]
pub fn divs_0(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs0)
}
#[doc = "SMCLK Source Divider 1"]
#[inline(always)]
pub fn divs_1(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs1)
}
#[doc = "SMCLK Source Divider 2"]
#[inline(always)]
pub fn divs_2(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs2)
}
#[doc = "SMCLK Source Divider 3"]
#[inline(always)]
pub fn divs_3(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs3)
}
#[doc = "SMCLK Source Divider 4"]
#[inline(always)]
pub fn divs_4(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs4)
}
#[doc = "SMCLK Source Divider 5"]
#[inline(always)]
pub fn divs_5(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs5)
}
#[doc = "SMCLK Source Divider 6"]
#[inline(always)]
pub fn divs_6(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs6)
}
#[doc = "SMCLK Source Divider 7"]
#[inline(always)]
pub fn divs_7(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs7)
}
}
#[doc = "ACLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Diva {
#[doc = "0: ACLK Source Divider 0"]
Diva0 = 0,
#[doc = "1: ACLK Source Divider 1"]
Diva1 = 1,
#[doc = "2: ACLK Source Divider 2"]
Diva2 = 2,
#[doc = "3: ACLK Source Divider 3"]
Diva3 = 3,
#[doc = "4: ACLK Source Divider 4"]
Diva4 = 4,
#[doc = "5: ACLK Source Divider 5"]
Diva5 = 5,
#[doc = "6: ACLK Source Divider 6"]
Diva6 = 6,
#[doc = "7: ACLK Source Divider 7"]
Diva7 = 7,
}
impl From<Diva> for u8 {
#[inline(always)]
fn from(variant: Diva) -> Self {
variant as _
}
}
impl crate::FieldSpec for Diva {
type Ux = u8;
}
impl crate::IsEnum for Diva {}
#[doc = "Field `DIVA` reader - ACLK Divider Bit: 0"]
pub type DivaR = crate::FieldReader<Diva>;
impl DivaR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Diva {
match self.bits {
0 => Diva::Diva0,
1 => Diva::Diva1,
2 => Diva::Diva2,
3 => Diva::Diva3,
4 => Diva::Diva4,
5 => Diva::Diva5,
6 => Diva::Diva6,
7 => Diva::Diva7,
_ => unreachable!(),
}
}
#[doc = "ACLK Source Divider 0"]
#[inline(always)]
pub fn is_diva_0(&self) -> bool {
*self == Diva::Diva0
}
#[doc = "ACLK Source Divider 1"]
#[inline(always)]
pub fn is_diva_1(&self) -> bool {
*self == Diva::Diva1
}
#[doc = "ACLK Source Divider 2"]
#[inline(always)]
pub fn is_diva_2(&self) -> bool {
*self == Diva::Diva2
}
#[doc = "ACLK Source Divider 3"]
#[inline(always)]
pub fn is_diva_3(&self) -> bool {
*self == Diva::Diva3
}
#[doc = "ACLK Source Divider 4"]
#[inline(always)]
pub fn is_diva_4(&self) -> bool {
*self == Diva::Diva4
}
#[doc = "ACLK Source Divider 5"]
#[inline(always)]
pub fn is_diva_5(&self) -> bool {
*self == Diva::Diva5
}
#[doc = "ACLK Source Divider 6"]
#[inline(always)]
pub fn is_diva_6(&self) -> bool {
*self == Diva::Diva6
}
#[doc = "ACLK Source Divider 7"]
#[inline(always)]
pub fn is_diva_7(&self) -> bool {
*self == Diva::Diva7
}
}
#[doc = "Field `DIVA` writer - ACLK Divider Bit: 0"]
pub type DivaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Diva, crate::Safe>;
impl<'a, REG> DivaW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ACLK Source Divider 0"]
#[inline(always)]
pub fn diva_0(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva0)
}
#[doc = "ACLK Source Divider 1"]
#[inline(always)]
pub fn diva_1(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva1)
}
#[doc = "ACLK Source Divider 2"]
#[inline(always)]
pub fn diva_2(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva2)
}
#[doc = "ACLK Source Divider 3"]
#[inline(always)]
pub fn diva_3(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva3)
}
#[doc = "ACLK Source Divider 4"]
#[inline(always)]
pub fn diva_4(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva4)
}
#[doc = "ACLK Source Divider 5"]
#[inline(always)]
pub fn diva_5(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva5)
}
#[doc = "ACLK Source Divider 6"]
#[inline(always)]
pub fn diva_6(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva6)
}
#[doc = "ACLK Source Divider 7"]
#[inline(always)]
pub fn diva_7(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva7)
}
}
#[doc = "ACLK from Pin Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Divpa {
#[doc = "0: ACLK from Pin Source Divider 0"]
Divpa0 = 0,
#[doc = "1: ACLK from Pin Source Divider 1"]
Divpa1 = 1,
#[doc = "2: ACLK from Pin Source Divider 2"]
Divpa2 = 2,
#[doc = "3: ACLK from Pin Source Divider 3"]
Divpa3 = 3,
#[doc = "4: ACLK from Pin Source Divider 4"]
Divpa4 = 4,
#[doc = "5: ACLK from Pin Source Divider 5"]
Divpa5 = 5,
#[doc = "6: ACLK from Pin Source Divider 6"]
Divpa6 = 6,
#[doc = "7: ACLK from Pin Source Divider 7"]
Divpa7 = 7,
}
impl From<Divpa> for u8 {
#[inline(always)]
fn from(variant: Divpa) -> Self {
variant as _
}
}
impl crate::FieldSpec for Divpa {
type Ux = u8;
}
impl crate::IsEnum for Divpa {}
#[doc = "Field `DIVPA` reader - ACLK from Pin Divider Bit: 0"]
pub type DivpaR = crate::FieldReader<Divpa>;
impl DivpaR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Divpa {
match self.bits {
0 => Divpa::Divpa0,
1 => Divpa::Divpa1,
2 => Divpa::Divpa2,
3 => Divpa::Divpa3,
4 => Divpa::Divpa4,
5 => Divpa::Divpa5,
6 => Divpa::Divpa6,
7 => Divpa::Divpa7,
_ => unreachable!(),
}
}
#[doc = "ACLK from Pin Source Divider 0"]
#[inline(always)]
pub fn is_divpa_0(&self) -> bool {
*self == Divpa::Divpa0
}
#[doc = "ACLK from Pin Source Divider 1"]
#[inline(always)]
pub fn is_divpa_1(&self) -> bool {
*self == Divpa::Divpa1
}
#[doc = "ACLK from Pin Source Divider 2"]
#[inline(always)]
pub fn is_divpa_2(&self) -> bool {
*self == Divpa::Divpa2
}
#[doc = "ACLK from Pin Source Divider 3"]
#[inline(always)]
pub fn is_divpa_3(&self) -> bool {
*self == Divpa::Divpa3
}
#[doc = "ACLK from Pin Source Divider 4"]
#[inline(always)]
pub fn is_divpa_4(&self) -> bool {
*self == Divpa::Divpa4
}
#[doc = "ACLK from Pin Source Divider 5"]
#[inline(always)]
pub fn is_divpa_5(&self) -> bool {
*self == Divpa::Divpa5
}
#[doc = "ACLK from Pin Source Divider 6"]
#[inline(always)]
pub fn is_divpa_6(&self) -> bool {
*self == Divpa::Divpa6
}
#[doc = "ACLK from Pin Source Divider 7"]
#[inline(always)]
pub fn is_divpa_7(&self) -> bool {
*self == Divpa::Divpa7
}
}
#[doc = "Field `DIVPA` writer - ACLK from Pin Divider Bit: 0"]
pub type DivpaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Divpa, crate::Safe>;
impl<'a, REG> DivpaW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ACLK from Pin Source Divider 0"]
#[inline(always)]
pub fn divpa_0(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa0)
}
#[doc = "ACLK from Pin Source Divider 1"]
#[inline(always)]
pub fn divpa_1(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa1)
}
#[doc = "ACLK from Pin Source Divider 2"]
#[inline(always)]
pub fn divpa_2(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa2)
}
#[doc = "ACLK from Pin Source Divider 3"]
#[inline(always)]
pub fn divpa_3(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa3)
}
#[doc = "ACLK from Pin Source Divider 4"]
#[inline(always)]
pub fn divpa_4(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa4)
}
#[doc = "ACLK from Pin Source Divider 5"]
#[inline(always)]
pub fn divpa_5(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa5)
}
#[doc = "ACLK from Pin Source Divider 6"]
#[inline(always)]
pub fn divpa_6(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa6)
}
#[doc = "ACLK from Pin Source Divider 7"]
#[inline(always)]
pub fn divpa_7(self) -> &'a mut crate::W<REG> {
self.variant(Divpa::Divpa7)
}
}
impl R {
#[doc = "Bits 0:2 - MCLK Divider Bit: 0"]
#[inline(always)]
pub fn divm(&self) -> DivmR {
DivmR::new((self.bits & 7) as u8)
}
#[doc = "Bits 4:6 - SMCLK Divider Bit: 0"]
#[inline(always)]
pub fn divs(&self) -> DivsR {
DivsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10 - ACLK Divider Bit: 0"]
#[inline(always)]
pub fn diva(&self) -> DivaR {
DivaR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 12:14 - ACLK from Pin Divider Bit: 0"]
#[inline(always)]
pub fn divpa(&self) -> DivpaR {
DivpaR::new(((self.bits >> 12) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - MCLK Divider Bit: 0"]
#[inline(always)]
pub fn divm(&mut self) -> DivmW<'_, Ucsctl5Spec> {
DivmW::new(self, 0)
}
#[doc = "Bits 4:6 - SMCLK Divider Bit: 0"]
#[inline(always)]
pub fn divs(&mut self) -> DivsW<'_, Ucsctl5Spec> {
DivsW::new(self, 4)
}
#[doc = "Bits 8:10 - ACLK Divider Bit: 0"]
#[inline(always)]
pub fn diva(&mut self) -> DivaW<'_, Ucsctl5Spec> {
DivaW::new(self, 8)
}
#[doc = "Bits 12:14 - ACLK from Pin Divider Bit: 0"]
#[inline(always)]
pub fn divpa(&mut self) -> DivpaW<'_, Ucsctl5Spec> {
DivpaW::new(self, 12)
}
}
#[doc = "UCS Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`ucsctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucsctl5Spec;
impl crate::RegisterSpec for Ucsctl5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucsctl5::R`](R) reader structure"]
impl crate::Readable for Ucsctl5Spec {}
#[doc = "`write(|w| ..)` method takes [`ucsctl5::W`](W) writer structure"]
impl crate::Writable for Ucsctl5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCSCTL5 to value 0"]
impl crate::Resettable for Ucsctl5Spec {}