cc430f5137 0.1.0

#[doc = "Register `UCSCTL1` reader"]
pub type R = crate::R<Ucsctl1Spec>;
#[doc = "Register `UCSCTL1` writer"]
pub type W = crate::W<Ucsctl1Spec>;
#[doc = "Field `DISMOD` reader - Disable Modulation"]
pub type DismodR = crate::BitReader;
#[doc = "Field `DISMOD` writer - Disable Modulation"]
pub type DismodW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "DCO Freq. Range Select Bit : 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dcorsel {
    #[doc = "0: DCO RSEL 0"]
    Dcorsel0 = 0,
    #[doc = "1: DCO RSEL 1"]
    Dcorsel1 = 1,
    #[doc = "2: DCO RSEL 2"]
    Dcorsel2 = 2,
    #[doc = "3: DCO RSEL 3"]
    Dcorsel3 = 3,
    #[doc = "4: DCO RSEL 4"]
    Dcorsel4 = 4,
    #[doc = "5: DCO RSEL 5"]
    Dcorsel5 = 5,
    #[doc = "6: DCO RSEL 6"]
    Dcorsel6 = 6,
    #[doc = "7: DCO RSEL 7"]
    Dcorsel7 = 7,
}
impl From<Dcorsel> for u8 {
    #[inline(always)]
    fn from(variant: Dcorsel) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for Dcorsel {
    type Ux = u8;
}
impl crate::IsEnum for Dcorsel {}
#[doc = "Field `DCORSEL` reader - DCO Freq. Range Select Bit : 0"]
pub type DcorselR = crate::FieldReader<Dcorsel>;
impl DcorselR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Dcorsel {
        match self.bits {
            0 => Dcorsel::Dcorsel0,
            1 => Dcorsel::Dcorsel1,
            2 => Dcorsel::Dcorsel2,
            3 => Dcorsel::Dcorsel3,
            4 => Dcorsel::Dcorsel4,
            5 => Dcorsel::Dcorsel5,
            6 => Dcorsel::Dcorsel6,
            7 => Dcorsel::Dcorsel7,
            _ => unreachable!(),
        }
    }
    #[doc = "DCO RSEL 0"]
    #[inline(always)]
    pub fn is_dcorsel_0(&self) -> bool {
        *self == Dcorsel::Dcorsel0
    }
    #[doc = "DCO RSEL 1"]
    #[inline(always)]
    pub fn is_dcorsel_1(&self) -> bool {
        *self == Dcorsel::Dcorsel1
    }
    #[doc = "DCO RSEL 2"]
    #[inline(always)]
    pub fn is_dcorsel_2(&self) -> bool {
        *self == Dcorsel::Dcorsel2
    }
    #[doc = "DCO RSEL 3"]
    #[inline(always)]
    pub fn is_dcorsel_3(&self) -> bool {
        *self == Dcorsel::Dcorsel3
    }
    #[doc = "DCO RSEL 4"]
    #[inline(always)]
    pub fn is_dcorsel_4(&self) -> bool {
        *self == Dcorsel::Dcorsel4
    }
    #[doc = "DCO RSEL 5"]
    #[inline(always)]
    pub fn is_dcorsel_5(&self) -> bool {
        *self == Dcorsel::Dcorsel5
    }
    #[doc = "DCO RSEL 6"]
    #[inline(always)]
    pub fn is_dcorsel_6(&self) -> bool {
        *self == Dcorsel::Dcorsel6
    }
    #[doc = "DCO RSEL 7"]
    #[inline(always)]
    pub fn is_dcorsel_7(&self) -> bool {
        *self == Dcorsel::Dcorsel7
    }
}
#[doc = "Field `DCORSEL` writer - DCO Freq. Range Select Bit : 0"]
pub type DcorselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dcorsel, crate::Safe>;
impl<'a, REG> DcorselW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    #[doc = "DCO RSEL 0"]
    #[inline(always)]
    pub fn dcorsel_0(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel0)
    }
    #[doc = "DCO RSEL 1"]
    #[inline(always)]
    pub fn dcorsel_1(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel1)
    }
    #[doc = "DCO RSEL 2"]
    #[inline(always)]
    pub fn dcorsel_2(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel2)
    }
    #[doc = "DCO RSEL 3"]
    #[inline(always)]
    pub fn dcorsel_3(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel3)
    }
    #[doc = "DCO RSEL 4"]
    #[inline(always)]
    pub fn dcorsel_4(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel4)
    }
    #[doc = "DCO RSEL 5"]
    #[inline(always)]
    pub fn dcorsel_5(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel5)
    }
    #[doc = "DCO RSEL 6"]
    #[inline(always)]
    pub fn dcorsel_6(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel6)
    }
    #[doc = "DCO RSEL 7"]
    #[inline(always)]
    pub fn dcorsel_7(self) -> &'a mut crate::W<REG> {
        self.variant(Dcorsel::Dcorsel7)
    }
}
impl R {
    #[doc = "Bit 0 - Disable Modulation"]
    #[inline(always)]
    pub fn dismod(&self) -> DismodR {
        DismodR::new((self.bits & 1) != 0)
    }
    #[doc = "Bits 4:6 - DCO Freq. Range Select Bit : 0"]
    #[inline(always)]
    pub fn dcorsel(&self) -> DcorselR {
        DcorselR::new(((self.bits >> 4) & 7) as u8)
    }
}
impl W {
    #[doc = "Bit 0 - Disable Modulation"]
    #[inline(always)]
    pub fn dismod(&mut self) -> DismodW<'_, Ucsctl1Spec> {
        DismodW::new(self, 0)
    }
    #[doc = "Bits 4:6 - DCO Freq. Range Select Bit : 0"]
    #[inline(always)]
    pub fn dcorsel(&mut self) -> DcorselW<'_, Ucsctl1Spec> {
        DcorselW::new(self, 4)
    }
}
#[doc = "UCS Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucsctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucsctl1Spec;
impl crate::RegisterSpec for Ucsctl1Spec {
    type Ux = u16;
}
#[doc = "`read()` method returns [`ucsctl1::R`](R) reader structure"]
impl crate::Readable for Ucsctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ucsctl1::W`](W) writer structure"]
impl crate::Writable for Ucsctl1Spec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCSCTL1 to value 0"]
impl crate::Resettable for Ucsctl1Spec {}