#[doc = "Register `UCSCTL6` reader"]
pub type R = crate::R<Ucsctl6Spec>;
#[doc = "Register `UCSCTL6` writer"]
pub type W = crate::W<Ucsctl6Spec>;
#[doc = "Field `XT1OFF` reader - High Frequency Oscillator 1 (XT1) disable"]
pub type Xt1offR = crate::BitReader;
#[doc = "Field `XT1OFF` writer - High Frequency Oscillator 1 (XT1) disable"]
pub type Xt1offW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMCLKOFF` reader - SMCLK Off"]
pub type SmclkoffR = crate::BitReader;
#[doc = "Field `SMCLKOFF` writer - SMCLK Off"]
pub type SmclkoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "XIN/XOUT Cap Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Xcap {
#[doc = "0: XIN/XOUT Cap 0"]
Xcap0 = 0,
#[doc = "1: XIN/XOUT Cap 1"]
Xcap1 = 1,
#[doc = "2: XIN/XOUT Cap 2"]
Xcap2 = 2,
#[doc = "3: XIN/XOUT Cap 3"]
Xcap3 = 3,
}
impl From<Xcap> for u8 {
#[inline(always)]
fn from(variant: Xcap) -> Self {
variant as _
}
}
impl crate::FieldSpec for Xcap {
type Ux = u8;
}
impl crate::IsEnum for Xcap {}
#[doc = "Field `XCAP` reader - XIN/XOUT Cap Bit: 0"]
pub type XcapR = crate::FieldReader<Xcap>;
impl XcapR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Xcap {
match self.bits {
0 => Xcap::Xcap0,
1 => Xcap::Xcap1,
2 => Xcap::Xcap2,
3 => Xcap::Xcap3,
_ => unreachable!(),
}
}
#[doc = "XIN/XOUT Cap 0"]
#[inline(always)]
pub fn is_xcap_0(&self) -> bool {
*self == Xcap::Xcap0
}
#[doc = "XIN/XOUT Cap 1"]
#[inline(always)]
pub fn is_xcap_1(&self) -> bool {
*self == Xcap::Xcap1
}
#[doc = "XIN/XOUT Cap 2"]
#[inline(always)]
pub fn is_xcap_2(&self) -> bool {
*self == Xcap::Xcap2
}
#[doc = "XIN/XOUT Cap 3"]
#[inline(always)]
pub fn is_xcap_3(&self) -> bool {
*self == Xcap::Xcap3
}
}
#[doc = "Field `XCAP` writer - XIN/XOUT Cap Bit: 0"]
pub type XcapW<'a, REG> = crate::FieldWriter<'a, REG, 2, Xcap, crate::Safe>;
impl<'a, REG> XcapW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "XIN/XOUT Cap 0"]
#[inline(always)]
pub fn xcap_0(self) -> &'a mut crate::W<REG> {
self.variant(Xcap::Xcap0)
}
#[doc = "XIN/XOUT Cap 1"]
#[inline(always)]
pub fn xcap_1(self) -> &'a mut crate::W<REG> {
self.variant(Xcap::Xcap1)
}
#[doc = "XIN/XOUT Cap 2"]
#[inline(always)]
pub fn xcap_2(self) -> &'a mut crate::W<REG> {
self.variant(Xcap::Xcap2)
}
#[doc = "XIN/XOUT Cap 3"]
#[inline(always)]
pub fn xcap_3(self) -> &'a mut crate::W<REG> {
self.variant(Xcap::Xcap3)
}
}
#[doc = "Field `XT1BYPASS` reader - XT1 bypass mode : 0: internal 1:sourced from external pin"]
pub type Xt1bypassR = crate::BitReader;
#[doc = "Field `XT1BYPASS` writer - XT1 bypass mode : 0: internal 1:sourced from external pin"]
pub type Xt1bypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `XTS` reader - 1: Selects high-freq. oscillator"]
pub type XtsR = crate::BitReader;
#[doc = "Field `XTS` writer - 1: Selects high-freq. oscillator"]
pub type XtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "XT1 Drive Level mode Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Xt1drive {
#[doc = "0: XT1 Drive Level mode: 0"]
Xt1drive0 = 0,
#[doc = "1: XT1 Drive Level mode: 1"]
Xt1drive1 = 1,
#[doc = "2: XT1 Drive Level mode: 2"]
Xt1drive2 = 2,
#[doc = "3: XT1 Drive Level mode: 3"]
Xt1drive3 = 3,
}
impl From<Xt1drive> for u8 {
#[inline(always)]
fn from(variant: Xt1drive) -> Self {
variant as _
}
}
impl crate::FieldSpec for Xt1drive {
type Ux = u8;
}
impl crate::IsEnum for Xt1drive {}
#[doc = "Field `XT1DRIVE` reader - XT1 Drive Level mode Bit 0"]
pub type Xt1driveR = crate::FieldReader<Xt1drive>;
impl Xt1driveR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Xt1drive {
match self.bits {
0 => Xt1drive::Xt1drive0,
1 => Xt1drive::Xt1drive1,
2 => Xt1drive::Xt1drive2,
3 => Xt1drive::Xt1drive3,
_ => unreachable!(),
}
}
#[doc = "XT1 Drive Level mode: 0"]
#[inline(always)]
pub fn is_xt1drive_0(&self) -> bool {
*self == Xt1drive::Xt1drive0
}
#[doc = "XT1 Drive Level mode: 1"]
#[inline(always)]
pub fn is_xt1drive_1(&self) -> bool {
*self == Xt1drive::Xt1drive1
}
#[doc = "XT1 Drive Level mode: 2"]
#[inline(always)]
pub fn is_xt1drive_2(&self) -> bool {
*self == Xt1drive::Xt1drive2
}
#[doc = "XT1 Drive Level mode: 3"]
#[inline(always)]
pub fn is_xt1drive_3(&self) -> bool {
*self == Xt1drive::Xt1drive3
}
}
#[doc = "Field `XT1DRIVE` writer - XT1 Drive Level mode Bit 0"]
pub type Xt1driveW<'a, REG> = crate::FieldWriter<'a, REG, 2, Xt1drive, crate::Safe>;
impl<'a, REG> Xt1driveW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "XT1 Drive Level mode: 0"]
#[inline(always)]
pub fn xt1drive_0(self) -> &'a mut crate::W<REG> {
self.variant(Xt1drive::Xt1drive0)
}
#[doc = "XT1 Drive Level mode: 1"]
#[inline(always)]
pub fn xt1drive_1(self) -> &'a mut crate::W<REG> {
self.variant(Xt1drive::Xt1drive1)
}
#[doc = "XT1 Drive Level mode: 2"]
#[inline(always)]
pub fn xt1drive_2(self) -> &'a mut crate::W<REG> {
self.variant(Xt1drive::Xt1drive2)
}
#[doc = "XT1 Drive Level mode: 3"]
#[inline(always)]
pub fn xt1drive_3(self) -> &'a mut crate::W<REG> {
self.variant(Xt1drive::Xt1drive3)
}
}
#[doc = "Field `XT2OFF` reader - High Frequency Oscillator 2 (XT2) disable"]
pub type Xt2offR = crate::BitReader;
#[doc = "Field `XT2OFF` writer - High Frequency Oscillator 2 (XT2) disable"]
pub type Xt2offW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - High Frequency Oscillator 1 (XT1) disable"]
#[inline(always)]
pub fn xt1off(&self) -> Xt1offR {
Xt1offR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SMCLK Off"]
#[inline(always)]
pub fn smclkoff(&self) -> SmclkoffR {
SmclkoffR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3 - XIN/XOUT Cap Bit: 0"]
#[inline(always)]
pub fn xcap(&self) -> XcapR {
XcapR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - XT1 bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn xt1bypass(&self) -> Xt1bypassR {
Xt1bypassR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 1: Selects high-freq. oscillator"]
#[inline(always)]
pub fn xts(&self) -> XtsR {
XtsR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - XT1 Drive Level mode Bit 0"]
#[inline(always)]
pub fn xt1drive(&self) -> Xt1driveR {
Xt1driveR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - High Frequency Oscillator 2 (XT2) disable"]
#[inline(always)]
pub fn xt2off(&self) -> Xt2offR {
Xt2offR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - High Frequency Oscillator 1 (XT1) disable"]
#[inline(always)]
pub fn xt1off(&mut self) -> Xt1offW<'_, Ucsctl6Spec> {
Xt1offW::new(self, 0)
}
#[doc = "Bit 1 - SMCLK Off"]
#[inline(always)]
pub fn smclkoff(&mut self) -> SmclkoffW<'_, Ucsctl6Spec> {
SmclkoffW::new(self, 1)
}
#[doc = "Bits 2:3 - XIN/XOUT Cap Bit: 0"]
#[inline(always)]
pub fn xcap(&mut self) -> XcapW<'_, Ucsctl6Spec> {
XcapW::new(self, 2)
}
#[doc = "Bit 4 - XT1 bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn xt1bypass(&mut self) -> Xt1bypassW<'_, Ucsctl6Spec> {
Xt1bypassW::new(self, 4)
}
#[doc = "Bit 5 - 1: Selects high-freq. oscillator"]
#[inline(always)]
pub fn xts(&mut self) -> XtsW<'_, Ucsctl6Spec> {
XtsW::new(self, 5)
}
#[doc = "Bits 6:7 - XT1 Drive Level mode Bit 0"]
#[inline(always)]
pub fn xt1drive(&mut self) -> Xt1driveW<'_, Ucsctl6Spec> {
Xt1driveW::new(self, 6)
}
#[doc = "Bit 8 - High Frequency Oscillator 2 (XT2) disable"]
#[inline(always)]
pub fn xt2off(&mut self) -> Xt2offW<'_, Ucsctl6Spec> {
Xt2offW::new(self, 8)
}
}
#[doc = "UCS Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`ucsctl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsctl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucsctl6Spec;
impl crate::RegisterSpec for Ucsctl6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucsctl6::R`](R) reader structure"]
impl crate::Readable for Ucsctl6Spec {}
#[doc = "`write(|w| ..)` method takes [`ucsctl6::W`](W) writer structure"]
impl crate::Writable for Ucsctl6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCSCTL6 to value 0"]
impl crate::Resettable for Ucsctl6Spec {}