#[doc = "Register `ADC12MCTL1` reader"]
pub type R = crate::R<Adc12mctl1Spec>;
#[doc = "Register `ADC12MCTL1` writer"]
pub type W = crate::W<Adc12mctl1Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
}
#[doc = "ADC12 Select Reference Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12sref {
#[doc = "0: ADC12 Select Reference 0"]
Adc12sref0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12sref1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12sref2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12sref3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12sref4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12sref5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12sref6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12sref7 = 7,
}
impl From<Adc12sref> for u8 {
#[inline(always)]
fn from(variant: Adc12sref) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12sref {
type Ux = u8;
}
impl crate::IsEnum for Adc12sref {}
#[doc = "Field `ADC12SREF` reader - ADC12 Select Reference Bit 0"]
pub type Adc12srefR = crate::FieldReader<Adc12sref>;
impl Adc12srefR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12sref {
match self.bits {
0 => Adc12sref::Adc12sref0,
1 => Adc12sref::Adc12sref1,
2 => Adc12sref::Adc12sref2,
3 => Adc12sref::Adc12sref3,
4 => Adc12sref::Adc12sref4,
5 => Adc12sref::Adc12sref5,
6 => Adc12sref::Adc12sref6,
7 => Adc12sref::Adc12sref7,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12sref_0(&self) -> bool {
*self == Adc12sref::Adc12sref0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12sref_1(&self) -> bool {
*self == Adc12sref::Adc12sref1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12sref_2(&self) -> bool {
*self == Adc12sref::Adc12sref2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12sref_3(&self) -> bool {
*self == Adc12sref::Adc12sref3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12sref_4(&self) -> bool {
*self == Adc12sref::Adc12sref4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12sref_5(&self) -> bool {
*self == Adc12sref::Adc12sref5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12sref_6(&self) -> bool {
*self == Adc12sref::Adc12sref6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12sref_7(&self) -> bool {
*self == Adc12sref::Adc12sref7
}
}
#[doc = "Field `ADC12SREF` writer - ADC12 Select Reference Bit 0"]
pub type Adc12srefW<'a, REG> = crate::FieldWriter<'a, REG, 3, Adc12sref, crate::Safe>;
impl<'a, REG> Adc12srefW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12sref_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12sref_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12sref_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12sref_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12sref_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12sref_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12sref_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12sref_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sref::Adc12sref7)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new(self.bits & 0x0f)
}
#[doc = "Bits 4:6 - ADC12 Select Reference Bit 0"]
#[inline(always)]
pub fn adc12sref(&self) -> Adc12srefR {
Adc12srefR::new((self.bits >> 4) & 7)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl1Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bits 4:6 - ADC12 Select Reference Bit 0"]
#[inline(always)]
pub fn adc12sref(&mut self) -> Adc12srefW<'_, Adc12mctl1Spec> {
Adc12srefW::new(self, 4)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl1Spec> {
Adc12eosW::new(self, 7)
}
}
#[doc = "ADC12 Memory Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl1Spec;
impl crate::RegisterSpec for Adc12mctl1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`adc12mctl1::R`](R) reader structure"]
impl crate::Readable for Adc12mctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl1::W`](W) writer structure"]
impl crate::Writable for Adc12mctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL1 to value 0"]
impl crate::Resettable for Adc12mctl1Spec {}