#[doc = "Register `ADC12CTL1` reader"]
pub type R = crate::R<Adc12ctl1Spec>;
#[doc = "Register `ADC12CTL1` writer"]
pub type W = crate::W<Adc12ctl1Spec>;
#[doc = "Field `ADC12BUSY` reader - ADC12 Busy"]
pub type Adc12busyR = crate::BitReader;
#[doc = "Field `ADC12BUSY` writer - ADC12 Busy"]
pub type Adc12busyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Conversion Sequence Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12conseq {
#[doc = "0: ADC12 Conversion Sequence Select: 0"]
Adc12conseq0 = 0,
#[doc = "1: ADC12 Conversion Sequence Select: 1"]
Adc12conseq1 = 1,
#[doc = "2: ADC12 Conversion Sequence Select: 2"]
Adc12conseq2 = 2,
#[doc = "3: ADC12 Conversion Sequence Select: 3"]
Adc12conseq3 = 3,
}
impl From<Adc12conseq> for u8 {
#[inline(always)]
fn from(variant: Adc12conseq) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12conseq {
type Ux = u8;
}
impl crate::IsEnum for Adc12conseq {}
#[doc = "Field `ADC12CONSEQ` reader - ADC12 Conversion Sequence Select Bit: 0"]
pub type Adc12conseqR = crate::FieldReader<Adc12conseq>;
impl Adc12conseqR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12conseq {
match self.bits {
0 => Adc12conseq::Adc12conseq0,
1 => Adc12conseq::Adc12conseq1,
2 => Adc12conseq::Adc12conseq2,
3 => Adc12conseq::Adc12conseq3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Conversion Sequence Select: 0"]
#[inline(always)]
pub fn is_adc12conseq_0(&self) -> bool {
*self == Adc12conseq::Adc12conseq0
}
#[doc = "ADC12 Conversion Sequence Select: 1"]
#[inline(always)]
pub fn is_adc12conseq_1(&self) -> bool {
*self == Adc12conseq::Adc12conseq1
}
#[doc = "ADC12 Conversion Sequence Select: 2"]
#[inline(always)]
pub fn is_adc12conseq_2(&self) -> bool {
*self == Adc12conseq::Adc12conseq2
}
#[doc = "ADC12 Conversion Sequence Select: 3"]
#[inline(always)]
pub fn is_adc12conseq_3(&self) -> bool {
*self == Adc12conseq::Adc12conseq3
}
}
#[doc = "Field `ADC12CONSEQ` writer - ADC12 Conversion Sequence Select Bit: 0"]
pub type Adc12conseqW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12conseq, crate::Safe>;
impl<'a, REG> Adc12conseqW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Conversion Sequence Select: 0"]
#[inline(always)]
pub fn adc12conseq_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq0)
}
#[doc = "ADC12 Conversion Sequence Select: 1"]
#[inline(always)]
pub fn adc12conseq_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq1)
}
#[doc = "ADC12 Conversion Sequence Select: 2"]
#[inline(always)]
pub fn adc12conseq_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq2)
}
#[doc = "ADC12 Conversion Sequence Select: 3"]
#[inline(always)]
pub fn adc12conseq_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq3)
}
}
#[doc = "ADC12 Clock Source Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12ssel {
#[doc = "0: ADC12 Clock Source Select: 0"]
Adc12ssel0 = 0,
#[doc = "1: ADC12 Clock Source Select: 1"]
Adc12ssel1 = 1,
#[doc = "2: ADC12 Clock Source Select: 2"]
Adc12ssel2 = 2,
#[doc = "3: ADC12 Clock Source Select: 3"]
Adc12ssel3 = 3,
}
impl From<Adc12ssel> for u8 {
#[inline(always)]
fn from(variant: Adc12ssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12ssel {
type Ux = u8;
}
impl crate::IsEnum for Adc12ssel {}
#[doc = "Field `ADC12SSEL` reader - ADC12 Clock Source Select Bit: 0"]
pub type Adc12sselR = crate::FieldReader<Adc12ssel>;
impl Adc12sselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12ssel {
match self.bits {
0 => Adc12ssel::Adc12ssel0,
1 => Adc12ssel::Adc12ssel1,
2 => Adc12ssel::Adc12ssel2,
3 => Adc12ssel::Adc12ssel3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Clock Source Select: 0"]
#[inline(always)]
pub fn is_adc12ssel_0(&self) -> bool {
*self == Adc12ssel::Adc12ssel0
}
#[doc = "ADC12 Clock Source Select: 1"]
#[inline(always)]
pub fn is_adc12ssel_1(&self) -> bool {
*self == Adc12ssel::Adc12ssel1
}
#[doc = "ADC12 Clock Source Select: 2"]
#[inline(always)]
pub fn is_adc12ssel_2(&self) -> bool {
*self == Adc12ssel::Adc12ssel2
}
#[doc = "ADC12 Clock Source Select: 3"]
#[inline(always)]
pub fn is_adc12ssel_3(&self) -> bool {
*self == Adc12ssel::Adc12ssel3
}
}
#[doc = "Field `ADC12SSEL` writer - ADC12 Clock Source Select Bit: 0"]
pub type Adc12sselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12ssel, crate::Safe>;
impl<'a, REG> Adc12sselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Clock Source Select: 0"]
#[inline(always)]
pub fn adc12ssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel0)
}
#[doc = "ADC12 Clock Source Select: 1"]
#[inline(always)]
pub fn adc12ssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel1)
}
#[doc = "ADC12 Clock Source Select: 2"]
#[inline(always)]
pub fn adc12ssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel2)
}
#[doc = "ADC12 Clock Source Select: 3"]
#[inline(always)]
pub fn adc12ssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel3)
}
}
#[doc = "ADC12 Clock Divider Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12div {
#[doc = "0: ADC12 Clock Divider Select: 0"]
Adc12div0 = 0,
#[doc = "1: ADC12 Clock Divider Select: 1"]
Adc12div1 = 1,
#[doc = "2: ADC12 Clock Divider Select: 2"]
Adc12div2 = 2,
#[doc = "3: ADC12 Clock Divider Select: 3"]
Adc12div3 = 3,
#[doc = "4: ADC12 Clock Divider Select: 4"]
Adc12div4 = 4,
#[doc = "5: ADC12 Clock Divider Select: 5"]
Adc12div5 = 5,
#[doc = "6: ADC12 Clock Divider Select: 6"]
Adc12div6 = 6,
#[doc = "7: ADC12 Clock Divider Select: 7"]
Adc12div7 = 7,
}
impl From<Adc12div> for u8 {
#[inline(always)]
fn from(variant: Adc12div) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12div {
type Ux = u8;
}
impl crate::IsEnum for Adc12div {}
#[doc = "Field `ADC12DIV` reader - ADC12 Clock Divider Select Bit: 0"]
pub type Adc12divR = crate::FieldReader<Adc12div>;
impl Adc12divR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12div {
match self.bits {
0 => Adc12div::Adc12div0,
1 => Adc12div::Adc12div1,
2 => Adc12div::Adc12div2,
3 => Adc12div::Adc12div3,
4 => Adc12div::Adc12div4,
5 => Adc12div::Adc12div5,
6 => Adc12div::Adc12div6,
7 => Adc12div::Adc12div7,
_ => unreachable!(),
}
}
#[doc = "ADC12 Clock Divider Select: 0"]
#[inline(always)]
pub fn is_adc12div_0(&self) -> bool {
*self == Adc12div::Adc12div0
}
#[doc = "ADC12 Clock Divider Select: 1"]
#[inline(always)]
pub fn is_adc12div_1(&self) -> bool {
*self == Adc12div::Adc12div1
}
#[doc = "ADC12 Clock Divider Select: 2"]
#[inline(always)]
pub fn is_adc12div_2(&self) -> bool {
*self == Adc12div::Adc12div2
}
#[doc = "ADC12 Clock Divider Select: 3"]
#[inline(always)]
pub fn is_adc12div_3(&self) -> bool {
*self == Adc12div::Adc12div3
}
#[doc = "ADC12 Clock Divider Select: 4"]
#[inline(always)]
pub fn is_adc12div_4(&self) -> bool {
*self == Adc12div::Adc12div4
}
#[doc = "ADC12 Clock Divider Select: 5"]
#[inline(always)]
pub fn is_adc12div_5(&self) -> bool {
*self == Adc12div::Adc12div5
}
#[doc = "ADC12 Clock Divider Select: 6"]
#[inline(always)]
pub fn is_adc12div_6(&self) -> bool {
*self == Adc12div::Adc12div6
}
#[doc = "ADC12 Clock Divider Select: 7"]
#[inline(always)]
pub fn is_adc12div_7(&self) -> bool {
*self == Adc12div::Adc12div7
}
}
#[doc = "Field `ADC12DIV` writer - ADC12 Clock Divider Select Bit: 0"]
pub type Adc12divW<'a, REG> = crate::FieldWriter<'a, REG, 3, Adc12div, crate::Safe>;
impl<'a, REG> Adc12divW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Clock Divider Select: 0"]
#[inline(always)]
pub fn adc12div_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div0)
}
#[doc = "ADC12 Clock Divider Select: 1"]
#[inline(always)]
pub fn adc12div_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div1)
}
#[doc = "ADC12 Clock Divider Select: 2"]
#[inline(always)]
pub fn adc12div_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div2)
}
#[doc = "ADC12 Clock Divider Select: 3"]
#[inline(always)]
pub fn adc12div_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div3)
}
#[doc = "ADC12 Clock Divider Select: 4"]
#[inline(always)]
pub fn adc12div_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div4)
}
#[doc = "ADC12 Clock Divider Select: 5"]
#[inline(always)]
pub fn adc12div_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div5)
}
#[doc = "ADC12 Clock Divider Select: 6"]
#[inline(always)]
pub fn adc12div_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div6)
}
#[doc = "ADC12 Clock Divider Select: 7"]
#[inline(always)]
pub fn adc12div_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div7)
}
}
#[doc = "Field `ADC12ISSH` reader - ADC12 Invert Sample Hold Signal"]
pub type Adc12isshR = crate::BitReader;
#[doc = "Field `ADC12ISSH` writer - ADC12 Invert Sample Hold Signal"]
pub type Adc12isshW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12SHP` reader - ADC12 Sample/Hold Pulse Mode"]
pub type Adc12shpR = crate::BitReader;
#[doc = "Field `ADC12SHP` writer - ADC12 Sample/Hold Pulse Mode"]
pub type Adc12shpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Sample/Hold Source Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12shs {
#[doc = "0: ADC12 Sample/Hold Source: 0"]
Adc12shs0 = 0,
#[doc = "1: ADC12 Sample/Hold Source: 1"]
Adc12shs1 = 1,
#[doc = "2: ADC12 Sample/Hold Source: 2"]
Adc12shs2 = 2,
#[doc = "3: ADC12 Sample/Hold Source: 3"]
Adc12shs3 = 3,
}
impl From<Adc12shs> for u8 {
#[inline(always)]
fn from(variant: Adc12shs) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12shs {
type Ux = u8;
}
impl crate::IsEnum for Adc12shs {}
#[doc = "Field `ADC12SHS` reader - ADC12 Sample/Hold Source Bit: 0"]
pub type Adc12shsR = crate::FieldReader<Adc12shs>;
impl Adc12shsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12shs {
match self.bits {
0 => Adc12shs::Adc12shs0,
1 => Adc12shs::Adc12shs1,
2 => Adc12shs::Adc12shs2,
3 => Adc12shs::Adc12shs3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample/Hold Source: 0"]
#[inline(always)]
pub fn is_adc12shs_0(&self) -> bool {
*self == Adc12shs::Adc12shs0
}
#[doc = "ADC12 Sample/Hold Source: 1"]
#[inline(always)]
pub fn is_adc12shs_1(&self) -> bool {
*self == Adc12shs::Adc12shs1
}
#[doc = "ADC12 Sample/Hold Source: 2"]
#[inline(always)]
pub fn is_adc12shs_2(&self) -> bool {
*self == Adc12shs::Adc12shs2
}
#[doc = "ADC12 Sample/Hold Source: 3"]
#[inline(always)]
pub fn is_adc12shs_3(&self) -> bool {
*self == Adc12shs::Adc12shs3
}
}
#[doc = "Field `ADC12SHS` writer - ADC12 Sample/Hold Source Bit: 0"]
pub type Adc12shsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12shs, crate::Safe>;
impl<'a, REG> Adc12shsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample/Hold Source: 0"]
#[inline(always)]
pub fn adc12shs_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs0)
}
#[doc = "ADC12 Sample/Hold Source: 1"]
#[inline(always)]
pub fn adc12shs_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs1)
}
#[doc = "ADC12 Sample/Hold Source: 2"]
#[inline(always)]
pub fn adc12shs_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs2)
}
#[doc = "ADC12 Sample/Hold Source: 3"]
#[inline(always)]
pub fn adc12shs_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs3)
}
}
#[doc = "ADC12 Conversion Start Address Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12cstartadd {
#[doc = "0: ADC12 Conversion Start Address: 0"]
Adc12cstartadd0 = 0,
#[doc = "1: ADC12 Conversion Start Address: 1"]
Adc12cstartadd1 = 1,
#[doc = "2: ADC12 Conversion Start Address: 2"]
Adc12cstartadd2 = 2,
#[doc = "3: ADC12 Conversion Start Address: 3"]
Adc12cstartadd3 = 3,
#[doc = "4: ADC12 Conversion Start Address: 4"]
Adc12cstartadd4 = 4,
#[doc = "5: ADC12 Conversion Start Address: 5"]
Adc12cstartadd5 = 5,
#[doc = "6: ADC12 Conversion Start Address: 6"]
Adc12cstartadd6 = 6,
#[doc = "7: ADC12 Conversion Start Address: 7"]
Adc12cstartadd7 = 7,
#[doc = "8: ADC12 Conversion Start Address: 8"]
Adc12cstartadd8 = 8,
#[doc = "9: ADC12 Conversion Start Address: 9"]
Adc12cstartadd9 = 9,
#[doc = "10: ADC12 Conversion Start Address: 10"]
Adc12cstartadd10 = 10,
#[doc = "11: ADC12 Conversion Start Address: 11"]
Adc12cstartadd11 = 11,
#[doc = "12: ADC12 Conversion Start Address: 12"]
Adc12cstartadd12 = 12,
#[doc = "13: ADC12 Conversion Start Address: 13"]
Adc12cstartadd13 = 13,
#[doc = "14: ADC12 Conversion Start Address: 14"]
Adc12cstartadd14 = 14,
#[doc = "15: ADC12 Conversion Start Address: 15"]
Adc12cstartadd15 = 15,
}
impl From<Adc12cstartadd> for u8 {
#[inline(always)]
fn from(variant: Adc12cstartadd) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12cstartadd {
type Ux = u8;
}
impl crate::IsEnum for Adc12cstartadd {}
#[doc = "Field `ADC12CSTARTADD` reader - ADC12 Conversion Start Address Bit: 0"]
pub type Adc12cstartaddR = crate::FieldReader<Adc12cstartadd>;
impl Adc12cstartaddR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12cstartadd {
match self.bits {
0 => Adc12cstartadd::Adc12cstartadd0,
1 => Adc12cstartadd::Adc12cstartadd1,
2 => Adc12cstartadd::Adc12cstartadd2,
3 => Adc12cstartadd::Adc12cstartadd3,
4 => Adc12cstartadd::Adc12cstartadd4,
5 => Adc12cstartadd::Adc12cstartadd5,
6 => Adc12cstartadd::Adc12cstartadd6,
7 => Adc12cstartadd::Adc12cstartadd7,
8 => Adc12cstartadd::Adc12cstartadd8,
9 => Adc12cstartadd::Adc12cstartadd9,
10 => Adc12cstartadd::Adc12cstartadd10,
11 => Adc12cstartadd::Adc12cstartadd11,
12 => Adc12cstartadd::Adc12cstartadd12,
13 => Adc12cstartadd::Adc12cstartadd13,
14 => Adc12cstartadd::Adc12cstartadd14,
15 => Adc12cstartadd::Adc12cstartadd15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Conversion Start Address: 0"]
#[inline(always)]
pub fn is_adc12cstartadd_0(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd0
}
#[doc = "ADC12 Conversion Start Address: 1"]
#[inline(always)]
pub fn is_adc12cstartadd_1(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd1
}
#[doc = "ADC12 Conversion Start Address: 2"]
#[inline(always)]
pub fn is_adc12cstartadd_2(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd2
}
#[doc = "ADC12 Conversion Start Address: 3"]
#[inline(always)]
pub fn is_adc12cstartadd_3(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd3
}
#[doc = "ADC12 Conversion Start Address: 4"]
#[inline(always)]
pub fn is_adc12cstartadd_4(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd4
}
#[doc = "ADC12 Conversion Start Address: 5"]
#[inline(always)]
pub fn is_adc12cstartadd_5(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd5
}
#[doc = "ADC12 Conversion Start Address: 6"]
#[inline(always)]
pub fn is_adc12cstartadd_6(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd6
}
#[doc = "ADC12 Conversion Start Address: 7"]
#[inline(always)]
pub fn is_adc12cstartadd_7(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd7
}
#[doc = "ADC12 Conversion Start Address: 8"]
#[inline(always)]
pub fn is_adc12cstartadd_8(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd8
}
#[doc = "ADC12 Conversion Start Address: 9"]
#[inline(always)]
pub fn is_adc12cstartadd_9(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd9
}
#[doc = "ADC12 Conversion Start Address: 10"]
#[inline(always)]
pub fn is_adc12cstartadd_10(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd10
}
#[doc = "ADC12 Conversion Start Address: 11"]
#[inline(always)]
pub fn is_adc12cstartadd_11(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd11
}
#[doc = "ADC12 Conversion Start Address: 12"]
#[inline(always)]
pub fn is_adc12cstartadd_12(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd12
}
#[doc = "ADC12 Conversion Start Address: 13"]
#[inline(always)]
pub fn is_adc12cstartadd_13(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd13
}
#[doc = "ADC12 Conversion Start Address: 14"]
#[inline(always)]
pub fn is_adc12cstartadd_14(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd14
}
#[doc = "ADC12 Conversion Start Address: 15"]
#[inline(always)]
pub fn is_adc12cstartadd_15(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd15
}
}
#[doc = "Field `ADC12CSTARTADD` writer - ADC12 Conversion Start Address Bit: 0"]
pub type Adc12cstartaddW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12cstartadd, crate::Safe>;
impl<'a, REG> Adc12cstartaddW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Conversion Start Address: 0"]
#[inline(always)]
pub fn adc12cstartadd_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd0)
}
#[doc = "ADC12 Conversion Start Address: 1"]
#[inline(always)]
pub fn adc12cstartadd_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd1)
}
#[doc = "ADC12 Conversion Start Address: 2"]
#[inline(always)]
pub fn adc12cstartadd_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd2)
}
#[doc = "ADC12 Conversion Start Address: 3"]
#[inline(always)]
pub fn adc12cstartadd_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd3)
}
#[doc = "ADC12 Conversion Start Address: 4"]
#[inline(always)]
pub fn adc12cstartadd_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd4)
}
#[doc = "ADC12 Conversion Start Address: 5"]
#[inline(always)]
pub fn adc12cstartadd_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd5)
}
#[doc = "ADC12 Conversion Start Address: 6"]
#[inline(always)]
pub fn adc12cstartadd_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd6)
}
#[doc = "ADC12 Conversion Start Address: 7"]
#[inline(always)]
pub fn adc12cstartadd_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd7)
}
#[doc = "ADC12 Conversion Start Address: 8"]
#[inline(always)]
pub fn adc12cstartadd_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd8)
}
#[doc = "ADC12 Conversion Start Address: 9"]
#[inline(always)]
pub fn adc12cstartadd_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd9)
}
#[doc = "ADC12 Conversion Start Address: 10"]
#[inline(always)]
pub fn adc12cstartadd_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd10)
}
#[doc = "ADC12 Conversion Start Address: 11"]
#[inline(always)]
pub fn adc12cstartadd_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd11)
}
#[doc = "ADC12 Conversion Start Address: 12"]
#[inline(always)]
pub fn adc12cstartadd_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd12)
}
#[doc = "ADC12 Conversion Start Address: 13"]
#[inline(always)]
pub fn adc12cstartadd_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd13)
}
#[doc = "ADC12 Conversion Start Address: 14"]
#[inline(always)]
pub fn adc12cstartadd_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd14)
}
#[doc = "ADC12 Conversion Start Address: 15"]
#[inline(always)]
pub fn adc12cstartadd_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd15)
}
}
impl R {
#[doc = "Bit 0 - ADC12 Busy"]
#[inline(always)]
pub fn adc12busy(&self) -> Adc12busyR {
Adc12busyR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
#[inline(always)]
pub fn adc12conseq(&self) -> Adc12conseqR {
Adc12conseqR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
#[inline(always)]
pub fn adc12ssel(&self) -> Adc12sselR {
Adc12sselR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
#[inline(always)]
pub fn adc12div(&self) -> Adc12divR {
Adc12divR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
#[inline(always)]
pub fn adc12issh(&self) -> Adc12isshR {
Adc12isshR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
#[inline(always)]
pub fn adc12shp(&self) -> Adc12shpR {
Adc12shpR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - ADC12 Sample/Hold Source Bit: 0"]
#[inline(always)]
pub fn adc12shs(&self) -> Adc12shsR {
Adc12shsR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15 - ADC12 Conversion Start Address Bit: 0"]
#[inline(always)]
pub fn adc12cstartadd(&self) -> Adc12cstartaddR {
Adc12cstartaddR::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Busy"]
#[inline(always)]
pub fn adc12busy(&mut self) -> Adc12busyW<'_, Adc12ctl1Spec> {
Adc12busyW::new(self, 0)
}
#[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
#[inline(always)]
pub fn adc12conseq(&mut self) -> Adc12conseqW<'_, Adc12ctl1Spec> {
Adc12conseqW::new(self, 1)
}
#[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
#[inline(always)]
pub fn adc12ssel(&mut self) -> Adc12sselW<'_, Adc12ctl1Spec> {
Adc12sselW::new(self, 3)
}
#[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
#[inline(always)]
pub fn adc12div(&mut self) -> Adc12divW<'_, Adc12ctl1Spec> {
Adc12divW::new(self, 5)
}
#[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
#[inline(always)]
pub fn adc12issh(&mut self) -> Adc12isshW<'_, Adc12ctl1Spec> {
Adc12isshW::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
#[inline(always)]
pub fn adc12shp(&mut self) -> Adc12shpW<'_, Adc12ctl1Spec> {
Adc12shpW::new(self, 9)
}
#[doc = "Bits 10:11 - ADC12 Sample/Hold Source Bit: 0"]
#[inline(always)]
pub fn adc12shs(&mut self) -> Adc12shsW<'_, Adc12ctl1Spec> {
Adc12shsW::new(self, 10)
}
#[doc = "Bits 12:15 - ADC12 Conversion Start Address Bit: 0"]
#[inline(always)]
pub fn adc12cstartadd(&mut self) -> Adc12cstartaddW<'_, Adc12ctl1Spec> {
Adc12cstartaddW::new(self, 12)
}
}
#[doc = "ADC12+ Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl1Spec;
impl crate::RegisterSpec for Adc12ctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl1::R`](R) reader structure"]
impl crate::Readable for Adc12ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl1::W`](W) writer structure"]
impl crate::Writable for Adc12ctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL1 to value 0"]
impl crate::Resettable for Adc12ctl1Spec {}