asm-lsp 0.10.1

Eneg�NEGate. Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

neg
NEG






0https://www.zilog.com/docs/z80/z80cpu_um.pdf#NEGind�<
INput and Decrement. Inputs a value from port BC into memory at the address stored in HL, then decrements HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

ind
IND







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#INDrrd�Rotate Right bcd Digit. Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

rrd
RRD





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRDdec�DECrment. Decrements the target by one. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
dec
DEC (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28HL%29
dec

DEC (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28IX%2Bo%29
dec

DEC (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20%28IY%2Bo%29
dec
DEC A







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20A
dec
DEC B







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20B
dec
DEC BC







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20BC
dec
DEC C







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20C
dec
DEC D







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20D
dec
DEC DE







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20DE
dec
DEC E







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20E
dec
DEC H







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20H
dec
DEC HL







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20HL
dec
DEC IX






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IX
dec
DEC IY






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IY
dec
DEC IXp






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IXp
dec
DEC IYq






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20IYq
dec
DEC L







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20L
dec
DEC SP







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DEC%20SPin<Inputs a byte value from the 16-bit port number given in BC.	
in
	IN A, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20A%2C%20%28C%29
in
	IN A, (n)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20A%2C%20%28n%29
in
	IN B, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20B%2C%20%28C%29
in
	IN C, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20C%2C%20%28C%29
in
	IN D, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20D%2C%20%28C%29
in
	IN E, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20E%2C%20%28C%29
in
	IN H, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20H%2C%20%28C%29
in
	IN L, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20L%2C%20%28C%29
in
	IN F, (C)







	
@https://www.zilog.com/docs/z80/z80cpu_um.pdf#IN%20F%2C%20%28C%29ei�Enable Interrupts. Enables maskable interrupts (after next instruction, i.e. for example: EI RET - the interrupt may happen only after RET instruction is finished (or EI DI pair of instructions will not allow any maskable interrupt to happen).

ei
EI







/https://www.zilog.com/docs/z80/z80cpu_um.pdf#EIrst�ReSTart. Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.
rst
RST 0







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%200
rst
RST 8H







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%208H
rst
RST 10H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2010H
rst
RST 18H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2018H
rst
RST 20H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2020H
rst
RST 28H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2028H
rst
RST 30H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2030H
rst
RST 38H







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#RST%2038HcallpLike JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.	
call
CALL nn







6https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20nn
call

CALL C, nn














=https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20C%2C%20nn
call

CALL M, nn














=https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20M%2C%20nn
call
CALL NC, nn














>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20NC%2C%20nn
call
CALL NZ, nn














>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20NZ%2C%20nn
call

CALL P, nn














=https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20P%2C%20nn
call
CALL PE, nn














>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20PE%2C%20nn
call
CALL PO, nn














>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20PO%2C%20nn
call

CALL Z, nn














=https://www.zilog.com/docs/z80/z80cpu_um.pdf#CALL%20Z%2C%20nnor!Performs the bitwise OR operator.
or
OR (HL)





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28HL%29
or
	OR (IX+o)





>https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28IX%2Bo%29
or
	OR (IY+o)





>https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20%28IY%2Bo%29
or
OR n





3https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20n
or
OR r







3https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20r
or
OR IXp






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20IXp
or
OR IYq






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#OR%20IYqdjnz}Decrement reg. b and Jump if Not Zero. Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

djnz
DJNZ o







	






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#DJNZ%20oinir�D
INput and Increment Repeated. Loops INI until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

inir
INIR












1https://www.zilog.com/docs/z80/z80cpu_um.pdf#INIRrr[Rotate Right. Rotates the target bitwise right by one position. The LSB is copied to Carry.
rr
RR (HL)





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28HL%29
rr
	RR (IX+o)






>https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28IX%2Bo%29
rr
	RR (IY+o)






>https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20%28IY%2Bo%29
rr
RR r






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#RR%20rotdr�Out and Decrement Repeated. except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.

otdr
OTDR












1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OTDRmulubLPerform 8-bit multiplication. Introduced as a new instruction with the R800.

mulub

MULUB A, r



=https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUB%20A%2C%20rrrcaQSame as RRC except it only works on A, is faster, and does not alter S, Z or P/V.

rrca
RRCA







1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRCArl�g
Rotate Left. Rotates the target bitwise left by one position. The MSB is copied to Carry. The previous contents of Carry are copied to bit 0. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.
rl
RL (HL)





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28HL%29
rl
	RL (IX+o)






>https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28IX%2Bo%29
rl
	RL (IY+o)






>https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20%28IY%2Bo%29
rl
RL r






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#RL%20rxor"Performs the bitwise XOR operator.
xor
XOR (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28HL%29
xor

XOR (IX+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28IX%2Bo%29
xor

XOR (IY+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20%28IY%2Bo%29
xor
XOR n





4https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20n
xor
XOR r







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20r
xor
XOR IXp






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20IXp
xor
XOR IYq






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#XOR%20IYqlddr�	
LoaD and Decrement Repeated. Automatically loops LDD until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDDR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).

lddr
LDDR










1https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDDRhalt�Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

halt
HALT





1https://www.zilog.com/docs/z80/z80cpu_um.pdf#HALTini�>
INput and Incremenent. Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

ini
INI







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#INIdaa�Decimal Adjust Accumulator. Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).

daa
DAA







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#DAArlc�O
Rotate Left Circular. Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.
rlc
RLC (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28HL%29
rlc

RLC (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28IX%2Bo%29
rlc

RLC (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20%28IY%2Bo%29
rlc
RLC r






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLC%20rsbc�M
SuBtract with Carry, er, borrow. Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.
sbc
SBC A, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28HL%29
sbc

SBC A, (IX+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28IX%2Bo%29
sbc

SBC A, (IY+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20%28IY%2Bo%29
sbc
SBC A, n





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20n
sbc
SBC A, r







;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20r
sbc

SBC A, IXp






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20IXp
sbc

SBC A, IYq






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20A%2C%20IYq
sbc

SBC HL, BC





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20BC
sbc

SBC HL, DE





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20DE
sbc

SBC HL, HL





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20HL
sbc

SBC HL, SP





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#SBC%20HL%2C%20SPretnZRETurn from Non-maskable interrupt. Returns from a non-maskable interrupt service routine.

retn
RETN





1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RETNldir�P
LoaD and Increment Repeated. Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself). Flag effects are the same as LDI except that P/V will always be reset.

ldir
LDIR










1https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDIRjp
jp
JP nn






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20nn
jp
JP (HL)






:https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28HL%29
jp
JP (IX)






:https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28IX%29
jp
JP (IY)






:https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20%28IY%29
jp
JP C, nn








;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20C%2C%20nn
jp
JP M, nn








;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20M%2C%20nn
jp
	JP NC, nn








<https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20NC%2C%20nn
jp
	JP NZ, nn








<https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20NZ%2C%20nn
jp
JP P, nn








;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20P%2C%20nn
jp
	JP PE, nn








<https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20PE%2C%20nn
jp
	JP PO, nn








<https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20PO%2C%20nn
jp
JP Z, nn








;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JP%20Z%2C%20nnld�LoaD. The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first.Z
ld

LD (BC), A





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28BC%29%2C%20A
ld

LD (DE), A





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28DE%29%2C%20A
ld

LD (HL), n






Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28HL%29%2C%20n
ld

LD (HL), r





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28HL%29%2C%20r
ld
LD (IX+o), n





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IX%2Bo%29%2C%20n
ld
LD (IX+o), r





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IX%2Bo%29%2C%20r
ld
LD (IY+o), n





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IY%2Bo%29%2C%20n
ld
LD (IY+o), r





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28IY%2Bo%29%2C%20r
ld

LD (nn), A






Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20A
ld
LD (nn), BC





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20BC
ld
LD (nn), DE





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20DE
ld
LD (nn), HL





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20HL
ld
LD (nn), IX





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20IX
ld
LD (nn), IY





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20IY
ld
LD (nn), SP





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20%28nn%29%2C%20SP
ld

LD A, (BC)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28BC%29
ld

LD A, (DE)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28DE%29
ld

LD A, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28HL%29
ld
LD A, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28IX%2Bo%29
ld
LD A, (IY+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28IY%2Bo%29
ld

LD A, (nn)






Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20%28nn%29
ld
LD A, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20n
ld
LD A, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20r
ld
	LD A, IXp






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20IXp
ld
	LD A, IYq






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20IYq
ld
LD A, I

	



:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20I
ld
LD A, R

	



:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20A%2C%20R
ld

LD B, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28HL%29
ld
LD B, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28IX%2Bo%29
ld
LD B, (IY+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20%28IY%2Bo%29
ld
LD B, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20n
ld
LD B, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20r
ld
	LD B, IXp






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20IXp
ld
	LD B, IYq






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20B%2C%20IYq
ld
LD BC, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20BC%2C%20%28nn%29
ld
	LD BC, nn






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20BC%2C%20nn
ld

LD C, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28HL%29
ld
LD C, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28IX%2Bo%29
ld
LD C, (IY+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20%28IY%2Bo%29
ld
LD C, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20n
ld
LD C, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20r
ld
	LD C, IXp






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20IXp
ld
	LD C, IYq






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20C%2C%20IYq
ld

LD D, (HL)





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ld
LD D, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20%28IX%2Bo%29
ld
LD D, (IY+o)





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ld
LD D, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20n
ld
LD D, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20r
ld
	LD D, IXp






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20IXp
ld
	LD D, IYq






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20D%2C%20IYq
ld
LD DE, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20DE%2C%20%28nn%29
ld
	LD DE, nn






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20DE%2C%20nn
ld

LD E, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20%28HL%29
ld
LD E, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20%28IX%2Bo%29
ld
LD E, (IY+o)





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ld
LD E, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20n
ld
LD E, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20r
ld
	LD E, IXp






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20IXp
ld
	LD E, IYq






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20E%2C%20IYq
ld

LD H, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28HL%29
ld
LD H, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28IX%2Bo%29
ld
LD H, (IY+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20%28IY%2Bo%29
ld
LD H, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20n
ld
LD H, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20H%2C%20r
ld
LD HL, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20HL%2C%20%28nn%29
ld
	LD HL, nn






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20HL%2C%20nn
ld
LD I, A

	



:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20I%2C%20A
ld
LD IX, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IX%2C%20%28nn%29
ld
	LD IX, nn





<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IX%2C%20nn
ld
	LD IXh, n






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXh%2C%20n
ld
	LD IXh, p






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXh%2C%20p
ld
	LD IXl, n






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXl%2C%20n
ld
	LD IXl, p






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IXl%2C%20p
ld
LD IY, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IY%2C%20%28nn%29
ld
	LD IY, nn





<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IY%2C%20nn
ld
	LD IYh, n






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYh%2C%20n
ld
	LD IYh, q






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYh%2C%20q
ld
	LD IYl, n






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYl%2C%20n
ld
	LD IYl, q






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20IYl%2C%20q
ld

LD L, (HL)





Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28HL%29
ld
LD L, (IX+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28IX%2Bo%29
ld
LD L, (IY+o)





Ehttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20%28IY%2Bo%29
ld
LD L, n





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20n
ld
LD L, r







:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20L%2C%20r
ld
LD R, A

	



:https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20R%2C%20A
ld
LD SP, (nn)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20%28nn%29
ld
	LD SP, HL







<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20HL
ld
	LD SP, IX






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20IX
ld
	LD SP, IY






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20IY
ld
	LD SP, nn






<https://www.zilog.com/docs/z80/z80cpu_um.pdf#LD%20SP%2C%20nnmuluwMPerform 16-bit multiplication. Introduced as a new instruction with the R800.
muluw
MULUW HL, BC

$
$
?https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUW%20HL%2C%20BC
muluw
MULUW HL, SP

$
$
?https://www.zilog.com/docs/z80/z80cpu_um.pdf#MULUW%20HL%2C%20SPsrl{Shift Right Logical. Shifts the target bitwise right by one position. The LSB is copied to Carry. 0 is copied into the MSB.
srl
SRL (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28HL%29
srl

SRL (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28IX%2Bo%29
srl

SRL (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20%28IY%2Bo%29
srl
SRL r






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRL%20rinc�INCrement. ncrements the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
inc
INC (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28HL%29
inc

INC (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28IX%2Bo%29
inc

INC (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20%28IY%2Bo%29
inc
INC A







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20A
inc
INC B







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20B
inc
INC BC







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20BC
inc
INC C







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20C
inc
INC D







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20D
inc
INC DE







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20DE
inc
INC E







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20E
inc
INC H







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20H
inc
INC HL







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20HL
inc
INC IX






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IX
inc
INC IY






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IY
inc
INC IXp






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IXp
inc
INC IYq






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20IYq
inc
INC L







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20L
inc
INC SP







5https://www.zilog.com/docs/z80/z80cpu_um.pdf#INC%20SPsraShift Right Arithmetic. Shifts the target bitwise right by one position. The MSB is copied to itself. Bit 0 is copied to Carry.
sra
SRA (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28HL%29
sra

SRA (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28IX%2Bo%29
sra

SRA (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20%28IY%2Bo%29
sra
SRA r






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SRA%20rcpdr�
ComPare and Decrement Repeated. Automatically loops CPIR until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPD except that one of the two terminating flag conditions will always be true.

cpdr
CPDR










1https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPDRcpir�
ComPare and Increment Repeated. Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

cpir
CPIR










1https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPIRrraPSame as RR except it only works on A, is faster, and does not alter S, Z or P/V.

rra
RRA







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRAand"Performs the bitwise AND operator.
and
AND (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28HL%29
and

AND (IX+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28IX%2Bo%29
and

AND (IY+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20%28IY%2Bo%29
and
AND n





4https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20n
and
AND r







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20r
and
AND IXp






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20IXp
and
AND IYq






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#AND%20IYqbit2test Bit. Tests if a bit is set on a target value.
bit
BIT b, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28HL%29
bit

BIT b, (IX+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28IX%2Bo%29
bit

BIT b, (IY+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20%28IY%2Bo%29
bit
BIT b, r






;https://www.zilog.com/docs/z80/z80cpu_um.pdf#BIT%20b%2C%20raddAdds values together.
add
ADD A, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28HL%29
add

ADD A, (IX+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28IX%2Bo%29
add

ADD A, (IY+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20%28IY%2Bo%29
add
ADD A, n





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20n
add
ADD A, r







;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20r
add

ADD A, IXp






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20IXp
add

ADD A, IYq






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20A%2C%20IYq
add

ADD HL, BC







=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20BC
add

ADD HL, DE







=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20DE
add

ADD HL, HL







=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20HL
add

ADD HL, SP







=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20HL%2C%20SP
add

ADD IX, BC





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20BC
add

ADD IX, DE





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20DE
add

ADD IX, IX





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20IX
add

ADD IX, SP





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IX%2C%20SP
add

ADD IY, BC





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20BC
add

ADD IY, DE





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20DE
add

ADD IY, IY





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20IY
add

ADD IY, SP





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADD%20IY%2C%20SPotir�Out and Increment Repeated. Behaves like INIR except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.

otir
OTIR












1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OTIRcpl4ComPLement. Inverts the contents of the accumulator.

cpl
CPL







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPLdi1Disable Interrupts. Disables maskable interrupts.

di
DI





/https://www.zilog.com/docs/z80/z80cpu_um.pdf#DIset/SET bit. Sets the numbered bit on target value.
set
SET b, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28HL%29
set

SET b, (IX+o)






Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28IX%2Bo%29
set

SET b, (IY+o)






Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20%28IY%2Bo%29
set
SET b, r






;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SET%20b%2C%20rldi�LoaD and Increment. Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

ldi
LDI





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDIres(Resets the numbered bit on target value.
res
RES b, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28HL%29
res

RES b, (IX+o)






Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28IX%2Bo%29
res

RES b, (IY+o)






Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20%28IY%2Bo%29
res
RES b, r






;https://www.zilog.com/docs/z80/z80cpu_um.pdf#RES%20b%2C%20rrld�Rotate Left bcd Digit. Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

rld
RLD





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLDpush�Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.
push
PUSH AF





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20AF
push
PUSH BC





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20BC
push
PUSH DE





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20DE
push
PUSH HL





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20HL
push
PUSH IX





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20IX
push
PUSH IY





6https://www.zilog.com/docs/z80/z80cpu_um.pdf#PUSH%20IYldd�LoaD and Decrement. Copies the byte pointed to by HL to the address pointed to by DE, then substracts 1 from DE, HL, and BC. P/V is set to (BC!=0), i.e. set when non zero.

ldd
LDD





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#LDDscf$Set Carry Flag. Sets the carry flag.

scf
SCF







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#SCFcpd�ComPare and Decrement. Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then subtracts 1 from HL and subtracts 1 from BC.

cpd
CPD





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPDnop�No OPeration. Does 'nothing' (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

nop
NOP







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#NOPexxaEXchange all. Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

exx
EXX







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#EXXjr�Jump Relative. Jumps to an alternate address by adding the parameter to the PC - in other words the parameter is an adjustment, not an absolute address.
jr
JR o






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20o
jr
JR C, o














:https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20C%2C%20o
jr
JR NC, o














;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20NC%2C%20o
jr
JR NZ, o














;https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20NZ%2C%20o
jr
JR Z, o














:https://www.zilog.com/docs/z80/z80cpu_um.pdf#JR%20Z%2C%20oslaxShift Left Arithmetic. Shifts the target bitwise left by one position. The MSB is copied to Carry. 0 is copied to bit 0.
sla
SLA (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28HL%29
sla

SLA (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28IX%2Bo%29
sla

SLA (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20%28IY%2Bo%29
sla
SLA r






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SLA%20rout=Outputs a byte value from the 16-bit port number given in BC.
out

OUT (C), A







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20A
out

OUT (C), B







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20B
out

OUT (C), C







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20C
out

OUT (C), D







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20D
out

OUT (C), E







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20E
out

OUT (C), H







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20H
out

OUT (C), L







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28C%29%2C%20L
out

OUT (n), A







	
Ahttps://www.zilog.com/docs/z80/z80cpu_um.pdf#OUT%20%28n%29%2C%20Acpi�CoPare and Increment. Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

cpi
CPI





0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CPIadcMADd with Carry. Adds values together, adding an additional 1 if Carry is set.
adc
ADC A, (HL)





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28HL%29
adc

ADC A, (IX+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28IX%2Bo%29
adc

ADC A, (IY+o)





Fhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20%28IY%2Bo%29
adc
ADC A, n





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20n
adc
ADC A, r







;https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20r
adc

ADC A, IXp






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20IXp
adc

ADC A, IYq






=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20A%2C%20IYq
adc

ADC HL, BC





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20BC
adc

ADC HL, DE





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20DE
adc

ADC HL, HL





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20HL
adc

ADC HL, SP





=https://www.zilog.com/docs/z80/z80cpu_um.pdf#ADC%20HL%2C%20SPsubSubtracts a value from A.
sub
SUB (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28HL%29
sub

SUB (IX+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28IX%2Bo%29
sub

SUB (IY+o)





?https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20%28IY%2Bo%29
sub
SUB n





4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20n
sub
SUB r







4https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20r
sub
SUB IXp






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20IXp
sub
SUB IYq






6https://www.zilog.com/docs/z80/z80cpu_um.pdf#SUB%20IYqreti�RETurn from Interrupt. Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

reti
RETI





1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RETIoutd�Out and Decrement. Behaves like IND, except that it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.

outd
OUTD







1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OUTDccf�Complement Carry Flag. Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

ccf
CCF







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#CCFrlcaQSame as RLC except it only works on A, is faster, and does not alter S, Z or P/V.

rlca
RLCA







1https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLCAex0EXchange. Exchanges the contents of two sources.
ex
EX (SP), HL





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20HL
ex
EX (SP), IX





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20IX
ex
EX (SP), IY





Bhttps://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20%28SP%29%2C%20IY
ex

EX AF, AF'







?https://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20AF%2C%20AF%27
ex
	EX DE, HL







<https://www.zilog.com/docs/z80/z80cpu_um.pdf#EX%20DE%2C%20HLretsRETurn. POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.	
ret
RET






0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET
ret
RET C















4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20C
ret
RET M















4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20M
ret
RET NC















5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20NC
ret
RET NZ















5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20NZ
ret
RET P















4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20P
ret
RET PE















5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20PE
ret
RET PO















5https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20PO
ret
RET Z















4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RET%20ZrlaPSame as RL except it only works on A, is faster, and does not alter S, Z or P/V.

rla
RLA







0https://www.zilog.com/docs/z80/z80cpu_um.pdf#RLAim-Interrupt Mode. Sets interrupt handling mode.
im
IM 0






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%200
im
IM 1






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%201
im
IM 2






3https://www.zilog.com/docs/z80/z80cpu_um.pdf#IM%202cp�ComPare. Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
cp
CP (HL)





:https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28HL%29
cp
	CP (IX+o)





>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28IX%2Bo%29
cp
	CP (IY+o)





>https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20%28IY%2Bo%29
cp
CP n





3https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20n
cp
CP r







3https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20r
cp
CP IXp






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20IXp
cp
CP IYq






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#CP%20IYqindr�E
INput and Decrement Repeated. Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

indr
INDR












1https://www.zilog.com/docs/z80/z80cpu_um.pdf#INDRrrc�S
Rotate Right Circular. Rotates the target bitwise right by one position. The LSB is copied to the MSB, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.
rrc
RRC (HL)





;https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28HL%29
rrc

RRC (IX+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28IX%2Bo%29
rrc

RRC (IY+o)






?https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20%28IY%2Bo%29
rrc
RRC r






4https://www.zilog.com/docs/z80/z80cpu_um.pdf#RRC%20routi�Out and Increment. Behaves like INI, except it outputs instead of inputs and B is decremented before the output instead of after. Condition check on B is performed after, so that if OTIR starts with B=0 it loops 256 times.

outi
OUTI







1https://www.zilog.com/docs/z80/z80cpu_um.pdf#OUTIpop�
Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2. Popping into AF does set value of flag register F directly to low 8 bits of value from stack.
pop
POP AF






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20AF
pop
POP BC






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20BC
pop
POP DE






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20DE
pop
POP HL






5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20HL
pop
POP IX





5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20IX
pop
POP IY





5https://www.zilog.com/docs/z80/z80cpu_um.pdf#POP%20IY