� amominu.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply unsigned min the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amominu.d rd,rs2,(rs1) fsgnjx.s|Produce a result that takes all bits except the sign bit from rs1.The result’s sign bit is XOR of sign bit of rs1 and rs2. fsgnjx.s rd,rs1,rs2 fsqrt.s%Perform single-precision square root. fsqrt.s rd,rs1 fnmadd.d1Perform single-precision fused multiply addition. fnmadd.d rd,rs1,rs2,rs3 c.fsd�Store a double-precision floating-point value in floating-point register rs2\' to memory.It computes an effective address by adding the zeroextended offset, scaled by 8, to the base address in register rs1\'. c.fsd rd\',uimm(rs1\') c.srai�Perform a arithmetic right shift of the value in register rd\' then writes the result to rd\'.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C. c.srai rd\',uimm srlw�Performs logical right shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd. srlw rd,rs1,rs2 c.andiCompute the bitwise AND of of the value in register rd\' and the sign-extended 6-bit immediate, then writes the result to rd\'. c.andi rd\',imm wfi��wait for interrupt.
Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart.WFI is available in all privileged modes, and optionally available to U-mode.This instruction may raise an illegal instruction exception when TW=1 in mstatus. wfi fnmsub.s1Perform single-precision fused multiply addition. fnmsub.s rd,rs1,rs2,rs3 lwucLoads a 32-bit value from memory and zero-extends this to 64 bits before storing it in register rd. lwu rd,offset(rs1) csrrs��atomic read and set bits in CSR.
Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR.Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.Other bits in the CSR are unaffected (though CSRs might have side effects when written). csrrs rd,offset,rs1 c.sd�Store a 64-bit value in register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'. c.sd rd\',uimm(rs1\') lbudLoads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. lbu rd,offset(rs1) amomax.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply max operator the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amomax.w rd,rs2,(rs1) c.fld�Load a double-precision floating-point value from memory into floating-point register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'. c.fld rd\',uimm(rs1\') fcvt.s.l fcvt.s.l rd,rs1 fadd.d1Perform single-precision floating-point addition. fadd.d rd,rs1,rs2 fsgnjn.szProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is opposite of rs2’s sign bit. fsgnjn.s rd,rs1,rs2 csrrci�Clear CSR bit using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field. csrrci rd,offset,uimm amoadd.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply add the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amoadd.w rd,rs2,(rs1) fdiv.d1Perform single-precision floating-point division. fdiv.d rd,rs1,rs2 lui�load upper immediate.
Build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. lui rd,imm fcvt.l.s fcvt.l.s rd,rs1 c.addiw�Add the non-zero sign-extended 6-bit immediate to the value in register rd then produce 32-bit result, then sign-extends result to 64 bits. c.addiw rd,imm srai�Performs arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5]. srai rd,rs1,shamt fsqrt.d%Perform single-precision square root. fsqrt.d rd,rs1 fmadd.d1Perform single-precision fused multiply addition. fmadd.d rd,rs1,rs2,rs3
sfence.vma��Guarantees that any previous stores already visible to the current RISC-V hart are ordered before all subsequent implicit references from that hart to the memory-management data structures.The SFENCE.VMA is used to flush any local hardware caches related to address translation.It is specified as a fence rather than a TLB flush to provide cleaner semantics with respect to which instructions are affected by the flush operation and to support a wider variety of dynamic caching structures and memory-management schemes.SFENCE.VMA is also used by higher privilege levels to synchronize page table writes and the address translation hardware. sfence.vma rs1,rs2 amoadd.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply add the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amoadd.d rd,rs2,(rs1) fcvt.s.lu fcvt.s.lu rd,rs1
c.addi16sp�Add the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). c.addi16sp imm c.ld�Load a 64-bit value from memory into register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1\'. c.ld rd\',uimm(rs1\') fcvt.l.d fcvt.l.d rd,rs1 fmv.x.d fmv.x.d rd,rs1 sc.w�write a word in rs2 to the address in rs1, provided a valid reservation still exists on that address.SC writes zero to rd on success or a nonzero code on failure. sc.w rd,rs1,rs2 fmv.x.w�Move the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. fmv.x.w rd,rs1 fmul.d7Perform single-precision floating-point multiplication. fmul.d rd,rs1,rs2 addiw�cAdds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd.Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits.Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W). addiw rd,rs1,imm c.lwsp�Load a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. c.lwsp rd,uimm(x2) fsgnj.snProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is rs2’s sign bit. fsgnj.s rd,rs1,rs2 c.fldsp�Load a double-precision floating-point value from memory into floating-point register rd.It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. c.fldsp rd,uimm(x2) fcvt.d.lu fcvt.d.lu rd,rs1 slli�Performs logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5]. slli rd,rs1,shamt ebreak�Used by debuggers to cause control to be transferred back to a debugging environment.It generates a breakpoint exception and performs no other operation. ebreak c.flw�Load a single-precision floating-point value from memory into floating-point register rd\'.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'. c.flw rd\',uimm(rs1\') mretKReturn from traps in M-mode, and MRET copies MPIE into MIE, then sets MPIE. mret fcvt.s.wuConverts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd. fcvt.s.w rd,rs1 sb@Store 8-bit, values from the low bits of register rs2 to memory. sb rs2,offset(rs1) fcvt.s.djConverts double floating-point register in rs1 into a floating-point number in floating-point register rd. fcvt.s.d rd,rs1 csrrsi�Set CSR bit using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field. csrrsi rd,offset,uimm fnmsub.d1Perform single-precision fused multiply addition. fnmsub.d rd,rs1,rs2,rs3 ecall� Make a request to the supporting execution environment.When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation. ecall fcvt.d.wu�Converts a 32-bit unsigned integer, in integer register rs1 into a double-precision floating-point number in floating-point register rd. fcvt.d.wu rd,rs1 fclass.s�sExamines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.The format of the mask is described in [classify table]_.The corresponding bit in rd will be set if the property is true and clear otherwise.All other bits in rd are cleared. Note that exactly one bit in rd will be set. fclass.s rd,rs1 sretKReturn from traps in S-mode, and SRET copies SPIE into SIE, then sets SPIE. sret swAStore 32-bit, values from the low bits of register rs2 to memory. sw rs2,offset(rs1) csrrwi�Update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field. csrrwi rd,offset,uimm c.xorkCompute the bitwise XOR of the values in registers rd\' and rs2\', then writes the result to register rd\'. c.xor rd\',rs2\' bgeZTake the branch if registers rs1 is greater than or equal to rs2, using signed comparison. bge rs1,rs2,offset slt�Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd. slt rd,rs1,rs2 csrrw�satomic read/write CSR.
Atomically swaps values in the CSRs and integer registers.CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd.The initial value in rs1 is written to the CSR.If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. csrrw rd,offset,rs1 c.jrJPerforms an unconditional control transfer to the address in register rs1. c.jr rs1 fsgnjx.d|Produce a result that takes all bits except the sign bit from rs1.The result’s sign bit is XOR of sign bit of rs1 and rs2. fsgnjx.d rd,rs1,rs2 oriePerforms bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd ori rd,rs1,imm c.orjCompute the bitwise OR of the values in registers rd\' and rs2\', then writes the result to register rd\'. c.or rd\',rs2\' c.srli�Perform a logical right shift of the value in register rd\' then writes the result to rd\'.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C. c.srli rd\',uimm amoor.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply or the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amoor.d rd,rs2,(rs1) fcvt.lu.d fcvt.lu.d rd,rs1 amoand.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply and the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amoand.d rd,rs2,(rs1) c.addw�Add the value in register rs2\' from the value in register rd\', then sign-extends the lower 32 bits of the difference before writing the result to register rd\'. c.addw rd\',rs2\' c.slli�Perform a logical left shift of the value in register rd then writes the result to rd.The shift amount is encoded in the shamt field, where shamt[5] must be zero for RV32C. c.slli rd,uimm fle.d�Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. fle.d rd,rs1,rs2 sllw�Performs logical left shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd. sllw rd,rs1,rs2 amoor.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply or the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amoor.w rd,rs2,(rs1) fadd.s1Perform single-precision floating-point addition. fadd.s rd,rs1,rs2 fmin.s@Write the smaller of single precision data in rs1 and rs2 to rd. fmin.s rd,rs1,rs2 fsdKStore a double-precision value from the floating-point registers to memory. fsd rs2,offset(rs1) auipc�add upper immediate to pc
Build pc-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then places the result in register rd. auipc rd,imm srli�Performs logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediateIn RV64, bit-25 is used to shamt[5]. srli rd,rs1,shamt csrrc��atomic read and clear bits in CSR.
Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR.Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.Other bits in the CSR are unaffected. csrrc rd,offset,rs1 fsgnj.dnProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is rs2’s sign bit. fsgnj.d rd,rs1,rs2 fdiv.s1Perform single-precision floating-point division. fdiv.s rd,rs1,rs2 bgeu\Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison. bgeu rs1,rs2,offset fcvt.d.l fcvt.d.l rd,rs1 c.mv0Copy the value in register rs2 into register rd. c.mv rd,rs2 sllvPerforms logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2. sll rd,rs1,rs2 andHPerforms bitwise AND on registers rs1 and rs2 and place the result in rd and rd,rs1,rs2 bltuMTake the branch if registers rs1 is less than rs2, using unsigned comparison. bltu rs1,rs2,offset remwDperform an 32 bits by 32 bits signed integer reminder of rs1 by rs2. remw rd,rs1,rs2 slti�set less than immediate
Place the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. slti rd,rs1,imm fle.s�Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. fle.s rd,rs1,rs2 c.fswsp�Store a single-precision floating-point value in floating-point register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. c.fswsp rs2,uimm(rs2) fmul.s7Perform single-precision floating-point multiplication. fmul.s rd,rs1,rs2
c.addi4spn�Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd\'.This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd\', x2, nzuimm[9:2]. c.addi4spn rd\',uimm divuwFperform an 32 bits by 32 bits unsigned integer division of rs1 by rs2. divuw rd,rs1,rs2 c.fsdsp�Store a double-precision floating-point value in floating-point register rs2 to memory.It computes an effective address by adding the zeroextended offset, scaled by 8, to the stack pointer, x2. c.fsdsp rs2,uimm(x2) sc.d�write a 64-bit data in rs2 to the address in rs1, provided a valid reservation still exists on that address.SC writes zero to rd on success or a nonzero code on failure. sc.d rd,rs1,rs2 mulhsu�performs an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. mulhsu rd,rs1,rs2 lr.drload a 64-bit data from the address in rs1, places value in rd, and registers a reservation on the memory address. lr.d rd,rs1 fcvt.wu.d�Converts a double-precision floating-point number in floating-point register rs1 to a unsigned 32-bit integer, in integer register rd. fcvt.wu.d rd,rs1 mulh�performs an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by signed rs2 and places the upper XLEN bits in the destination register. mulh rd,rs1,rs2 lbdLoads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. lb rd,offset(rs1) divwDperform an 32 bits by 32 bits signed integer division of rs1 by rs2. divw rd,rs1,rs2 amomin.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply min operator the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amomin.w rd,rs2,(rs1) c.sw�Store a 32-bit value in register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'. c.sw rd\',uimm(rs1\') fsub.s5Perform single-precision floating-point substraction. fsub.s rd,rs1,rs2 feq.d�Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. feq.d rd,rs1,rs2 bne7Take the branch if registers rs1 and rs2 are not equal. bne rs1,rs2,offset addw�Adds the 32-bit of registers rs1 and 32-bit of register rs2 and stores the result in rd.Arithmetic overflow is ignored and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register. addw rd,rs1,rs2 c.li]Load the sign-extended 6-bit immediate, imm, into register rd.C.LI is only valid when rd!=x0. c.li rd,imm fnmadd.s1Perform single-precision fused multiply addition. fnmadd.s rd,rs1,rs2,rs3 c.subw�Subtract the value in register rs2\' from the value in register rd\', then sign-extends the lower 32 bits of the difference before writing the result to register rd\'. c.subw rd\',rs2\' fmv.w.x�Move the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. fmv.w.x rd,rs1 jal/Jump to address and place return address in rd. jal rd,offset orGPerforms bitwise OR on registers rs1 and rs2 and place the result in rd or rd,rs1,rs2 feq.s�Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. feq.s rd,rs1,rs2 flt.d�Performs a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. flt.d rd,rs1,rs2 srayPerforms arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2 sra rd,rs1,rs2 subw�Subtract the 32-bit of registers rs1 and 32-bit of register rs2 and stores the result in rd.Arithmetic overflow is ignored and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register. subw rd,rs1,rs2 fmax.d?Write the larger of single precision data in rs1 and rs2 to rd. fmax.d rd,rs1,rs2 div_perform an XLEN bits by XLEN bits signed integer division of rs1 by rs2, rounding towards zero. div rd,rs1,rs2 c.flwsp�Load a single-precision floating-point value from memory into floating-point register rd.It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. c.flwsp rd,uimm(x2) fmadd.s1Perform single-precision fused multiply addition. fmadd.s rd,rs1,rs2,rs3 c.jal/Jump to address and place return address in rd. c.jal offset sd1Store 64-bit, values from register rs2 to memory. sd rs2,offset(rs1) c.j Unconditional control transfer.
c.j offset c.bnez;Take the branch if the value in register rs1\' is not zero. c.bnez rs1\',offset fcvt.wu.srConvert a floating-point number in floating-point register rs1 to a signed 32-bit in unsigned integer register rd. fcvt.wu.s rd,rs1 jalr/Jump to address and place return address in rd. jalr rd,rs1,offset andifPerforms bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd andi rd,rs1,imm fcvt.d.w�Converts a 32-bit signed integer, in integer register rs1 into a double-precision floating-point number in floating-point register rd. fcvt.d.w rd,rs1 amomax.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply max the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amomax.d rd,rs2,(rs1) sltiu�Place the value 1 in register rd if register rs1 is less than the immediate when both are treated as unsigned numbers, else 0 is written to rd. sltiu rd,rs1,imm xori�Performs bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rdNote, "XORI rd, rs1, -1" performs a bitwise logical inversion of register rs1(assembler pseudo-instruction NOT rd, rs) xori rd,rs1,imm amomaxu.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply unsigned max the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amomaxu.d rd,rs2,(rs1) c.nopDDoes not change any user-visible state, except for advancing the pc. c.nop c.subnSubtract the value in register rs2\' from the value in register rd\', then writes the result to register rd\'. c.sub rd\',rs2\' fmax.s?Write the larger of single precision data in rs1 and rs2 to rd. fmax.s rd,rs1,rs2 amoand.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply and the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amoand.w rd,rs2,(rs1) c.lw�Load a 32-bit value from memory into register rd\'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'. c.lw rd\',uimm(rs1\') fclass.d�yExamines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.The format of the mask is described in table [classify table]_.The corresponding bit in rd will be set if the property is true and clear otherwise.All other bits in rd are cleared. Note that exactly one bit in rd will be set. fclass.d rd,rs1 fmin.d@Write the smaller of single precision data in rs1 and rs2 to rd. fmin.d rd,rs1,rs2 amoswap.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, swap the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amoswap.d rd,rs2,(rs1) slliw�Performs logical left shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved. slliw rd,rs1,shamt amoxor.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, apply exclusive or the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amoxor.w rd,rs2,(rs1) flt.s�Performs a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd.Only signaling NaN inputs cause an Invalid Operation exception.The result is 0 if either operand is NaN. flt.s rd,rs1,rs2 fsgnjn.dzProduce a result that takes all bits except the sign bit from rs1.The result’s sign bit is opposite of rs2’s sign bit. fsgnjn.d rd,rs1,rs2 sub�Subs the register rs2 from rs1 and stores the result in rd.Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. sub rd,rs1,rs2 fcvt.s.wuwConverts a 32-bit unsigned integer, in integer register rs1 into a floating-point number in floating-point register rd. fcvt.s.wu rd,rs1 fcvt.d.sqConverts single floating-point register in rs1 into a double floating-point number in floating-point register rd. fcvt.d.s rd,rs1 fcvt.w.d�Converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit integer, in integer register rd. fcvt.w.d rd,rs1 xorHPerforms bitwise XOR on registers rs1 and rs2 and place the result in rd xor rd,rs1,rs2 srlmLogical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2 srl rd,rs1,rs2 uretKReturn from traps in U-mode, and URET copies UPIE into UIE, then sets UPIE. uret sraw�Performs arithmetic right shift on the low 32-bits value in register rs1 by the shift amount held in the lower 5 bits of register rs2 and produce 32-bit results and written to the destination register rd. sraw rd,rs1,rs2 c.swsp�Store a 32-bit value in register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. c.swsp rs2,uimm(x2) fcvt.lu.s fcvt.lu.s rd,rs1 ld<Loads a 64-bit value from memory into register rd for RV64I. ld rd,offset(rs1) fmsub.d1Perform single-precision fused multiply addition. fmsub.d rd,rs1,rs2,rs3 fence��Used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors.Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same.Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE. fence pred, succ lhueLoads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. lhu rd,offset(rs1) c.andkCompute the bitwise AND of the values in registers rd\' and rs2\', then writes the result to register rd\'. c.and rd\',rs2\' c.ebreakBCause control to be transferred back to the debugging environment. c.ebreak remuwFperform an 32 bits by 32 bits unsigned integer reminder of rs1 by rs2. remuw rd,rs1,rs2 fsub.d4Perform single-precision floating-point subtraction. fsub.d rd,rs1,rs2 c.fsw�Store a single-precision floating-point value in floatingpoint register rs2\' to memory.It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1\'. c.fsw rd\',uimm(rs1\') flwYLoad a single-precision floating-point value from memory into floating-point register rd. flw rd,offset(rs1) fswJStore a single-precision value from floating-point register rs2 to memory. fsw rs2,offset(rs1) amoswap.w�atomically load a 32-bit signed data value from the address in rs1, place the value into register rd, swap the loaded value and the original 32-bit signed value in rs2, then store the result back to the address in rs1. amoswap.w rd,rs2,(rs1) sltu�Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as unsigned numbers, else 0 is written to rd. sltu rd,rs1,rs2 shAStore 16-bit, values from the low bits of register rs2 to memory. sh rs2,offset(rs1) c.ldsp�Load a 64-bit value from memory into register rd.It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. c.ldsp rd,uimm(x2) amominu.w�atomically load a 32-bit unsigned data value from the address in rs1, place the value into register rd, apply unsigned min the loaded value and the original 32-bit unsigned value in rs2, then store the result back to the address in rs1. amominu.w rd,rs2,(rs1) divuaperform an XLEN bits by XLEN bits unsigned integer division of rs1 by rs2, rounding towards zero. divu rd,rs1,rs2 sraiw�Performs arithmetic right shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved. sraiw rd,rs1,shamt c.addihAdd the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. c.addi rd,u[12:12]|u[6:2] mulw mulw rd,rs1,rs2 c.lui c.lui rd,imm fmsub.s1Perform single-precision fused multiply addition. fmsub.s rd,rs1,rs2,rs3 fcvt.w.siConvert a floating-point number in floating-point register rs1 to a signed 32-bit in integer register rd. fcvt.w.s rd,rs1 fldYLoad a double-precision floating-point value from memory into floating-point register rd. fld rd,rs1,offset fence.ipProvides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. fence.i amoxor.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply xor the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amoxor.d rd,rs2,(rs1) amomaxu.w�atomically load a 32-bit unsigned data value from the address in rs1, place the value into register rd, apply unsigned max the loaded value and the original 32-bit unsigned value in rs2, then store the result back to the address in rs1. amomaxu.w rd,rs2,(rs1) c.jalr/Jump to address and place return address in rd.
c.jalr rd amomin.d�atomically load a 64-bit data value from the address in rs1, place the value into register rd, apply min the loaded value and the original 64-bit value in rs2, then store the result back to the address in rs1. amomin.d rd,rs2,(rs1) lheLoads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. lh rd,offset(rs1) fmv.d.x fmv.d.x rd,rs1 lweLoads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. lw rd,offset(rs1) c.sdsp�Store a 64-bit value in register rs2 to memory.It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. c.sdsp rs2,uimm(x2) beq3Take the branch if registers rs1 and rs2 are equal. beq rs1,rs2,offset bltKTake the branch if registers rs1 is less than rs2, using signed comparison. blt rs1,rs2,offset mul�performs an XLEN-bit :math:`\times` XLEN-bit multiplication of signed rs1 by signed rs2 and places the lower XLEN bits in the destination register. mul rd,rs1,rs2 c.beqz7Take the branch if the value in register rs1\' is zero. c.beqz rs1\',offset addi�add immediate
Adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction. addi rd,rs1,imm srliw�Performs logical right shift on the 32-bit of value in register rs1 by the shift amount held in the lower 5 bits of the immediate.Encodings with $imm[5] \neq 0$ are reserved. srliw rd,rs1,shamt c.addLAdd the values in registers rd and rs2 and writes the result to register rd. c.add rd,rs2 remHperform an XLEN bits by XLEN bits signed integer reminder of rs1 by rs2. rem rd,rs1,rs2 add�Adds the registers rs1 and rs2 and stores the result in rd.Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. add rd,rs1,rs2 remuJperform an XLEN bits by XLEN bits unsigned integer reminder of rs1 by rs2. remu rd,rs1,rs2 mulhu�performs an XLEN-bit :math:`\times` XLEN-bit multiplication of unsigned rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. mulhu rd,rs1,rs2 lr.w}load a word from the address in rs1, places the sign-extended value in rd, and registers a reservation on the memory address. lr.w rd,rs1