asm-lsp 0.10.1

�abs.s�B
fd ← abs(fs)
To compute the absolute value of a single precision FP value
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.This operation is arithmetic; a NaN operand signals invalid operation.
abs.s fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
abs.s�B
fd ← abs(fs)
To compute the absolute value of a double precision FP value
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.This operation is arithmetic; a NaN operand signals invalid operation.
abs.s fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
add�[
rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
	-If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
	If the addition does not overflow, the 32-bit result is placed into GPR rd.
ADD rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
add.s�c
fd ← fs + ft
To add single precision floating point values
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
ADD.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
add.d�c
fd ← fs + ft
To add double precision floating point values
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
ADD.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
addi��
rt ← rs + immediate
To add a constant to a 32-bit integer. If overflow occurs, then trap.
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
	If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
	If the addition does not overflow, the 32-bit result is placed into GPR rt.
ADDI rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
addiu�To add a constant to a 32-bit integer
rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rt. No Integer Overflow exception occurs under any circumstances.
ADDIU rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
addu�To add 32-bit integers
rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rd. No Integer Overflow exception occurs under any circumstances.
ADDU rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
and�To do a bitwise logical AND
rd ← rs AND r
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd
AND rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
andi�To do a bitwise logical AND with a constant
rt ← rs AND immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND operation. The result is placed into GPR rt.
ANDI rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf

b��
To do an unconditional branch
branch
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BEQ r0, r0, offset.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
B offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bal�iTo do an unconditional PC-relative procedure call
procedure_call
BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the hardware as BGEZAL r0, offset.

Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
BAL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc1f� To test an FP condition code and do a PC-relative conditional branch
if cc = 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP condition code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.BC1F offset (cc = 0 implied)BC1F cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc1fl��To test an FP condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Condition Code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.BC1FL offset (cc = 0 implied)BC1FL cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc1t�To test an FP condition code and do a PC-relative conditional branch
if cc = 1 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP condition code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.BC1T offset (cc = 0 implied)BC1T cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc1tl��To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Condition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.BC1TL offset (cc = 0 implied)BC1TL cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc2f��
To test a COP2 condition code and do a PC-relative conditional branch
if cc = 0 then branchAn 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed.BC2F offset (cc = 0 implied)BC2F cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc2fl��To test a COP2 condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.BC2FL offset (cc = 0 implied)BC2FL cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc2t��
To test a COP2 condition code and do a PC-relative conditional branch
if cc = 1 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed.BC2T offset (cc = 0 implied)BC2T cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bc2tl�|To test a COP2 condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
if cc = 1 then branch_likely
n 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.BC2TL offset (cc = 0 implied)BC2TL cc, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
beq��
To compare GPRs then do a PC-relative conditional branch
if rs = rt then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed.
BEQ rs, rt, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
beql�FTo compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs = rt then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs and GPR rt are equal, branch to the target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BEQL rs, rt, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgez��
To test a GPR then do a PC-relative conditional branch
if rs ≥ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
BGEZ rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgezal��To test a GPR then do a PC-relative conditional procedure call
if rs ≥ 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
BGEZAL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgezall�'To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
if rs ≥ 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BGEZALL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgezl�lTo test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs ≥ 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BGEZL rs, offset 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgtz��
To test a GPR then do a PC-relative conditional branch
if rs > 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed.
BGTZ rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bgtzl�qTo test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs > 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BGTZL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
blez��
To test a GPR then do a PC-relative conditional branch
if rs ≤ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed.
BLEZ rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
blezl�zTo test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs ≤ 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BLEZL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bltz��
To test a GPR then do a PC-relative conditional branch
if rs < 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
BLTZ rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bltzal��To test a GPR then do a PC-relative conditional procedure call
if rs < 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
BLTZAL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bltzall�To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
if rs < 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BLTZALL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bltzl�[To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs < 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BLTZL rs, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bne��
To compare GPRs then do a PC-relative conditional branch
if rs ≠ rt then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed.
BNE rs, rt, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
bnel�VTo compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
if rs ≠ rt then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
BNEL rs, rt, offset
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
break�?
To cause a Breakpoint exception
A breakpoint exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
BREAK 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf

c�t
To compare FP values and record the Boolean result in a condition code
cc ← fs compare_cond ft
The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The comparison is exact and neither overflows nor underflows.

If the comparison specified by cond 2..1 is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into condition code CC; true is 1 and false is 0.

If one of the values is an SNaN, or cond 3 is set and at least one of the values is a QNaN, an Invalid Operation condition is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise, the Boolean result is written into condition code CC.

There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0.

The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal, equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Boolean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP values in the equation. If the equal relation is true, for example, then all four example predicates above yield a true result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result.

Logical negation of a compare result allows eight distinct comparisons to test for the 16 predicates as shown in . Each mnemonic tests for both a predicate and its logical negation. For each mnemonic, compare tests the truth of the first predicate. When the first predicate is true, the result is true as shown in the “If Predicate Is True” column, and the second predicate must be false, and vice versa. (Note that the False predicate is never true and False/True do not follow the normal pattern.)

The truth of the second predicate is the logical negation of the instruction result. After a compare instruction, test for the truth of the first predicate can be made with the Branch on FP True (BC1T) instruction and the truth of the second can be made with Branch on FP False (BC1F). C.cond.S fs, ft (cc = 0 implied)0C.cond.D fs, ft (cc = 0 implied) MIPS32 (MIPS I)C.cond.S cc, fs, ftC.cond.D cc, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cache�<
To perform the cache operation specified by op.
The 16-bit offset is sign-extended and added to the contents of the base register to form an effective address. The effective address is used in one of the following ways based on the operation to be performed and the type of cache as described in the following table.
CACHE op, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ceil.w.s��To convert a single precision FP value to 32-bit fixed point, rounding up
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format and rounding toward +∞ (rounding mode 2). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd
CEIL.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ceil.w.d��To convert a double precision FP value to 32-bit fixed point, rounding up
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format and rounding toward +∞ (rounding mode 2). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd
CEIL.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cfc1�To copy a word from an FPU control register to a GPR
rt ← FP_Control[fs]
Copy the 32-bit word from FP (coprocessor 1) control register fs into GPR rt.
CFC1 rt, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cfc2�To copy a word from a Coprocessor 2 control register to a GPR
rt ← CCR[2,rd]
Copy the 32-bit word from Coprocessor 2 control register rd into GPR rt.
CFC2 rt, rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
clo�3
To Count the number of leading ones in a word
rd ← count_leading_ones rs
Bits 31..0 of GPR rs are scanned from most significant to least significant bit. The number of leading ones is counted and the result is written to GPR rd. If all of bits 31..0 were set in GPR rs, the result written to GPR rd is 32.

CLO rd, rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
clz�)
Count the number of leading zeros in a word
rd ← count_leading_zeros rs
Bits 31..0 of GPR rs are scanned from most significant to least significant bit. The number of leading zeros is counted and the result is written to GPR rd. If no bits were set in GPR rs, the result written to GPR rt is 32.

CLZ rd, rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cop2��
To performan operation to Coprocessor 2
CoprocessorOperation(2, cofun)
An implementation-dependent operation is performance to Coprocessor 2, with the cofun value passed as an argument. The operation may specify and reference internal coprocessor registers, and may change the state of the coprocessor conditions, but does not modify state within the processor. Details of coprocessor operation and internal state are described in the documentation for each Coprocessor 2 implementation.
	COP2 func
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ctc1�`To copy a word from a GPR to an FPU control register
FP_Control[fs] ← rt
Copy the low word from GPR rt into the FP (coprocessor 1) control register indicated by fs.

Writing to the floating point Control/Status register, the FCSR, causes the appropriate exception if any Cause bit and its corresponding Enable bit are both set. The register is written before the exception occurs. Writing to FEXR to set a cause bit whose enable bit is already set, or writing to FENR to set an enable bit whose cause bit is already set causes the appropriate exception. The register is written before the exception occurs.
CTC1 rt, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ctc2�To copy a word from a GPR to a Coprocessor 2 control register
CCR[2,rd] ← rt
Copy the low word from GPR rt into the Coprocessor 2control register indicated by rd.
CTC2 rt, rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cvt.d�=
To convert an FP or fixed point value to double FP
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in double floating point format and rounded according to the current rounding mode in FCSR. The result is placed in FPR fd. If fmt is S or W, then the operation is always exact.CVT.D.S fd, fsCVT.D.W fd, fsCVT.D.L fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cvt.s�
To convert an FP or fixed point value to single FP
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in single floating point format and rounded according to the current rounding mode in FCSR. The result is placed in FPR fd.CVT.S.D fd, fsCVT.S.W fd, fsCVT.S.L fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cvt.w.s��To convert a single precision FP value to 32-bit fixed point
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format and rounded according to the current rounding mode in FCSR. The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
CVT.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
cvt.w.d��To convert a double precision FP value to 32-bit fixed point
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format and rounded according to the current rounding mode in FCSR. The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
CVT.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
deret�To Return from a debug exception.
DERET returns from Debug Mode and resumes non-debug execution at the instruction whose address is contained in the DEPC register. DERET does not execute the next instruction (i.e. it has no delay slot).
DERET
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
div�W
To divide a 32-bit signed integers
(LO, HI) ← rs / rt
The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as signed values.

The 32-bit quotient is placed into special register LO and the 32-bit remainder isplaced into special register HI.

No arithmetic exception occurs under any circumstances.

DIV rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
div.s�
To divide single precision FP values
fd ← fs / ft
The value in FPR fs is divided by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt.
DIV.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
div.d�
To divide double precision FP values
fd ← fs / ft
The value in FPR fs is divided by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt.
DIV.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
divu�[
To divide a 32-bit unsigned integers
(LO, HI) ← rs / rt
The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as unsigned values.

The 32-bit quotient is placed into special register LO and the 32-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.
DIVU rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
eret�To return from interrupt, exception, or error trap.
ERET returns to the interrupted instruction at the completion of interrupt, exception, or error trap processing. ERET does not execute the next instruction (i.e., it has no delay slot).
ERET
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
	floor.w.s��To convert an FP value to 32-bit fixed point, rounding down
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format and rounded toward –∞ (rounding mode 3). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
FLOOR.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf

j�To branch within the current 256 MB-aligned region
This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.
J target
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
jal��To execute a procedure call within the current 256 MB-aligned region
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call.

This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.

JAL target
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
jalr��To execute a procedure call to an instruction address in a register
 rd ← return_addr, PC ← rs
Place the return address link in GPR rd. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.
For processors that do not implement the MIPS16 ASE:
- Jump to the effective target address in GPR rs. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.

For processors that do implement the MIPS16 ASE:
- Jump to the effective target address in GPR rs. Set the ISA Mode bit to the value in GPR rs bit 0. Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one

At this time the only defined hint field value is 0, which sets default handling of JALR. Future versions of the architecture may define additional hint values.JALR rs (rd = 31 implied)JALR rd, rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
jr��
To execute a branch to an instruction address in a register
 PC ← rs
Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot, before jumping.

For processors that implement the MIPS16 ASE, set the ISA Mode bit to the value in GPR rs bit 0. Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one
JR rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lb�0
To load a byte from memory as a signed value
 rt ← memory[base+offset]
The contents of the 8-bit byte at the memory location specified by the effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LB rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lbu�2
To load a byte from memory as an unsigned value
rt ← memory[base+offset]
The contents of the 8-bit byte at the memory location specified by the effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LBU rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lcd1�-
To load a doubleword from memory to an FPR
 ft ← memory[base+offset]
The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in FPR ft. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LDC1 ft, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ldc2�Q
To load a doubleword from memory to a Coprocessor 2 register
rt ← memory[base+offset]
The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in Coprocessor 2 register rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LDC2 rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lh�@
To load a halfword from memory as a signed value
rt ← memory[base+offset]
The contents of the 16-bit halfword at the memory location specified by the aligned effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LH rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lhu�C
To load a halfword from memory as an unsigned value
rt ← memory[base+offset]
The contents of the 16-bit halfword at the memory location specified by the aligned effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LHU rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ll�xTo load a word from memory for an atomic read-modify-write
rt ← memory[base+offset]
The LL and SC instructions provide the primitives to implement atomic read-modify-write (RMW) operations for cached memory locations.

The 16-bit signed offset is added to the contents of GPR base to form an effective address. The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the GPR register length if necessary, and written into GPR rt.

This begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor.

When an LL is executed it starts an active RMW sequence replacing any other sequence that was active.

The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomically and succeeds, or does not and fails.

Executing LL on one processor does not cause an action that, by itself, causes an SC for the same block to fail on another processor.

An execution of LL does not have to be followed by execution of SC; a program is free to abandon the RMW sequence without attempting a write.
LL rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lui�To load a constant into the upper half of a word
rt ← immediate || 016
The 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order zeros. The 32-bit result is placed into GPR rt.
LUI rt, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lw�`
To load a word from memory as a signed value
rt ← memory[base+offset]
The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LW rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lwc1�M
To load a word from memory to an FPR
ft ← memory[base+offset]
The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and placed into the low word of coprocessor 1 general register ft. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LWC1 ft, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lwc2�]
To load a word from memory to a COP2 register
rt ← memory[base+offset]
The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and placed into the low word of COP2 (Coprocessor 2) general register rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
LWC2 rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lwl�STo load the most-significant part of a word as a signed value from an unaligned memory address
rt ← rt MERGE memory[base+offset]
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

The most-significant 1 to 4 bytes of W is in the aligned word containing the EffAddr. This part of W is loaded into the most-significant (left) part of the word in GPR rt. The remaining least-significant part of the word in GPR rt is unchanged.

The figure below illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is in the aligned word containing the most-significant byte at 2. First, LWL loads these 2 bytes into the left part of the destination register word and leaves the right part of the destination word unchanged. Next, the complementary LWR loads the remainder of the unaligned word
LWL rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
lwr��To load the least-significant part of a word from an unaligned memory address as a signed value
rt ← rt MERGE memory[base+offset]
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the least-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

A part of W, the least-significant 1 to 4 bytes, is in the aligned word containing EffAddr. This part of W is loaded into the least-significant (right) part of the word in GPR rt. The remaining most-significant part of the word in GPR rt is unchanged.

Executing both LWR and LWL, in either order, delivers a sign-extended word value in the destination register. The figure below illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is in the aligned word containing the least-significant byte at 5. First, LWR loads these 2 bytes into the right part of the destination register. Next, the complementary LWL loads the remainder of the unaligned word.
LWR rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
madd��
To multiply two words and add the result to Hi, Lo
(LO,HI) ← (rs x rt) + (LO,HI)The 32-bit word value in GPR rs is multiplied by the 32-bit word value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The product is added to the 64-bit concatenated values of HI and LO.. The most significant 32 bits of the result are written into HI and the least signficant 32 bits are written into LO. No arithmetic exception occurs under any circumstances.
MADD rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
maddu��
To multiply two unsigned words and add the result to Hi, Lo.
(LO,HI) ← (rs x rt) + (LO,HI)
The 32-bit word value in GPR rs is multiplied by the 32-bit word value in GPR rt, treating both operands as unsigned values, to produce a 64-bit result. The product is added to the 64-bit concatenated values of HI and LO.. The most significant 32 bits of the result are written into HI and the least signficant 32 bits are written into LO. No arithmetic exception occurs under any circumstances.
MADDU rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mfc0�G
To move the contents of a coprocessor 0 register to a general register.
rt ← CPR[0,rd,sel]
The contents of the coprocessor 0 register specified by the combination of rd and sel are loaded into general registe rt. Note that not all coprocessor 0 registers support the sel field. In those instances, the sel field must be zero.
MFC0 rt, rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mfc1�To copy a word from an FPU (CP1) general register to a GPR
rt ← fs
The contents of FPR fs are loaded into general register rt.
MFC1 rt, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mfc2�
To copy a word from a COP2 general register to a GPR
rt ← rd
The contents of GPR rt are and placed into the coprocessor 2 register specified by the rd and sel fields. Note that not all coprocessor 2 registers may support the sel field. In those instances, the sel field must be zero.MFC2 rt, rdMFC2, rt, rd, sel
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mfhivTo copy the special purpose HI register to a GPR
rd ← HI
The contents of special register HI are loaded into GPR rd.
MFHI rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mflovTo copy the special purpose LO register to a GPR
rd ← LO
The contents of special register LO are loaded into GPR rd.
MFLO rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mov.s�To move a single precision FP value between FPRs
fd ← fs
The value in FPR fs is placed into FPR fd. The source and destination are values in format fmt. The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOV.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mov.d�To move a double precision FP value between FPRs
fd ← fs
The value in FPR fs is placed into FPR fd. The source and destination are values in format fmt. The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOV.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movf�To test an FP condition code then conditionally move a GPR
if cc = 0 then rd ← rs
If the floating point condition code specified by CC is zero, then the contents of GPR rs are placed into GPR rd.
MOVF rd, rs, cc
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movf.s�qTo test an FP condition code then conditionally move an FP value
if cc = 0 then fd ← fs
If the floating point condition code specified by CC is zero, then the value in FPR fs is placed into FPR fd. The source and destination are values in format fmt.

If the condition code is not zero, then FPR fs is not copied and FPR fd retains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVF.S fd, fs, cc
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movn�To conditionally move a GPR after testing a GPR value
if rt ≠ 0 then rd ← rs
If the value in GPR rt is not equal to zero, then the contents of GPR rs are placed into GPR rd.
MOVN rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movn.s�XTo test a GPR then conditionally move a single precision FP value
if rt ≠ 0 then fd ← fs
If the value in GPR rt is not equal to zero, then the value in FPR fs is placed in FPR fd. The source and destination are values in format fmt.

If GPR rt contains zero, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVN.S fd, fs, rt 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movn.d�XTo test a GPR then conditionally move a double precision FP value
if rt ≠ 0 then fd ← fs
If the value in GPR rt is not equal to zero, then the value in FPR fs is placed in FPR fd. The source and destination are values in format fmt.

If GPR rt contains zero, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVN.S fd, fs, rt 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movt�To test an FP condition code then conditionally move a GPR
if cc = 1 then rd ← rs
If the floating point condition code specified by CC is one, then the contents of GPR rs are placed into GPR rd.
MOVT rd, rs, cc
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movt.s�|To test an FP condition code then conditionally move a single precision FP value
if cc = 1 then fd ← fs
If the floating point condition code specified by CC is one, then the value in FPR fs is placed into FPR fd. The source and destination are values in format fmt.

If the condition code is not one, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes undefined.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVT.S fd, fs, cc
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movt.d�|To test an FP condition code then conditionally move a single precision FP value
if cc = 1 then fd ← fs
If the floating point condition code specified by CC is one, then the value in FPR fs is placed into FPR fd. The source and destination are values in format fmt.

If the condition code is not one, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes undefined.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVT.D fd, fs, cc
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movz�To conditionally move a GPR after testing a GPR value
if rt = 0 then rd ← rs
If the value in GPR rt is equal to zero, then the contents of GPR rs are placed into GPR rd.
MOVZ rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movz.s�OTo test a GPR then conditionally move a single precision FP value
if rt = 0 then fd ← fs
If the value in GPR rt is equal to zero then the value in FPR fs is placed in FPR fd. The source and destination are values in format fmt.

If GPR rt is not zero, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVZ.S fd, fs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
movz.d�OTo test a GPR then conditionally move a double precision FP value
if rt = 0 then fd ← fs
If the value in GPR rt is equal to zero then the value in FPR fs is placed in FPR fd. The source and destination are values in format fmt.

If GPR rt is not zero, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.

The move is non-arithmetic; it causes no IEEE 754 exceptions.
MOVZ.D fd, fs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
msub��
To multiply two words and subtract the result from Hi, Lo
(LO,HI) ← (rs x rt) - (LO,HI)
The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The product is subtracted from the 64-bit concatenated values of HI and LO.. The most significant 32 bits of the result are written into HI and the least signficant 32 bits are written into LO. No arithmetic exception occurs under any circumstances.
MSUB rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
msubu��
To multiply two words and subtract the result from Hi, Lo
(LO,HI) ← (rs x rt) - (LO,HI)
The 32-bit word value in GPR rs is multiplied by the 32-bit word value in GPR rt, treating both operands as unsigned values, to produce a 64-bit result. The product is subtracted from the 64-bit concatenated values of HI and LO.. The most significant 32 bits of the result are written into HI and the least signficant 32 bits are written into LO. No arithmetic exception occurs under any circumstances.
MSUBU rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mtc0�L
To move the contents of a general register to a coprocessor 0 register.
CPR[r0, rd, sel] ← rt
The contents of general register rt are loaded into the coprocessor 0 register specified by the combination of rd and sel. Not all coprocessor 0 registers support the the sel field. In those instances, the sel field must be set to zero.
MTC0 rt, rd
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mtc1�To copy a word from a GPR to an FPU (CP1) general register
fs ← rt
The low word in GPR rt is placed into the low word of floating point (Coprocessor 1) general register fs
MTC1 rt, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mtc2�,
To copy a word from a GPR to a COP2 general register
rd ← rt
The low word in GPR rt is placed into the low word of coprocessor 2 general register specified by the rd and sel fields. Note that not all coprocessor 2 registers may support the sel field. In those instances, the sel field must be zero.MTC2 rt, rdMTC2 rt, rd, sel
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mthiwTo copy a GPR to the special purpose HI register
 HI ← rs
The contents of GPR rs are loaded into special register HI.
MTHI rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mtlovTo copy a GPR to the special purpose LO register
LO ← rs
The contents of GPR rs are loaded into special register LO.
MTLO rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mul��
To multiply two words and write the result to a GPR.
rd ← rs × rt
The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The least significant 32 bits of the product are written to GPR rd. The contents of HI and LO are UNPREDICTABLE after the operation. No arithmetic exception occurs under any circumstances.
MUL rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mul.s�"
To multiply single precision FP values
fd ← fs × ft
The value in FPR fs is multiplied by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt.
MUL.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mul.d�"
To multiply single precision FP values
fd ← fs × ft
The value in FPR fs is multiplied by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt.
MUL.D fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
mult��
To multiply 32-bit signed integers
(LO, HI) ← rs × rt
The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is splaced into special register HI.

No arithmetic exception occurs under any circumstances.
MULT rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
multu��
To multiply 32-bit unsigned integers
(LO, HI) ← rs × rt
The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is placed into special register HI. No arithmetic exception occurs under any circumstances.
MULTU rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
neg.s�
To negate an FP value
fd ← −fs
The value in FPR fs is negated and placed into FPR fd. The value is negated by changing the sign bit value. The operand and result are values in format fmt. This operation is arithmetic; a NaN operand signals invalid operation.
NEG.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
neg.d�
To negate an FP value
fd ← −fs
The value in FPR fs is negated and placed into FPR fd. The value is negated by changing the sign bit value. The operand and result are values in format fmt. This operation is arithmetic; a NaN operand signals invalid operation.
NEG.D fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
nop�To perform no operation.
NOP is the assembly idiom used to denote no operation. The actual instruction is interpreted by the hardware as SLL r0, r0, 0.
NOP
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
nor�To do a bitwise logical NOT OR
rd ← rs NOR rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical NOR operation. The result is placed into GPR rd.
NOR rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
or�To do a bitwise logical OR
rd ← rs or rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical OR operation. The result is placed into GPR rd.

OR rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ori�To do a bitwise logical OR with a constant
rt ← rs or immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical OR operation. The result is placed into GPR rt.
ORI rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
pref�hTo move data between memory and cache.
prefetch_memory(base+offset)
PREF adds the 16-bit signed offset to the contents of GPR base to form an effective byte address. The hint field supplies information about the way that the data is expected to be used.

PREF enables the processor to take some action, typically prefetching the data into cache, to improve program performance. The action taken for a specific PREF instruction is both system and context dependent. Any action, including doing nothing, is permitted as long as it does not change architecturally visible state or alter the meaning of a program. Implementations are expected either to do nothing, or to take an action that increases the performance of the program.

PREF does not cause addressing-related exceptions. If the address specified would cause an addressing exception, the exception condition is ignored and no data movement occurs.However even if no data is prefetched, some action that is not architecturally visible, such as writeback of a dirty cache line, can take place.

PREF never generates a memory operation for a location with an uncached memory access type.

If PREF results in a memory operation, the memory access type used for the operation is determined by the memory access type of the effective address, just as it would be if the memory operation had been caused by a load or store to the effective address.

For a cached location, the expected and useful action for the processor is to prefetch a block of data that includes the effective address. The size of the block and the level of the memory hierarchy it is fetched into are implementation specific.

The hint field supplies information about the way the data is expected to be used. A hint value cannot cause an action to modify architecturally visible state. A processor may use a hint value to improve the effectiveness of the prefetch action.
PREF hint,offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
	round.w.s��To convert a single precision FP value to 32-bit fixed point, rounding to nearest
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format rounding to nearest/even (rounding mode 0). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. In this case the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
ROUND.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
	round.w.d��To convert a double precision FP value to 32-bit fixed point, rounding to nearest
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format rounding to nearest/even (rounding mode 0). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. In this case the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
ROUND.W.D fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sb�
To store a byte to memory
memory[base+offset] ← rt
The least-significant 8-bit byte of GPR rt is stored in memory at the location specified by the effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SB rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sc��To store a word to memory to complete an atomic read-modify-write
if atomic_update then memory[base+offset] ← rt, rt ← 1 else rt ← 0
The LL and SC instructions provide primitives to implement atomic read-modify-write (RMW) operations for cached memory locations.

The 16-bit signed offset is added to the contents of GPR base to form an effective address. The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor. To complete the RMW sequence atomically, the following occur:
	- The least-significant 32-bit word of GPR rt is stored into memory at the location specified by the aligned effective address.
	A 1, indicating success, is written into GPR rt.
		Otherwise, memory is not modified and a 0, indicating failure, is written into GPR rt.
		If either of the following events occurs between the execution of LL and SC, the SC fails:
	- A coherent store is completed by another processor or coherent I/O module into the block of physical memory containing the word. The size and alignment of the block is implementation dependent, but it is at least one word and at most the minimum page size.
	- An exception occurs on the processor executing the LL/SC.
		If either of the following events occurs between the execution of LL and SC, the SC may succeed or it may fail; the success or failure is not predictable. Portable programs should not cause one of these events.
	- A load, store, or prefetch is executed on the processor executing the LL/SC.
	- The instructions executed starting with the LL and ending with the SC do not lie in a 2048-byte contiguous region of virtual memory. The region does not have to be aligned, other than the alignment required for instruction words.
The following conditions must be true or the result of the SC is undefined:
	- Execution of SC must have been preceded by execution of an LL instruction.
	- A RMW sequence executed without intervening exceptions must use the same address in the LL and SC. The address is the same if the virtual address, physical address, and cache-coherence algorithm are identical.
		Atomic RMW is provided only for cached memory locations. The extent to which the detection of atomicity operates correctly depends on the system implementation and the memory access type used for the location:

	MP atomicity: To provide atomic RMW among multiple processors, all accesses to the location must be made with a memory access type of cached coherent.
	Uniprocessor atomicity: To provide atomic RMW on a single processor, all accesses to the location must be made with memory access type of either cached noncoherent or cached coherent. All accesses must be to one or the other access type, and they may not be mixed.
I/O System: To provide atomic RMW with a coherent I/O system, all accesses to the location must be made with a memory access type of cached coherent. If the I/O system does not use coherent memory operations, then atomic RMW cannot be provided with respect to the I/O reads and writes.
SC rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sdbbp��
To cause a debug breakpoint exception
This instruction causes a debug exception, passing control to the debug exception handler. The code field can be used for passing information to the debug exception handler, and is retrieved by the debug exception handler only by loading the contents of the memory word containing the instruction, using the DEPC register. The CODE field is not used in any way by the hardware.

SDBBP code
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sdc1�
To store a doubleword from an FPR to memory
memory[base+offset] ← ft
The 64-bit doubleword in FPR ft is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SDC1 ft, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sdc2�8
To store a doubleword from a Coprocessor 2 register to memory
 memory[base+offset] ← rt
The 64-bit doubleword in Coprocessor 2 register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address
SDC2 rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sh�
To store a halfword to memory
memory[base+offset] ← rt
The least-significant 16-bit halfword of register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SH rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sll�To left-shift a word by a fixed number of bits
rd ← rt << sa
The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa.
SLL rd, rt, sa
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
slt�T
To record the result of a less-than comparison
 rd ← (rs < rt)
Compare the contents of GPR rs and GPR rt as signed integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false).

The arithmetic comparison does not cause an Integer Overflow exception.
SLT rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
slti��
To record the result of a less-than comparison with a constant
rt ← (rs < immediate)
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers and record the Boolean result of the comparison in GPR rt. If GPR rs is less than immediate, the result is 1 (true); otherwise, it is 0 (false).

The arithmetic comparison does not cause an Integer Overflow exception.
SLTI rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sltiu��To record the result of an unsigned less-than comparison with a constant
rt ← (rs < immediate)
Compare the contents of GPR rs and the sign-extended 16-bit immediate as unsigned integers and record the Boolean result of the comparison in GPR rt. If GPR rs is less than immediate, the result is 1 (true); otherwise, it is 0 (false).

Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range. The arithmetic comparison does not cause an Integer Overflow exception.
SLTIU rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sltu�_
To record the result of an unsigned less-than comparison
rd ← (rs < rt)
Compare the contents of GPR rs and GPR rt as unsigned integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false).

The arithmetic comparison does not cause an Integer Overflow exception.
SLTU rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sqrt.s�Y
To compute the square root of a single precision FP value
fd ← SQRT(fs)
The square root of the value in FPR fs is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operand and result are values in format fmt.

If the value in FPR fs corresponds to – 0, the result is – 0.

SQRT.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sqrt.d�Y
To compute the square root of a single precision FP value
fd ← SQRT(fs)
The square root of the value in FPR fs is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operand and result are values in format fmt.

If the value in FPR fs corresponds to – 0, the result is – 0.

SQRT.D fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sra�1
To execute an arithmetic right-shift of a word by a fixed number of bits
rd ← rt >> sa (arithmetic)
The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa.
SRA rd, rt, sa
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
srav�Q
To execute an arithmetic right-shift of a word by a variable number of bits
 rd ← rt >> rs (arithmetic)
The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs.
SRAV rd, rt, rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
srl�
To execute a logical right-shift of a word by a fixed number of bits
rd ← rt >> sa (logical)
The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa.
SRL rd, rt, sa
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
srlv�:
To execute a logical right-shift of a word by a variable number of bits
 rd ← rt >> rs (logical)
The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs.
SRLV rd, rt, rs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
ssnop�BBreak superscalar issue on a superscalar processor.
SSNOP is the assembly idiom used to denote superscalar no operation. The actual instruction is interpreted by the hardware as SLL r0, r0, 1.

This instruction alters the instruction issue behavior on a superscalar processor by forcing the SSNOP instruction to single-issue. The processor must then end the current instruction issue between the instruction previous to the SSNOP and the SSNOP. The SSNOP then issues alone in the next issue slot.

On a single-issue processor, this instruction is a NOP that takes an issue slot.
SSNOP
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sub��
To subtract 32-bit integers. If overflow occurs, then trap
rd ← rs - rt
The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to produce a 32-bit result. If the subtraction results in 32-bit 2’s complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd
SUB rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sub.s�8To subtract FP values
 fd ← fs - ft
The value in FPR ft is subtracted from the value in FPR fs. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Restrictions:
	- The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPREDICTABLE.
	- The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
SUB.S fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sub.d�8To subtract FP values
 fd ← fs - ft
The value in FPR ft is subtracted from the value in FPR fs. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Restrictions:
	- The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPREDICTABLE.
	- The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
SUB.D fd, fs, ft
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
subu�To subtract 32-bit integers
rd ← rs - rt
The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs and the 32-bit arithmetic result is and placed into GPR rd.

No integer overflow exception occurs under any circumstances.
SUBU rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sw�
To store a word to memory
memory[base+offset] ← rt
The least-significant 32-bit word of register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SW rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
swc1�

To store a word from an FPR to memory
memory[base+offset] ← ft
The low 32-bit word from FPR ft is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SWC1 ft, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
swc2�1
To store a word from a COP2 register to memory
 memory[base+offset] ← ft
The low 32-bit word from COP2 (Coprocessor 2) register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
SWC2 rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
swl�`To store the most-significant part of a word to an unaligned memory address
memory[base+offset] ← rt
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

A part of W, the most-significant 1 to 4 bytes, is in the aligned word containing EffAddr. The same number of the most-significant (left) bytes from the word in GPR rt are stored into these bytes of W.

The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is located in the aligned word containing the most-significant byte at 2. First, SWL stores the most-significant 2 bytes of the low word from the source register into these 2 bytes in memory. Next, the complementary SWR stores the remainder of the unaligned word.The bytes stored from the source register to memory depend on both the offset of the effective address within an aligned word—that is, the low 2 bits of the address (vAddr1..0)—and the current byte-ordering mode of the processor (big- or little-endian). The following figure shows the bytes stored for every combination of offset and byte ordering.
SWL rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
swr�jTo store the least-significant part of a word to an unaligned memory address
 memory[base+offset] ← rt
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the least-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

A part of W, the least-significant 1 to 4 bytes, is in the aligned word containing EffAddr. The same number of the least-significant (right) bytes from the word in GPR rt are stored into these bytes of W.

The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is contained in the aligned word containing the least-significant byte at 5. First, SWR stores the least-significant 2 bytes of the low word from the source register into these 2 bytes in memory. Next, the complementary SWL stores the remainder of the unaligned word.The bytes stored from the source register to memory depend on both the offset of the effective address within an aligned word—that is, the low 2 bits of the address (vAddr1..0)—and the current byte-ordering mode of the processor (big- or little-endian). The following figure shows the bytes stored for every combination of offset and byte-ordering.
SWR rt, offset(base)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
sync��To order loads and stores
Simple Description:
	- SYNC affects only uncached and cached coherent loads and stores. The loads and stores that occur before the SYNC must be completed before the loads and stores after the SYNC are allowed to start.
	- Loads are completed when the destination register is written. Stores are completed when the stored value is visible to every other processor in the system.
	- SYNC is required, potentially in conjunction with SSNOP, to guarantee that memory reference results are visible across operating mode changes. For example, a SYNC is required on some implementations on entry to and exit from Debug Mode to guarantee that memory affects are handled correctly.
Detailed Description:
	- When the stype field has a value of zero, every synchronizable load and store that occurs in the instruction stream before the SYNC instruction must be globally performed before any synchronizable load or store that occurs after the SYNC can be performed, with respect to any other processor or coherent I/O module.
	- SYNC does not guarantee the order in which instruction fetches are performed. The stype values 1-31 are reserved; they produce the same result as the value zero.
SYNC (stype = 0 implied)
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
syscall�A
To cause a System Call exception
A system call exception occurs, immediately and unconditionally transferring control to the exception handler.
The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
SYSCALL 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
teq��
To compare GPRs and do a conditional trap
if rs = rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is equal to GPR rt, then take a Trap excep- tion.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.

TEQ rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
teqi�To compare a GPR to a constant and do a conditional trap
if rs = immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is equal to immediate, then take a Trap exception.
TEQI rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tge��
To compare GPRs and do a conditional trap
if rs ≥ rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is greater than or equal to GPR rt, then take a Trap exception.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.

TGE rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tgei�To compare a GPR to a constant and do a conditional trap
if rs ≥ immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is greater than or equal to immediate, then take a Trap exception.
TGEI rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tgeiu�	To compare a GPR to a constant and do a conditional trap
if rs ≥ immediate then Trap
Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned integers; if GPR rs is greater than or equal to immediate, then take a Trap exception.

Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range.
TGEIU rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tgeu��
To compare GPRs and do a conditional trap if rs ≥ rt then Trap
Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is greater than or equal to GPR rt, then take a Trap exception.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
TGEU rs, rt 
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlbp�To find a matching entry in the TLB.
The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the Index register is set.
TLBP
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlbr�4To read an entry from the TLB
The EntryHi, EntryLo0, EntryLo1, and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register. Note that the value written to the EntryHi, EntryLo0, and EntryLo1 registers may be different from that originally written to the TLB via these registers in that:
	-The value returned in the VPN2 field of the EntryHi register may havethose bits set to zero corresponding to the one bits in the Mask field of the TLB entry (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.
	- The value returned in the PFN field of the EntryLo0 and EntryLo1 registers may havethose bits set to zero corresponding to the one bits in the Mask field of the TLB entry (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.
	- The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written.
TLBR
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlbwi�uTo write a TLB entry indexed by the Index register.
The TLB entry pointed to by the Index register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:
	- The value written to the VPN2 field of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of the PageMask register (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
	- The value written to the PFN0 and PFN1 fields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of PageMask register (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write. 
	- The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
TLBWI
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlbwr��To write a TLB entry indexed by the Random register.
The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:
	- The value written to the VPN2 field of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of the PageMask register (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
	- The value written to the PFN0 and PFN1 fields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of PageMask register (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
	- The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written.
TLBWR
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlt��
To compare GPRs and do a conditional trap
if rs < rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is less than GPR rt, then take a Trap exception.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.

TLT rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tlti�To compare a GPR to a constant and do a conditional trap
if rs < immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is less than immediate, then take a Trap exception.
TLTI rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tltiu��
To compare a GPR to a constant and do a conditional trap
if rs < immediate then Trap
Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned integers; if GPR rs is less than immediate, then take a Trap exception.

Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range.
TLTIU rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tltu��
To compare GPRs and do a conditional trap
if rs < rt then Trap
Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is less than GPR rt, then take a Trap exception.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
TLTU rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tne��
To compare GPRs and do a conditional trap
if rs ≠ rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is not equal to GPR rt, then take a Trap exception.

The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.

TNE rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
tnei�To compare a GPR to a constant and do a conditional trap
if rs ≠ immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is not equal to immediate, then take a Trap exception.
TNEI rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
	trunc.w.s��To convert a single precision FP value to 32-bit fixed point, rounding toward zero
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format using rounding toward zero (rounding mode 1). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. In this case the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
TRUNC.W.S fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
	trunc.w.d��To convert a double precision FP value to 32-bit fixed point, rounding toward zero
fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format using rounding toward zero (rounding mode 1). The result is placed in FPR fd.

When the source value is Infinity, NaN, or rounds to an integer outside the range -2 31 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. In this case the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, the default result, 2 31–1, is written to fd.
TRUNC.W.D fd, fs
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
wait��Wait for Event
The WAIT instruction performs an implementation-dependent operation, usually involving a lower power mode.
Software may use bits 24:6 of the instruction to communicate additional information to the processor, and the processor may use this information as control for the lower power mode. A value of zero for bits 24:6 is the default and must be valid in all implementations.

The WAIT instruction is typically implemented by stalling the pipeline at the completion of the instruction and entering a lower power mode. The pipeline is restarted when an external event, such as an interrupt or external request occurs, and execution continues with the instruction following the WAIT instruction. It is implementation-dependent whether the pipeline restarts when a non-enabled interrupt is requested. In this case, software must poll for the cause of the restart. If the pipeline restarts as the result of an enabled interrupt, that interrupt is taken between the WAIT instruction and the following instruction (EPC for the interrupt points at the instruction following the WAIT instruction).

The assertion of any reset or NMI must restart the pipelihne and the corresponding exception myust be taken.
WAIT
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
xor�To do a bitwise logical Exclusive OR
 rd ← rs XOR rt
Combine the contents of GPR rs and GPR rt in a bitwise logical Exclusive OR operation and place the result into GPR rd.
XOR rd, rs, rt
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
xori�To do a bitwise logical Exclusive OR with a constant
rt ← rs XOR immediate
Combine the contents of GPR rs and the 16-bit zero-extended immediate in a bitwise logical Exclusive OR operation and place the result into GPR rt.
XORI rt, rs, immediate
>https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf