asm-lsp 0.10.1

8adcFAdd Memory to Accumulator with Carry
A + M + C -> A, C
NZCIDV
`+++--+`	ADC #operADC oper
ADC oper,XADC oper
ADC oper,X
ADC oper,YADC (oper,X)ADC (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#ADCand8AND Memory with Accumulator
A AND M -> A
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`++----`	AND #operAND oper
AND oper,XAND oper
AND oper,X
AND oper,YAND (oper,X)AND (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#ANDaslOShift Left One Bit (Memory or Accumulator)
C <- [76543210] <- 0
NZCIDV
`+++---`ASL AASL oper
ASL oper,XASL oper
ASL oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#ASLbcc5Branch on Carry Clear
branch on C = 0
NZCIDV
`------`
BCC oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BCCbcs3Branch on Carry Set
branch on C = 1
NZCIDV
`------`
BCS oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BCSbeq5Branch on Result Zero
branch on Z = 1
NZCIDV
`------`
BEQ oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BEQbit��
Test Bits in Memory with Accumulator
bits 7 and 6 of operand are transfered to bit 7 and 6 of SR (N,V);the zero-flag is set according to the result of the operand ANDthe accumulator (set, if the result is zero, unset otherwise).This allows a quick check of a few bits at once without affectingany of the registers, other than the status register (SR).
A AND M -> Z, M7 -> N, M6 -> V
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`M>>>>>`BIT operBIT oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BITbmi6Branch on Result Minus
branch on N = 1
NZCIDV
`------`
BMI oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BMIbne9Branch on Result not Zero
branch on Z = 0
NZCIDV
`------`
BNE oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BNEbpl5Branch on Result Plus
branch on N = 0
NZCIDV
`------`
BPL oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BPLbrk��
Force Break
BRK initiates a software interrupt similar to a hardwareinterrupt (IRQ). The return address pushed to the stack isPC+2, providing an extra byte of spacing for a break mark(identifying a reason for the break.)The status register will be pushed to the stack with the breakflag set to 1. However, when retrieved during RTI or by a PLPinstruction, the break flag will be ignored.The interrupt disable flag is not set automatically.
interrupt,push PC+2, push SR 
NZCIDV
`---1--`
BRK
:https://www.masswerk.at/6502/6502_instruction_set.html#BRKbvc8Branch on Overflow Clear
branch on V = 0
NZCIDV
`------`
BVC oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BVCbvs6Branch on Overflow Set
branch on V = 1
NZCIDV
`------`
BVS oper
:https://www.masswerk.at/6502/6502_instruction_set.html#BVSclc'Clear Carry Flag
0 -> C
NZCIDV
`--0---`
CLC
:https://www.masswerk.at/6502/6502_instruction_set.html#CLCcld)Clear Decimal Mode
0 -> D
NZCIDV
`----0-`
CLD
:https://www.masswerk.at/6502/6502_instruction_set.html#CLDcli2Clear Interrupt Disable Bit
0 -> I
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`---0--`
CLI
:https://www.masswerk.at/6502/6502_instruction_set.html#CLIclv*Clear Overflow Flag
0 -> V
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`-----0`
CLV
:https://www.masswerk.at/6502/6502_instruction_set.html#CLVcmp5Compare Memory with Accumulator
A - M
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`+++---`	CMP #operCMP oper
CMP oper,XCMP oper
CMP oper,X
CMP oper,YCMP (oper,X)CMP (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#CMPcpx0Compare Memory and Index X
X - M
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`+++---`	CPX #operCPX operCPX oper
:https://www.masswerk.at/6502/6502_instruction_set.html#CPXcpy0Compare Memory and Index Y
Y - M
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`+++---`	CPY #operCPY operCPY oper
:https://www.masswerk.at/6502/6502_instruction_set.html#CPYdec2Decrement Memory by One
M - 1 -> M
NZCIDV
`++----`DEC oper
DEC oper,XDEC oper
DEC oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#DECdex3Decrement Index X by One
X - 1 -> X
NZCIDV
`++----`
DEX
:https://www.masswerk.at/6502/6502_instruction_set.html#DEXdey3Decrement Index Y by One
Y - 1 -> Y
NZCIDV
`++----`
DEY
:https://www.masswerk.at/6502/6502_instruction_set.html#DEYeorAExclusive-OR Memory with Accumulator
A EOR M -> A
NZCIDV
`++----`	EOR #operEOR oper
EOR oper,XEOR oper
EOR oper,X
EOR oper,YEOR (oper,X)EOR (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#EORinc2Increment Memory by One
M + 1 -> M
NZCIDV
`++----`INC oper
INC oper,XINC oper
INC oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#INCinx3Increment Index X by One
X + 1 -> X
NZCIDV
`++----`
INX
:https://www.masswerk.at/6502/6502_instruction_set.html#INXiny3Increment Index Y by One
Y + 1 -> Y
NZCIDV
`++----`
INY
:https://www.masswerk.at/6502/6502_instruction_set.html#INYjmpSJump to New Location
operand 1st byte -> PCLoperand 2nd byte -> PCH
NZCIDV
`------`JMP oper
JMP (oper)
:https://www.masswerk.at/6502/6502_instruction_set.html#JMPjsruJump to New Location Saving Return Address
push (PC+2),operand 1st byte -> PCLoperand 2nd byte -> PCH
NZCIDV
`------`
JSR oper
:https://www.masswerk.at/6502/6502_instruction_set.html#JSRlda3Load Accumulator with Memory
M -> A
NZCIDV
`++----`	LDA #operLDA oper
LDA oper,XLDA oper
LDA oper,X
LDA oper,YLDA (oper,X)LDA (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#LDAldx/Load Index X with Memory
M -> X
NZCIDV
`++----`	LDX #operLDX oper
LDX oper,YLDX oper
LDX oper,Y
:https://www.masswerk.at/6502/6502_instruction_set.html#LDXldy/Load Index Y with Memory
M -> Y
NZCIDV
`++----`	LDY #operLDY oper
LDY oper,XLDY oper
LDY oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#LDYlsrPShift One Bit Right (Memory or Accumulator)
0 -> [76543210] -> C
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`0++---`LSR ALSR oper
LSR oper,XLSR oper
LSR oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#LSRnop No Operation
---
NZCIDV
`------`
NOP
:https://www.masswerk.at/6502/6502_instruction_set.html#NOPora6OR Memory with Accumulator
A OR M -> A
NZCIDV
`++----`	ORA #operORA oper
ORA oper,XORA oper
ORA oper,X
ORA oper,YORA (oper,X)ORA (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#ORApha0Push Accumulator on Stack
push A
NZCIDV
`------`
PHA
:https://www.masswerk.at/6502/6502_instruction_set.html#PHAphp�Push Processor Status on Stack
The status register will be pushed with the breakflag and bit 5 set to 1.
push SR
NZCIDV
`------`
PHP
:https://www.masswerk.at/6502/6502_instruction_set.html#PHPpla2Pull Accumulator from Stack
pull A
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`++----`
PLA
:https://www.masswerk.at/6502/6502_instruction_set.html#PLAplp�Pull Processor Status from Stack
The status register will be pulled with the breakflag and bit 5 ignored.
pull SR
NZCIDV
`from stack`
PLP
:https://www.masswerk.at/6502/6502_instruction_set.html#PLProlPRotate One Bit Left (Memory or Accumulator)
C <- [76543210] <- C
NZCIDV
`+++---`ROL AROL oper
ROL oper,XROL oper
ROL oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#ROLrorQRotate One Bit Right (Memory or Accumulator)
C -> [76543210] -> C
NZCIDV
`+++---`ROR AROR oper
ROR oper,XROR oper
ROR oper,X
:https://www.masswerk.at/6502/6502_instruction_set.html#RORrti�Return from Interrupt
The status register is pulled with the break flagand bit 5 ignored. Then PC is pulled from the stack.
pull SR, pull PC
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`from stack`
RTI
:https://www.masswerk.at/6502/6502_instruction_set.html#RTIrts:Return from Subroutine
pull PC, PC+1 -> PC
NZCIDV
`------`
RTS
:https://www.masswerk.at/6502/6502_instruction_set.html#RTSsbcMSubtract Memory from Accumulator with Borrow
A - M - C̅ -> A
NZCIDV
`+++--+`	SBC #operSBC oper
SBC oper,XSBC oper
SBC oper,X
SBC oper,YSBC (oper,X)SBC (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#SBCsec%Set Carry Flag
1 -> C
NZCIDV
`--1---`
SEC
:https://www.masswerk.at/6502/6502_instruction_set.html#SECsed'Set Decimal Flag
1 -> D
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`----1-`
SED
:https://www.masswerk.at/6502/6502_instruction_set.html#SEDsei3Set Interrupt Disable Status
1 -> I
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`---1--`
SEI
:https://www.masswerk.at/6502/6502_instruction_set.html#SEIsta2Store Accumulator in Memory
A -> M
NZCIDV
`------`STA oper
STA oper,XSTA oper
STA oper,X
STA oper,YSTA (oper,X)STA (oper),Y
:https://www.masswerk.at/6502/6502_instruction_set.html#STAstx.Store Index X in Memory
X -> M
NZCIDV
`------`STX oper
STX oper,YSTX oper
:https://www.masswerk.at/6502/6502_instruction_set.html#STXsty-Sore Index Y in Memory
Y -> M
NZCIDV
`------`STY oper
STY oper,XSTY oper
:https://www.masswerk.at/6502/6502_instruction_set.html#STYtax6Transfer Accumulator to Index X
A -> X
NZCIDV
`++----`
TAX
:https://www.masswerk.at/6502/6502_instruction_set.html#TAXtay6Transfer Accumulator to Index Y
A -> Y
NZCIDV
`++----`
TAY
:https://www.masswerk.at/6502/6502_instruction_set.html#TAYtsx9Transfer Stack Pointer to Index X
SP -> X
NZCIDV
`++----`
TSX
:https://www.masswerk.at/6502/6502_instruction_set.html#TSXtxa6Transfer Index X to Accumulator
X -> A
NZCIDV
`++----`
TXA
:https://www.masswerk.at/6502/6502_instruction_set.html#TXAtxs:Transfer Index X to Stack Register
X -> SP
NZCIDV
`------`
TXS
:https://www.masswerk.at/6502/6502_instruction_set.html#TXStya6Transfer Index Y to Accumulator
Y -> A
NZCIDV
`++----`
TYA
:https://www.masswerk.at/6502/6502_instruction_set.html#TYA