Struct stm32_hal2::pac::i2c1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cr1: Reg<CR1_SPEC>,
    pub cr2: Reg<CR2_SPEC>,
    pub oar1: Reg<OAR1_SPEC>,
    pub oar2: Reg<OAR2_SPEC>,
    pub timingr: Reg<TIMINGR_SPEC>,
    pub timeoutr: Reg<TIMEOUTR_SPEC>,
    pub isr: Reg<ISR_SPEC>,
    pub icr: Reg<ICR_SPEC>,
    pub pecr: Reg<PECR_SPEC>,
    pub rxdr: Reg<RXDR_SPEC>,
    pub txdr: Reg<TXDR_SPEC>,
}

Register block

Fields

cr1: Reg<CR1_SPEC>

0x00 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

cr2: Reg<CR2_SPEC>

0x04 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

oar1: Reg<OAR1_SPEC>

0x08 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

oar2: Reg<OAR2_SPEC>

0x0c - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

timingr: Reg<TIMINGR_SPEC>

0x10 - Access: No wait states

timeoutr: Reg<TIMEOUTR_SPEC>

0x14 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

isr: Reg<ISR_SPEC>

0x18 - Access: No wait states

icr: Reg<ICR_SPEC>

0x1c - Access: No wait states

pecr: Reg<PECR_SPEC>

0x20 - Access: No wait states

rxdr: Reg<RXDR_SPEC>

0x24 - Access: No wait states

txdr: Reg<TXDR_SPEC>

0x28 - Access: No wait states