Struct stm32_hal2::pac::i2c1::timeoutr::TIMEOUTR_SPEC

pub struct TIMEOUTR_SPEC;

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see timeoutr module

Trait Implementations

impl Readable for TIMEOUTR_SPEC

read() method returns timeoutr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for TIMEOUTR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for TIMEOUTR_SPEC

reset() method sets TIMEOUTR to value 0

fn reset_value() -> <TIMEOUTR_SPEC as RegisterSpec>::Ux

Reset value of the register.

impl Writable for TIMEOUTR_SPEC

write(|w| ..) method takes timeoutr::W writer structure

type Writer = W

Writer type argument to write, et al.