pub struct OAR1_SPEC;
Expand description
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
This register you can read
, write_with_zero
, reset
, write
, modify
. See API.
For information about available fields see oar1 module
Trait Implementations
sourceimpl RegisterSpec for OAR1_SPEC
impl RegisterSpec for OAR1_SPEC
sourceimpl Resettable for OAR1_SPEC
impl Resettable for OAR1_SPEC
reset()
method sets OAR1 to value 0
sourcefn reset_value() -> <OAR1_SPEC as RegisterSpec>::Ux
fn reset_value() -> <OAR1_SPEC as RegisterSpec>::Ux
Reset value of the register.
Auto Trait Implementations
impl RefUnwindSafe for OAR1_SPEC
impl Send for OAR1_SPEC
impl Sync for OAR1_SPEC
impl Unpin for OAR1_SPEC
impl UnwindSafe for OAR1_SPEC
Blanket Implementations
sourceimpl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more