Trait rust_hdl::prelude::Logic

pub trait Logic {
    // Required method
    fn update(&mut self);

    // Provided methods
    fn connect(&mut self) { ... }
    fn hdl(&self) -> Verilog { ... }
    fn timing(&self) -> Vec<TimingInfo, Global> { ... }
}

Required Methods

fn update(&mut self)

Provided Methods

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>

Implementations on Foreign Types

impl<L, const P: usize> Logic for [L; P]where L: Logic,

fn update(&mut self)

impl<L> Logic for Vec<L, Global>where L: Logic,

fn update(&mut self)

impl<T> Logic for EdgeDFF<T>where T: Synth,

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>

impl<const D: usize> Logic for SDRAMDevice<D>

fn update(&mut self)

fn connect(&mut self)

impl<const N: usize, const M: usize, const P: usize> Logic for Accum<N, M, P>

fn update(&mut self)

impl<const W: usize> Logic for RegisteredEdgeTristate<W>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl Logic for SDRAMCommandDecoder

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl<D, const N: usize> Logic for RAMWrite<D, N>where D: Synth,

fn update(&mut self)

fn connect(&mut self)

impl Logic for SDRAMCommandEncoder

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>where D: Synth,

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl Logic for I2CDriver

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOReadLogic<D, N, NP1, BLOCK_SIZE>where D: Synth,

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl Logic for I2CController

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl Logic for ADS8688Simulator

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl Logic for MuxedMAX31856Simulators

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl<const R: usize, const C: usize, const A: usize, const D: usize> Logic for MemoryBank<R, C, A, D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

Implementors

impl Logic for AD7193Simulator

impl Logic for ADS868XSimulator

impl Logic for AutoReset

impl Logic for BitSynchronizer

impl Logic for EdgeDetector

impl Logic for FaderWithSyncROM

impl Logic for I2CBusDriver

impl Logic for I2CBusReceiver

impl Logic for I2CTarget

impl Logic for I2CTestTarget

impl Logic for LFSRSimple

impl Logic for MAX31856Simulator

impl Logic for MuxedAD7193Simulators

impl Logic for OpenDrainBuffer

impl Logic for OpenDrainDriver

impl Logic for OpenDrainReceiver

impl Logic for Pulser

impl Logic for SPIWiresMaster

impl Logic for SPIWiresSlave

impl Logic for SoCTestChip

impl<D> Logic for TristateBuffer<D>where D: Synth,

impl<D, T> Logic for Signal<D, T>where D: Direction, T: Synth,

impl<D, const N: usize> Logic for RAM<D, N>where D: Synth,

impl<D, const N: usize> Logic for ROM<D, N>where D: Synth,

impl<D, const N: usize> Logic for SyncROM<D, N>where D: Synth,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>where D: Synth,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for SynchronousFIFO<D, N, NP1, BLOCK_SIZE>where D: Synth,

impl<D, const N: usize, const W: usize> Logic for DelayLine<D, N, W>where D: Synth,

impl<T> Logic for BidiBusD<T>where T: Synth,

impl<T> Logic for BidiBusM<T>where T: Synth,

impl<T> Logic for BidiMaster<T>where T: Synth,

impl<T> Logic for BidiSimulatedDevice<T>where T: Synth,

impl<T> Logic for Constant<T>where T: Synth,

impl<T> Logic for DFF<T>where T: Synth,

impl<T> Logic for DFFWithInit<T>where T: Synth + BitXor<T, Output = T>,

impl<T> Logic for FIFOLink<T>where T: Synth,

impl<T> Logic for FIFOReadController<T>where T: Synth,

impl<T> Logic for FIFOReadResponder<T>where T: Synth,

impl<T> Logic for FIFOWriteController<T>where T: Synth,

impl<T> Logic for FIFOWriteResponder<T>where T: Synth,

impl<T> Logic for RegisterFIFO<T>where T: Synth,

impl<T> Logic for SyncReceiver<T>where T: Synth,

impl<T> Logic for SyncSender<T>where T: Synth,

impl<T> Logic for VectorSynchronizer<T>where T: Synth,

impl<T, const N: usize> Logic for LazyFIFOFeeder<T, N>where T: Synth,

impl<T, const N: usize> Logic for LazyFIFOReader<T, N>where T: Synth,

impl<T, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for AsyncFIFO<T, N, NP1, BLOCK_SIZE>where T: Synth,

impl<T, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for SyncFIFO<T, N, NP1, BLOCK_SIZE>where T: Synth,

impl<U> Logic for TopWrap<U>where U: Block,

impl<const A: usize> Logic for BaseController<A>

impl<const A: usize> Logic for Host<A>

impl<const ADDR_BITS: usize> Logic for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const D: usize> Logic for MISOPort<D>

impl<const D: usize> Logic for MOSIPort<D>

impl<const D: usize> Logic for SDRAMDriver<D>

impl<const D: usize> Logic for SDRAMOnChipBuffer<D>

impl<const D: usize> Logic for SoCPortController<D>

impl<const D: usize> Logic for SoCPortResponder<D>

impl<const D: usize, const A: usize> Logic for SoCBusController<D, A>

impl<const D: usize, const A: usize> Logic for SoCBusResponder<D, A>

impl<const D: usize, const A: usize, const N: usize> Logic for Bridge<D, A, N>

impl<const D: usize, const A: usize, const N: usize> Logic for HLSSPIMuxMasters<D, A, N>

impl<const D: usize, const A: usize, const N: usize> Logic for HLSSPIMuxSlaves<D, A, N>

impl<const D: usize, const A: usize, const N: usize> Logic for Router<D, A, N>

impl<const D: usize, const A: usize, const N: usize> Logic for RouterROM<D, A, N>

impl<const D: usize, const A: usize, const W: usize> Logic for HLSSPIMaster<D, A, W>

impl<const D: usize, const A: usize, const W: usize> Logic for HLSSPIMasterDynamicMode<D, A, W>

impl<const DN: usize, const DW: usize> Logic for FIFOExpanderN<DN, DW>

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Logic for CrossWiden<DN, NN, NNP1, DW, WN, WNP1>

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Logic for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

impl<const DW: usize, const DN: usize> Logic for Expander<DN, DW>

impl<const DW: usize, const DN: usize> Logic for FIFOReducerN<DW, DN>

impl<const DW: usize, const DN: usize> Logic for Reducer<DW, DN>

impl<const DW: usize, const DN: usize, const REVERSE: bool> Logic for FIFOReducer<DW, DN, REVERSE>

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Logic for CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Logic for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

impl<const N: usize> Logic for I2CTestBus<N>

impl<const N: usize> Logic for MuxedADS868XSimulators<N>

impl<const N: usize> Logic for PulseWidthModulator<N>

impl<const N: usize> Logic for SPIMaster<N>

impl<const N: usize> Logic for SPIMasterDynamicMode<N>

impl<const N: usize> Logic for SPISlave<N>

impl<const N: usize> Logic for Shot<N>

impl<const N: usize> Logic for Strobe<N>

impl<const N: usize, const A: usize> Logic for MuxMasters<N, A>

impl<const N: usize, const A: usize> Logic for MuxSlaves<N, A>

impl<const R: usize, const C: usize> Logic for SDRAMController<R, C>

impl<const R: usize, const C: usize> Logic for SDRAMControllerTester<R, C>

impl<const R: usize, const C: usize, const A: usize, const D: usize> Logic for SDRAMSimulator<R, C, A, D>

impl<const R: usize, const C: usize, const L: u32, const D: usize> Logic for SDRAMBurstController<R, C, L, D>

impl<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> Logic for SDRAMFIFOController<R, C, L, D, A>

impl<const R: usize, const C: usize, const L: usize, const D: usize> Logic for SDRAMBaseController<R, C, L, D>

impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> Logic for SDRAMFIFO<R, C, P, D, A>

impl<const W: usize, const D: usize> Logic for MISOWidePort<W, D>

impl<const W: usize, const D: usize> Logic for MOSIWidePort<W, D>

impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Logic for MISOFIFOPort<W, N, NP1, BLOCK>

impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Logic for MOSIFIFOPort<W, N, NP1, BLOCK>