Trait Block

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pub trait Block: Logic {
    // Required methods
    fn connect_all(&mut self);
    fn update_all(&mut self);
    fn has_changed(&self) -> bool;
    fn accept(&self, name: &str, probe: &mut dyn Probe);
}
Expand description

The Block trait is required for all circuitry that can be simulated by RustHDL. If you want to be able to simulate a circuit, the corresponding struct must impl Block. Normally, this is done via the #[derive(LogicBlock)] construct, and you will rarely, if ever, need to impl the Block trait yourself.

Required Methods§

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fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

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fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

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fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

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fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

Implementations on Foreign Types§

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impl Block for ADS8688Simulator

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl Block for MuxedMAX31856Simulators

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl Block for I2CController

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl Block for I2CDriver

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl Block for SDRAMCommandDecoder

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl Block for SDRAMCommandEncoder

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<B> Block for Vec<B>
where B: Block,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<B, const P: usize> Block for [B; P]
where B: Block,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<D, const N: usize> Block for RAMWrite<D, N>
where D: Synth,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for FIFOReadLogic<D, N, NP1, BLOCK_SIZE>
where D: Synth,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>
where D: Synth,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<T> Block for EdgeDFF<T>
where T: Synth,

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<const D: usize> Block for SDRAMDevice<D>

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<const N: usize, const M: usize, const P: usize> Block for Accum<N, M, P>

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<const R: usize, const C: usize, const A: usize, const D: usize> Block for MemoryBank<R, C, A, D>

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<const W: usize> Block for RegisteredEdgeTristate<W>

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

Implementors§

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impl Block for AD7193Simulator

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impl Block for ADS868XSimulator

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impl Block for AutoReset

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impl Block for BitSynchronizer

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impl Block for EdgeDetector

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impl Block for FaderWithSyncROM

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impl Block for I2CBusDriver

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impl Block for I2CBusReceiver

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impl Block for I2CTarget

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impl Block for I2CTestTarget

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impl Block for LFSRSimple

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impl Block for MAX31856Simulator

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impl Block for MuxedAD7193Simulators

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impl Block for OpenDrainBuffer

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impl Block for OpenDrainDriver

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impl Block for OpenDrainReceiver

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impl Block for Pulser

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impl Block for SPIWiresMaster

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impl Block for SPIWiresSlave

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impl Block for SoCTestChip

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impl<D> Block for TristateBuffer<D>
where D: Synth,

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impl<D, T> Block for Signal<D, T>
where D: Direction, T: Synth,

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impl<D, const N: usize> Block for RAM<D, N>
where D: Synth,

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impl<D, const N: usize> Block for ROM<D, N>
where D: Synth,

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impl<D, const N: usize> Block for SyncROM<D, N>
where D: Synth,

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impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>
where D: Synth,

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impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for SynchronousFIFO<D, N, NP1, BLOCK_SIZE>
where D: Synth,

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impl<D, const N: usize, const W: usize> Block for DelayLine<D, N, W>
where D: Synth,

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impl<T> Block for BidiBusD<T>
where T: Synth,

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impl<T> Block for BidiBusM<T>
where T: Synth,

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impl<T> Block for BidiMaster<T>
where T: Synth,

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impl<T> Block for BidiSimulatedDevice<T>
where T: Synth,

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impl<T> Block for Constant<T>
where T: Synth,

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impl<T> Block for DFF<T>
where T: Synth,

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impl<T> Block for DFFWithInit<T>
where T: Synth + BitXor<Output = T>,

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impl<T> Block for FIFOLink<T>
where T: Synth,

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impl<T> Block for FIFOReadController<T>
where T: Synth,

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impl<T> Block for FIFOReadResponder<T>
where T: Synth,

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impl<T> Block for FIFOWriteController<T>
where T: Synth,

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impl<T> Block for FIFOWriteResponder<T>
where T: Synth,

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impl<T> Block for RegisterFIFO<T>
where T: Synth,

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impl<T> Block for SyncReceiver<T>
where T: Synth,

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impl<T> Block for SyncSender<T>
where T: Synth,

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impl<T> Block for VectorSynchronizer<T>
where T: Synth,

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impl<T, const N: usize> Block for LazyFIFOFeeder<T, N>
where T: Synth,

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impl<T, const N: usize> Block for LazyFIFOReader<T, N>
where T: Synth,

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impl<T, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for AsyncFIFO<T, N, NP1, BLOCK_SIZE>
where T: Synth,

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impl<T, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for SyncFIFO<T, N, NP1, BLOCK_SIZE>
where T: Synth,

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impl<U> Block for TopWrap<U>
where U: Block,

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impl<const A: usize> Block for BaseController<A>

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impl<const A: usize> Block for Host<A>

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impl<const ADDR_BITS: usize> Block for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

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impl<const D: usize> Block for MISOPort<D>

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impl<const D: usize> Block for MOSIPort<D>

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impl<const D: usize> Block for SDRAMDriver<D>

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impl<const D: usize> Block for SDRAMOnChipBuffer<D>

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impl<const D: usize> Block for SoCPortController<D>

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impl<const D: usize> Block for SoCPortResponder<D>

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impl<const D: usize, const A: usize> Block for SoCBusController<D, A>

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impl<const D: usize, const A: usize> Block for SoCBusResponder<D, A>

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impl<const D: usize, const A: usize, const N: usize> Block for Bridge<D, A, N>

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impl<const D: usize, const A: usize, const N: usize> Block for HLSSPIMuxMasters<D, A, N>

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impl<const D: usize, const A: usize, const N: usize> Block for HLSSPIMuxSlaves<D, A, N>

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impl<const D: usize, const A: usize, const N: usize> Block for Router<D, A, N>

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impl<const D: usize, const A: usize, const N: usize> Block for RouterROM<D, A, N>

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impl<const D: usize, const A: usize, const W: usize> Block for HLSSPIMaster<D, A, W>

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impl<const D: usize, const A: usize, const W: usize> Block for HLSSPIMasterDynamicMode<D, A, W>

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impl<const DN: usize, const DW: usize> Block for Expander<DN, DW>

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impl<const DN: usize, const DW: usize> Block for FIFOExpanderN<DN, DW>

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impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Block for CrossWiden<DN, NN, NNP1, DW, WN, WNP1>

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impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Block for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

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impl<const DW: usize, const DN: usize> Block for FIFOReducerN<DW, DN>

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impl<const DW: usize, const DN: usize> Block for Reducer<DW, DN>

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impl<const DW: usize, const DN: usize, const REVERSE: bool> Block for FIFOReducer<DW, DN, REVERSE>

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impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Block for CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

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impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Block for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

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impl<const N: usize> Block for I2CTestBus<N>

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impl<const N: usize> Block for MuxedADS868XSimulators<N>

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impl<const N: usize> Block for PulseWidthModulator<N>

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impl<const N: usize> Block for SPIMaster<N>

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impl<const N: usize> Block for SPIMasterDynamicMode<N>

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impl<const N: usize> Block for SPISlave<N>

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impl<const N: usize> Block for Shot<N>

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impl<const N: usize> Block for Strobe<N>

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impl<const N: usize, const A: usize> Block for MuxMasters<N, A>

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impl<const N: usize, const A: usize> Block for MuxSlaves<N, A>

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impl<const R: usize, const C: usize> Block for SDRAMController<R, C>

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impl<const R: usize, const C: usize> Block for SDRAMControllerTester<R, C>

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impl<const R: usize, const C: usize, const A: usize, const D: usize> Block for SDRAMSimulator<R, C, A, D>

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impl<const R: usize, const C: usize, const L: u32, const D: usize> Block for SDRAMBurstController<R, C, L, D>

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impl<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> Block for SDRAMFIFOController<R, C, L, D, A>

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impl<const R: usize, const C: usize, const L: usize, const D: usize> Block for SDRAMBaseController<R, C, L, D>

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impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> Block for SDRAMFIFO<R, C, P, D, A>

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impl<const W: usize, const D: usize> Block for MISOWidePort<W, D>

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impl<const W: usize, const D: usize> Block for MOSIWidePort<W, D>

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impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Block for MISOFIFOPort<W, N, NP1, BLOCK>

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impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Block for MOSIFIFOPort<W, N, NP1, BLOCK>