Struct FIFOWriteController

pub struct FIFOWriteController<T>
where
    T: Synth,
{
    pub data: Signal<Out, T>,
    pub write: Signal<Out, bool>,
    pub full: Signal<In, bool>,
    pub almost_full: Signal<In, bool>,
}

Fields

data: Signal<Out, T>

write: Signal<Out, bool>

full: Signal<In, bool>

almost_full: Signal<In, bool>

Implementations

impl<T> FIFOWriteController<T>

where T: Synth,

pub fn join(&mut self, other: &mut FIFOWriteResponder<T>)

Trait Implementations

impl<T> Block for FIFOWriteController<T>

where T: Synth,

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T> Clone for FIFOWriteController<T>

where T: Clone + Synth,

fn clone(&self) -> FIFOWriteController<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T> Debug for FIFOWriteController<T>

where T: Debug + Synth,

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl<T> Default for FIFOWriteController<T>

where T: Default + Synth,

fn default() -> FIFOWriteController<T>

Returns the “default value” for a type.

impl<T> Logic for FIFOWriteController<T>

where T: Synth,

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl<T> LogicJoin for FIFOWriteController<T>

where T: Synth,

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl<T> LogicLink for FIFOWriteController<T>

where T: Synth,

fn link(&mut self, other: &mut FIFOWriteController<T>)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>