Crate rp2040_pac
source · [−]Expand description
Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.21.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use pll_sys as pll_usb;pub use uart0 as uart1;pub use spi0 as spi1;pub use i2c0 as i2c1;pub use pio0 as pio1;Modules
Control and data interface to SAR ADC
Register block for busfabric control signals and performance counters
CLOCKS
DMA with separate read and write masters
Common register and bit access and modify traits
DW_apb_i2c address block
IO_BANK0
IO_QSPI
PADS_BANK0
PADS_QSPI
Programmable IO block
PLL_SYS
PPB
PSM
Simple PWM
RESETS
ROSC
Register block to control RTC
Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.
SPI0
Register block for various chip control signals
SYSINFO
Testbench manager. Allows the programmer to know what platform their software is running on.
Controls time and alarms
time is a 64 bit value indicating the time in usec since power-on
timeh is the top 32 bits of time & timel is the bottom 32 bits
to change time write to timelw before timehw
to read time read from timelr before timehr
An alarm is set by setting alarm_enable and writing to the corresponding alarm register
When an alarm is pending, the corresponding alarm_running signal will be high
An alarm can be cancelled before it has finished by clearing the alarm_enable
When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
To clear the interrupt write a 1 to the corresponding alarm_irq
UART0
DPRAM layout for USB device.
USB FS/LS controller device registers
control and status for on-chip voltage regulator and chip level reset subsystem
WATCHDOG
QSPI flash execute-in-place block
DW_apb_ssi has the following features:
Controls the crystal oscillator
Structs
Control and data interface to SAR ADC
Register block for busfabric control signals and performance counters
Cache and branch predictor maintenance operations
CLOCKS
CPUID
Core peripherals
Debug Control Block
DMA with separate read and write masters
Data Watchpoint and Trace unit
Flash Patch and Breakpoint unit
DW_apb_i2c address block
DW_apb_i2c address block
IO_BANK0
IO_QSPI
Instrumentation Trace Macrocell
Memory Protection Unit
Nested Vector Interrupt Controller
PADS_BANK0
PADS_QSPI
Programmable IO block
Programmable IO block
PLL_SYS
PLL_USB
PPB
PSM
Simple PWM
All the peripherals
RESETS
ROSC
Register block to control RTC
System Control Block
Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.
SPI0
SPI1
Register block for various chip control signals
SYSINFO
SysTick: System Timer
Testbench manager. Allows the programmer to know what platform their software is running on.
Controls time and alarms
time is a 64 bit value indicating the time in usec since power-on
timeh is the top 32 bits of time & timel is the bottom 32 bits
to change time write to timelw before timehw
to read time read from timelr before timehr
An alarm is set by setting alarm_enable and writing to the corresponding alarm register
When an alarm is pending, the corresponding alarm_running signal will be high
An alarm can be cancelled before it has finished by clearing the alarm_enable
When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
To clear the interrupt write a 1 to the corresponding alarm_irq
Trace Port Interface Unit
UART0
UART1
DPRAM layout for USB device.
USB FS/LS controller device registers
control and status for on-chip voltage regulator and chip level reset subsystem
WATCHDOG
QSPI flash execute-in-place block
DW_apb_ssi has the following features:
Controls the crystal oscillator
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority