Module rp2040_pac::pll_sys
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PLL_SYS
Modules
Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=400MHz, max=1600MHz
Feedback divisor
(note: this PLL does not support fractional division)
Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2
Controls the PLL power modes.
Structs
Register block