Module rp2040_pac::syscfg
source · [−]Expand description
Register block for various chip control signals
Modules
Directly control the SWD debug port of either processor
Control power downs to memories. Set high to power down memories.
Use with extreme caution
Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ
Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ
Configuration for processors
For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.
For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).
Structs
Register block
Type Definitions
DBGFORCE register accessor: an alias for Reg<DBGFORCE_SPEC>
MEMPOWERDOWN register accessor: an alias for Reg<MEMPOWERDOWN_SPEC>
PROC0_NMI_MASK register accessor: an alias for Reg<PROC0_NMI_MASK_SPEC>
PROC1_NMI_MASK register accessor: an alias for Reg<PROC1_NMI_MASK_SPEC>
PROC_CONFIG register accessor: an alias for Reg<PROC_CONFIG_SPEC>
PROC_IN_SYNC_BYPASS register accessor: an alias for Reg<PROC_IN_SYNC_BYPASS_SPEC>
PROC_IN_SYNC_BYPASS_HI register accessor: an alias for Reg<PROC_IN_SYNC_BYPASS_HI_SPEC>