Module rp2040_pac::i2c0
source · [−]Expand description
DW_apb_i2c address block
List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are fixed values, set at hardware design time):
IC_ULTRA_FAST_MODE ……………. 0x0
IC_UFM_TBUF_CNT_DEFAULT ……….. 0x8
IC_UFM_SCL_LOW_COUNT ………….. 0x0008
IC_UFM_SCL_HIGH_COUNT …………. 0x0006
IC_TX_TL …………………….. 0x0
IC_TX_CMD_BLOCK ………………. 0x1
IC_HAS_DMA …………………… 0x1
IC_HAS_ASYNC_FIFO …………….. 0x0
IC_SMBUS_ARP …………………. 0x0
IC_FIRST_DATA_BYTE_STATUS ……… 0x1
IC_INTR_IO …………………… 0x1
IC_MASTER_MODE ……………….. 0x1
IC_DEFAULT_ACK_GENERAL_CALL ……. 0x1
IC_INTR_POL ………………….. 0x1
IC_OPTIONAL_SAR ………………. 0x0
IC_DEFAULT_TAR_SLAVE_ADDR ……… 0x055
IC_DEFAULT_SLAVE_ADDR …………. 0x055
IC_DEFAULT_HS_SPKLEN ………….. 0x1
IC_FS_SCL_HIGH_COUNT ………….. 0x0006
IC_HS_SCL_LOW_COUNT …………… 0x0008
IC_DEVICE_ID_VALUE ……………. 0x0
IC_10BITADDR_MASTER …………… 0x0
IC_CLK_FREQ_OPTIMIZATION ………. 0x0
IC_DEFAULT_FS_SPKLEN ………….. 0x7
IC_ADD_ENCODED_PARAMS …………. 0x0
IC_DEFAULT_SDA_HOLD …………… 0x000001
IC_DEFAULT_SDA_SETUP ………….. 0x64
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
IC_CLOCK_PERIOD ………………. 100
IC_EMPTYFIFO_HOLD_MASTER_EN ……. 1
IC_RESTART_EN ………………… 0x1
IC_TX_CMD_BLOCK_DEFAULT ……….. 0x0
IC_BUS_CLEAR_FEATURE ………….. 0x0
IC_CAP_LOADING ……………….. 100
IC_FS_SCL_LOW_COUNT …………… 0x000d
APB_DATA_WIDTH ……………….. 32
IC_SDA_STUCK_TIMEOUT_DEFAULT …… 0xffffffff
IC_SLV_DATA_NACK_ONLY …………. 0x1
IC_10BITADDR_SLAVE ……………. 0x0
IC_CLK_TYPE ………………….. 0x0
IC_SMBUS_UDID_MSB …………….. 0x0
IC_SMBUS_SUSPEND_ALERT ………… 0x0
IC_HS_SCL_HIGH_COUNT ………….. 0x0006
IC_SLV_RESTART_DET_EN …………. 0x1
IC_SMBUS …………………….. 0x0
IC_OPTIONAL_SAR_DEFAULT ……….. 0x0
IC_PERSISTANT_SLV_ADDR_DEFAULT …. 0x0
IC_USE_COUNTS ………………… 0x0
IC_RX_BUFFER_DEPTH ……………. 16
IC_SCL_STUCK_TIMEOUT_DEFAULT …… 0xffffffff
IC_RX_FULL_HLD_BUS_EN …………. 0x1
IC_SLAVE_DISABLE ……………… 0x1
IC_RX_TL …………………….. 0x0
IC_DEVICE_ID …………………. 0x0
IC_HC_COUNT_VALUES ……………. 0x0
I2C_DYNAMIC_TAR_UPDATE ………… 0
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ….. 0xffffffff
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ….. 0xffffffff
IC_HS_MASTER_CODE …………….. 0x1
IC_SMBUS_RST_IDLE_CNT_DEFAULT ….. 0xffff
IC_SMBUS_UDID_LSB_DEFAULT ……… 0xffffffff
IC_SS_SCL_HIGH_COUNT ………….. 0x0028
IC_SS_SCL_LOW_COUNT …………… 0x002f
IC_MAX_SPEED_MODE …………….. 0x2
IC_STAT_FOR_CLK_STRETCH ……….. 0x0
IC_STOP_DET_IF_MASTER_ACTIVE …… 0x0
IC_DEFAULT_UFM_SPKLEN …………. 0x1
IC_TX_BUFFER_DEPTH ……………. 16
Modules
I2C ACK General Call Register
Clear ACTIVITY Interrupt Register
Clear GEN_CALL Interrupt Register
Clear Combined and Individual Interrupt Register
Clear RD_REQ Interrupt Register
Clear RESTART_DET Interrupt Register
Clear RX_DONE Interrupt Register
Clear RX_OVER Interrupt Register
Clear RX_UNDER Interrupt Register
Clear START_DET Interrupt Register
Clear STOP_DET Interrupt Register
Clear TX_ABRT Interrupt Register
Clear TX_OVER Interrupt Register
Component Parameter Register 1
I2C Component Type Register
I2C Component Version Register
I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
DMA Control Register
I2C Receive Data Level Register
DMA Transmit Data Level Register
I2C Enable Register
I2C Enable Status Register
Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
I2C SS, FS or FM+ spike suppression limit
I2C Interrupt Mask Register.
I2C Interrupt Status Register
I2C Raw Interrupt Status Register
I2C Receive FIFO Threshold Register
I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
I2C Slave Address Register
I2C SDA Hold Time Length Register
I2C SDA Setup Register
Generate Slave Data NACK Register
Standard Speed I2C Clock SCL High Count Register
Standard Speed I2C Clock SCL Low Count Register
I2C Status Register
I2C Target Address Register
I2C Transmit Abort Source Register
I2C Transmit FIFO Threshold Register
I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
Structs
Register block
Type Definitions
IC_ACK_GENERAL_CALL register accessor: an alias for Reg<IC_ACK_GENERAL_CALL_SPEC>
IC_CLR_ACTIVITY register accessor: an alias for Reg<IC_CLR_ACTIVITY_SPEC>
IC_CLR_GEN_CALL register accessor: an alias for Reg<IC_CLR_GEN_CALL_SPEC>
IC_CLR_INTR register accessor: an alias for Reg<IC_CLR_INTR_SPEC>
IC_CLR_RD_REQ register accessor: an alias for Reg<IC_CLR_RD_REQ_SPEC>
IC_CLR_RESTART_DET register accessor: an alias for Reg<IC_CLR_RESTART_DET_SPEC>
IC_CLR_RX_DONE register accessor: an alias for Reg<IC_CLR_RX_DONE_SPEC>
IC_CLR_RX_OVER register accessor: an alias for Reg<IC_CLR_RX_OVER_SPEC>
IC_CLR_RX_UNDER register accessor: an alias for Reg<IC_CLR_RX_UNDER_SPEC>
IC_CLR_START_DET register accessor: an alias for Reg<IC_CLR_START_DET_SPEC>
IC_CLR_STOP_DET register accessor: an alias for Reg<IC_CLR_STOP_DET_SPEC>
IC_CLR_TX_ABRT register accessor: an alias for Reg<IC_CLR_TX_ABRT_SPEC>
IC_CLR_TX_OVER register accessor: an alias for Reg<IC_CLR_TX_OVER_SPEC>
IC_COMP_PARAM_1 register accessor: an alias for Reg<IC_COMP_PARAM_1_SPEC>
IC_COMP_TYPE register accessor: an alias for Reg<IC_COMP_TYPE_SPEC>
IC_COMP_VERSION register accessor: an alias for Reg<IC_COMP_VERSION_SPEC>
IC_CON register accessor: an alias for Reg<IC_CON_SPEC>
IC_DATA_CMD register accessor: an alias for Reg<IC_DATA_CMD_SPEC>
IC_DMA_CR register accessor: an alias for Reg<IC_DMA_CR_SPEC>
IC_DMA_RDLR register accessor: an alias for Reg<IC_DMA_RDLR_SPEC>
IC_DMA_TDLR register accessor: an alias for Reg<IC_DMA_TDLR_SPEC>
IC_ENABLE register accessor: an alias for Reg<IC_ENABLE_SPEC>
IC_ENABLE_STATUS register accessor: an alias for Reg<IC_ENABLE_STATUS_SPEC>
IC_FS_SCL_HCNT register accessor: an alias for Reg<IC_FS_SCL_HCNT_SPEC>
IC_FS_SCL_LCNT register accessor: an alias for Reg<IC_FS_SCL_LCNT_SPEC>
IC_FS_SPKLEN register accessor: an alias for Reg<IC_FS_SPKLEN_SPEC>
IC_INTR_MASK register accessor: an alias for Reg<IC_INTR_MASK_SPEC>
IC_INTR_STAT register accessor: an alias for Reg<IC_INTR_STAT_SPEC>
IC_RAW_INTR_STAT register accessor: an alias for Reg<IC_RAW_INTR_STAT_SPEC>
IC_RXFLR register accessor: an alias for Reg<IC_RXFLR_SPEC>
IC_RX_TL register accessor: an alias for Reg<IC_RX_TL_SPEC>
IC_SAR register accessor: an alias for Reg<IC_SAR_SPEC>
IC_SDA_HOLD register accessor: an alias for Reg<IC_SDA_HOLD_SPEC>
IC_SDA_SETUP register accessor: an alias for Reg<IC_SDA_SETUP_SPEC>
IC_SLV_DATA_NACK_ONLY register accessor: an alias for Reg<IC_SLV_DATA_NACK_ONLY_SPEC>
IC_SS_SCL_HCNT register accessor: an alias for Reg<IC_SS_SCL_HCNT_SPEC>
IC_SS_SCL_LCNT register accessor: an alias for Reg<IC_SS_SCL_LCNT_SPEC>
IC_STATUS register accessor: an alias for Reg<IC_STATUS_SPEC>
IC_TAR register accessor: an alias for Reg<IC_TAR_SPEC>
IC_TXFLR register accessor: an alias for Reg<IC_TXFLR_SPEC>
IC_TX_ABRT_SOURCE register accessor: an alias for Reg<IC_TX_ABRT_SOURCE_SPEC>
IC_TX_TL register accessor: an alias for Reg<IC_TX_TL_SPEC>