#[doc = "Register `APPSS_IRQ_REQ_SEL` reader"]
pub type R = crate::R<AppssIrqReqSelSpec>;
#[doc = "Register `APPSS_IRQ_REQ_SEL` writer"]
pub type W = crate::W<AppssIrqReqSelSpec>;
#[doc = "Field `select` reader - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
pub type SelectR = crate::FieldReader<u32>;
#[doc = "Field `select` writer - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
pub type SelectW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
#[inline(always)]
pub fn select(&self) -> SelectR {
SelectR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
#[inline(always)]
#[must_use]
pub fn select(&mut self) -> SelectW<AppssIrqReqSelSpec> {
SelectW::new(self, 0)
}
}
#[doc = "APPSS_IRQ_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_irq_req_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_irq_req_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssIrqReqSelSpec;
impl crate::RegisterSpec for AppssIrqReqSelSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`appss_irq_req_sel::R`](R) reader structure"]
impl crate::Readable for AppssIrqReqSelSpec {}
#[doc = "`write(|w| ..)` method takes [`appss_irq_req_sel::W`](W) writer structure"]
impl crate::Writable for AppssIrqReqSelSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets APPSS_IRQ_REQ_SEL to value 0"]
impl crate::Resettable for AppssIrqReqSelSpec {
const RESET_VALUE: u32 = 0;
}