xwrl64xx-pac 0.6.0

A Peripheral Access Crate for the ti xwrl64xx radar devkit
Documentation 
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#[doc = "Register `APPSS_CAPEVNT_SEL` reader"]
pub type R = crate::R<AppssCapevntSelSpec>;
#[doc = "Register `APPSS_CAPEVNT_SEL` writer"]
pub type W = crate::W<AppssCapevntSelSpec>;
#[doc = "Field `src0` reader - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
pub type Src0R = crate::FieldReader<u16>;
#[doc = "Field `src0` writer - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
pub type Src0W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `src1` reader - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
pub type Src1R = crate::FieldReader<u16>;
#[doc = "Field `src1` writer - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
pub type Src1W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
    #[doc = "Bits 0:11 - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
    #[inline(always)]
    pub fn src0(&self) -> Src0R {
        Src0R::new((self.bits & 0x0fff) as u16)
    }
    #[doc = "Bits 12:23 - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
    #[inline(always)]
    pub fn src1(&self) -> Src1R {
        Src1R::new(((self.bits >> 12) & 0x0fff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:11 - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
    #[inline(always)]
    #[must_use]
    pub fn src0(&mut self) -> Src0W<AppssCapevntSelSpec> {
        Src0W::new(self, 0)
    }
    #[doc = "Bits 12:23 - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
    #[inline(always)]
    #[must_use]
    pub fn src1(&mut self) -> Src1W<AppssCapevntSelSpec> {
        Src1W::new(self, 12)
    }
}
#[doc = "APPSS_CAPEVNT_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_capevnt_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_capevnt_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCapevntSelSpec;
impl crate::RegisterSpec for AppssCapevntSelSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`appss_capevnt_sel::R`](R) reader structure"]
impl crate::Readable for AppssCapevntSelSpec {}
#[doc = "`write(|w| ..)` method takes [`appss_capevnt_sel::W`](W) writer structure"]
impl crate::Writable for AppssCapevntSelSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets APPSS_CAPEVNT_SEL to value 0"]
impl crate::Resettable for AppssCapevntSelSpec {
    const RESET_VALUE: u32 = 0;
}