vyre 0.4.0

GPU compute intermediate representation with a standard operation library
Documentation 
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use crate::ir::{Expr, Program};
use crate::ops::primitive;
use crate::ops::{AlgebraicLaw, OpSpec, U32_OUTPUTS, U32_U32_INPUTS};

// Logical left shift of a u32 by a u32 amount.



pub const LAWS: &[AlgebraicLaw] = &[AlgebraicLaw::Bounded {
    lo: 0,
    hi: u32::MAX,
}];

/// Left shift operation.
#[derive(Debug, Clone, Copy, Default)]
pub struct Shl;

impl Shl {
    /// Declarative operation specification.
    ///
    /// Laws are declared as explicit `AlgebraicLaw` values on `SPEC`.
    pub const SPEC: OpSpec = OpSpec::composition_inlinable(
        "primitive.bitwise.shl",
        U32_U32_INPUTS,
        U32_OUTPUTS,
        LAWS,
        Self::program,
    );

    /// Build the canonical IR program.
    ///
    /// # Examples
    ///
    /// ```
    /// use vyre::ir::Expr;
    /// use vyre::ops::primitive::shl::Shl;
    ///
    /// let _expr = Expr::shl(Expr::u32(1), Expr::u32(4));
    /// let program = Shl::program();
    /// assert!(!program.entry().is_empty());
    /// ```
    #[must_use]
    pub fn program() -> Program {
        primitive::binary_u32_program(Expr::shl)
    }
}

// Backend-specific lowering tripwires for shl.

// WGSL lowering marker for `primitive.bitwise.shl`.
//
// Not a stub: this is a zero-overhead Category A marker. `Shl::program`
// builds concrete IR through `core/src/ops/primitive/mod.rs::binary_u32_program`; `core/src/lower/wgsl/expr.rs::emit_binop` emits WGSL.
// `core/tests/conformance.rs::conformance_all_primitives` verifies
// lowered GPU bytes are bit-exact against the conform CPU reference.
//
// ```wgsl
// _vyre_store_out(idx, (_vyre_load_a(idx) << (_vyre_load_b(idx) & 31u)));
// ```