vyre 0.4.0

GPU compute intermediate representation with a standard operation library
Documentation 
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use crate::ir::{Expr, Program};
use crate::ops::primitive;
use crate::ops::{AlgebraicLaw, OpSpec, U32_INPUTS, U32_OUTPUTS};

// Count trailing zero bits, ctz(0) = 32.



pub const LAWS: &[AlgebraicLaw] = &[AlgebraicLaw::Bounded { lo: 0, hi: 32 }];

/// Count trailing zero bits, ctz(0) = 32 operation.
#[derive(Debug, Clone, Copy, Default)]
pub struct Ctz;

impl Ctz {
    /// Declarative operation specification.
    ///
    /// Laws are declared as explicit `AlgebraicLaw` values on `SPEC`.
    pub const SPEC: OpSpec = OpSpec::composition_inlinable(
        "primitive.bitwise.ctz",
        U32_INPUTS,
        U32_OUTPUTS,
        LAWS,
        Self::program,
    );

    /// Build the canonical IR program.
    ///
    /// # Examples
    ///
    /// ```
    /// use vyre::ir::Expr;
    /// use vyre::ops::primitive::ctz::Ctz;
    ///
    /// let _expr = Expr::ctz(Expr::u32(0x0000_ff00));
    /// let program = Ctz::program();
    /// assert!(!program.entry().is_empty());
    /// ```
    #[must_use]
    pub fn program() -> Program {
        primitive::unary_u32_program(Expr::ctz)
    }
}

// Backend-specific lowering tripwires for ctz.

// WGSL lowering marker for `primitive.bitwise.ctz`.
//
// Not a stub: this is a zero-overhead Category A marker. `Ctz::program`
// builds concrete IR through `core/src/ops/primitive/mod.rs::unary_u32_program`; `core/src/lower/wgsl/expr.rs::emit_unop` emits WGSL.
// `core/tests/conformance.rs::conformance_all_primitives` verifies
// lowered GPU bytes are bit-exact against the conform CPU reference.
//
// ```wgsl
// _vyre_store_out(idx, countTrailingZeros(_vyre_load_a(idx)));
// ```