use crate::svd::{
create_bit_range, create_field_constraint, create_register, create_register_properties,
create_write_constraint,
};
use crate::Result;
/// Creates the Divisor Latch High.
pub fn create() -> Result<svd::RegisterCluster> {
Ok(svd::RegisterCluster::Register(
create_register(
"dlh",
"Divisor Latch High",
0x4,
create_register_properties(32, 0)?,
Some(&[
create_field_constraint(
"dlh",
"Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data.",
create_bit_range("[7:0]")?,
svd::Access::ReadWrite,
create_write_constraint(0, 0xff)?,
None,
)?
]),
None,
)?
))
}