#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! TIM14
use crate::{RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// TIM14 control register 1
pub mod TIM14_CR1 {
/// CEN
pub mod CEN {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UDIS
pub mod UDIS {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// URS
pub mod URS {
/// Offset (2 bits)
pub const offset: u16 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OPM
pub mod OPM {
/// Offset (3 bits)
pub const offset: u16 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ARPE
pub mod ARPE {
/// Offset (7 bits)
pub const offset: u16 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CKD
pub mod CKD {
/// Offset (8 bits)
pub const offset: u16 = 8;
/// Mask (2 bits: 0b11 << 8)
pub const mask: u16 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UIFREMAP
pub mod UIFREMAP {
/// Offset (11 bits)
pub const offset: u16 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 Interrupt enable register
pub mod TIM14_DIER {
/// UIE
pub mod UIE {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1IE
pub mod CC1IE {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 status register
pub mod TIM14_SR {
/// UIF
pub mod UIF {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1IF
pub mod CC1IF {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1OF
pub mod CC1OF {
/// Offset (9 bits)
pub const offset: u16 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 event generation register
pub mod TIM14_EGR {
/// UG
pub mod UG {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1G
pub mod CC1G {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
pub mod TIM14_CCMR1 {
/// CC1S
pub mod CC1S {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1FE
pub mod OC1FE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1PE
pub mod OC1PE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1M
pub mod OC1M {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1M3
pub mod OC1M3 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 capture/compare enable register
pub mod TIM14_CCER {
/// CC1E
pub mod CC1E {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1P
pub mod CC1P {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1NP
pub mod CC1NP {
/// Offset (3 bits)
pub const offset: u16 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 counter
pub mod TIM14_CNT {
/// CNT
pub mod CNT {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UIFCPY
pub mod UIFCPY {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 prescaler
pub mod TIM14_PSC {
/// PSC
pub mod PSC {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 auto-reload register
pub mod TIM14_ARR {
/// ARR
pub mod ARR {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 capture/compare register 1
pub mod TIM14_CCR1 {
/// CCR1
pub mod CCR1 {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM14 timer input selection register
pub mod TIM14_TISEL {
/// TI1SEL
pub mod TI1SEL {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u16 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// TIM14 control register 1
pub TIM14_CR1: RWRegister<u16>,
_reserved1: [u32; 2],
_reserved2: [u16; 1],
/// TIM14 Interrupt enable register
pub TIM14_DIER: RWRegister<u16>,
_reserved3: [u16; 1],
/// TIM14 status register
pub TIM14_SR: RWRegister<u16>,
_reserved4: [u16; 1],
/// TIM14 event generation register
pub TIM14_EGR: WORegister<u16>,
_reserved5: [u16; 1],
/// The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
pub TIM14_CCMR1: RWRegister<u32>,
_reserved6: [u32; 1],
/// TIM14 capture/compare enable register
pub TIM14_CCER: RWRegister<u16>,
_reserved7: [u16; 1],
/// TIM14 counter
pub TIM14_CNT: RWRegister<u32>,
/// TIM14 prescaler
pub TIM14_PSC: RWRegister<u16>,
_reserved8: [u16; 1],
/// TIM14 auto-reload register
pub TIM14_ARR: RWRegister<u16>,
_reserved9: [u32; 1],
_reserved10: [u16; 1],
/// TIM14 capture/compare register 1
pub TIM14_CCR1: RWRegister<u16>,
_reserved11: [u32; 12],
_reserved12: [u16; 1],
/// TIM14 timer input selection register
pub TIM14_TISEL: RWRegister<u16>,
}
pub struct ResetValues {
pub TIM14_CR1: u16,
pub TIM14_DIER: u16,
pub TIM14_SR: u16,
pub TIM14_EGR: u16,
pub TIM14_CCMR1: u32,
pub TIM14_CCER: u16,
pub TIM14_CNT: u32,
pub TIM14_PSC: u16,
pub TIM14_ARR: u16,
pub TIM14_CCR1: u16,
pub TIM14_TISEL: u16,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}
/// Access functions for the TIM14 peripheral instance
pub mod TIM14 {
use super::ResetValues;
#[cfg(not(feature = "nosync"))]
use super::Instance;
#[cfg(not(feature = "nosync"))]
const INSTANCE: Instance = Instance {
addr: 0x40008000,
_marker: ::core::marker::PhantomData,
};
/// Reset values for each field in TIM14
pub const reset: ResetValues = ResetValues {
TIM14_CR1: 0x00000000,
TIM14_DIER: 0x00000000,
TIM14_SR: 0x00000000,
TIM14_EGR: 0x00000000,
TIM14_CCMR1: 0x00000000,
TIM14_CCER: 0x00000000,
TIM14_CNT: 0x00000000,
TIM14_PSC: 0x00000000,
TIM14_ARR: 0x0000FFFF,
TIM14_CCR1: 0x00000000,
TIM14_TISEL: 0x00000000,
};
#[cfg(not(feature = "nosync"))]
#[allow(renamed_and_removed_lints)]
#[allow(private_no_mangle_statics)]
#[no_mangle]
static mut TIM14_TAKEN: bool = false;
/// Safe access to TIM14
///
/// This function returns `Some(Instance)` if this instance is not
/// currently taken, and `None` if it is. This ensures that if you
/// do get `Some(Instance)`, you are ensured unique access to
/// the peripheral and there cannot be data races (unless other
/// code uses `unsafe`, of course). You can then pass the
/// `Instance` around to other functions as required. When you're
/// done with it, you can call `release(instance)` to return it.
///
/// `Instance` itself dereferences to a `RegisterBlock`, which
/// provides access to the peripheral's registers.
#[cfg(not(feature = "nosync"))]
#[inline]
pub fn take() -> Option<Instance> {
external_cortex_m::interrupt::free(|_| unsafe {
if TIM14_TAKEN {
None
} else {
TIM14_TAKEN = true;
Some(INSTANCE)
}
})
}
/// Release exclusive access to TIM14
///
/// This function allows you to return an `Instance` so that it
/// is available to `take()` again. This function will panic if
/// you return a different `Instance` or if this instance is not
/// already taken.
#[cfg(not(feature = "nosync"))]
#[inline]
pub fn release(inst: Instance) {
external_cortex_m::interrupt::free(|_| unsafe {
if TIM14_TAKEN && inst.addr == INSTANCE.addr {
TIM14_TAKEN = false;
} else {
panic!("Released a peripheral which was not taken");
}
});
}
/// Unsafely steal TIM14
///
/// This function is similar to take() but forcibly takes the
/// Instance, marking it as taken irregardless of its previous
/// state.
#[cfg(not(feature = "nosync"))]
#[inline]
pub unsafe fn steal() -> Instance {
TIM14_TAKEN = true;
INSTANCE
}
}
/// Raw pointer to TIM14
///
/// Dereferencing this is unsafe because you are not ensured unique
/// access to the peripheral, so you may encounter data races with
/// other users of this peripheral. It is up to you to ensure you
/// will not cause data races.
///
/// This constant is provided for ease of use in unsafe code: you can
/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
pub const TIM14: *const RegisterBlock = 0x40008000 as *const _;