stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `PLL1SSCGR` reader
pub type R = crate::R<PLL1SSCGRrs>;
///Register `PLL1SSCGR` writer
pub type W = crate::W<PLL1SSCGRrs>;
///Field `MOD_PER` reader - Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
pub type MOD_PER_R = crate::FieldReader<u16>;
///Field `MOD_PER` writer - Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
pub type MOD_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
///Field `TPDFN_DIS1` reader - Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
pub type TPDFN_DIS1_R = crate::BitReader;
///Field `TPDFN_DIS1` writer - Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
pub type TPDFN_DIS1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RPDFN_DIS1` reader - Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
pub type RPDFN_DIS1_R = crate::BitReader;
///Field `RPDFN_DIS1` writer - Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
pub type RPDFN_DIS1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DWNSPREAD1` reader - Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
pub type DWNSPREAD1_R = crate::BitReader;
///Field `DWNSPREAD1` writer - Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
pub type DWNSPREAD1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `INC_STEP` reader - Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
pub type INC_STEP_R = crate::FieldReader<u16>;
///Field `INC_STEP` writer - Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
pub type INC_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
impl R {
    ///Bits 0:12 - Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
    #[inline(always)]
    pub fn mod_per(&self) -> MOD_PER_R {
        MOD_PER_R::new((self.bits & 0x1fff) as u16)
    }
    ///Bit 13 - Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
    #[inline(always)]
    pub fn tpdfn_dis1(&self) -> TPDFN_DIS1_R {
        TPDFN_DIS1_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
    #[inline(always)]
    pub fn rpdfn_dis1(&self) -> RPDFN_DIS1_R {
        RPDFN_DIS1_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
    #[inline(always)]
    pub fn dwnspread1(&self) -> DWNSPREAD1_R {
        DWNSPREAD1_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bits 16:30 - Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
    #[inline(always)]
    pub fn inc_step(&self) -> INC_STEP_R {
        INC_STEP_R::new(((self.bits >> 16) & 0x7fff) as u16)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLL1SSCGR")
            .field("mod_per", &self.mod_per())
            .field("tpdfn_dis1", &self.tpdfn_dis1())
            .field("rpdfn_dis1", &self.rpdfn_dis1())
            .field("dwnspread1", &self.dwnspread1())
            .field("inc_step", &self.inc_step())
            .finish()
    }
}
impl W {
    ///Bits 0:12 - Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
    #[inline(always)]
    pub fn mod_per(&mut self) -> MOD_PER_W<PLL1SSCGRrs> {
        MOD_PER_W::new(self, 0)
    }
    ///Bit 13 - Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
    #[inline(always)]
    pub fn tpdfn_dis1(&mut self) -> TPDFN_DIS1_W<PLL1SSCGRrs> {
        TPDFN_DIS1_W::new(self, 13)
    }
    ///Bit 14 - Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
    #[inline(always)]
    pub fn rpdfn_dis1(&mut self) -> RPDFN_DIS1_W<PLL1SSCGRrs> {
        RPDFN_DIS1_W::new(self, 14)
    }
    ///Bit 15 - Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
    #[inline(always)]
    pub fn dwnspread1(&mut self) -> DWNSPREAD1_W<PLL1SSCGRrs> {
        DWNSPREAD1_W::new(self, 15)
    }
    ///Bits 16:30 - Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
    #[inline(always)]
    pub fn inc_step(&mut self) -> INC_STEP_W<PLL1SSCGRrs> {
        INC_STEP_W::new(self, 16)
    }
}
/**RCC PLL1 Spread Spectrum Clock Generator register

You can [`read`](crate::Reg::read) this register and get [`pll1sscgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1sscgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct PLL1SSCGRrs;
impl crate::RegisterSpec for PLL1SSCGRrs {
    type Ux = u32;
}
///`read()` method returns [`pll1sscgr::R`](R) reader structure
impl crate::Readable for PLL1SSCGRrs {}
///`write(|w| ..)` method takes [`pll1sscgr::W`](W) writer structure
impl crate::Writable for PLL1SSCGRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets PLL1SSCGR to value 0
impl crate::Resettable for PLL1SSCGRrs {}