///Register `BMCFGR` reader
pub type R = crate::R<BMCFGRrs>;
///Register `BMCFGR` writer
pub type W = crate::W<BMCFGRrs>;
/**Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk\[5:1\] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk\[5:1\] = rcc_aclk = sys_bus_ck.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum HPRE {
///8: sys_ck divided by 2
Div2 = 8,
///9: sys_ck divided by 4
Div4 = 9,
///10: sys_ck divided by 8
Div8 = 10,
///11: sys_ck divided by 16
Div16 = 11,
///12: sys_ck divided by 64
Div64 = 12,
///13: sys_ck divided by 128
Div128 = 13,
///14: sys_ck divided by 256
Div256 = 14,
///15: sys_ck divided by 512
Div512 = 15,
///0: sys_ck not divided
Div1 = 0,
}
impl From<HPRE> for u8 {
#[inline(always)]
fn from(variant: HPRE) -> Self {
variant as _
}
}
impl crate::FieldSpec for HPRE {
type Ux = u8;
}
impl crate::IsEnum for HPRE {}
///Field `HPRE` reader - Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk\[5:1\] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk\[5:1\] = rcc_aclk = sys_bus_ck.
pub type HPRE_R = crate::FieldReader<HPRE>;
impl HPRE_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> HPRE {
match self.bits {
8 => HPRE::Div2,
9 => HPRE::Div4,
10 => HPRE::Div8,
11 => HPRE::Div16,
12 => HPRE::Div64,
13 => HPRE::Div128,
14 => HPRE::Div256,
15 => HPRE::Div512,
_ => HPRE::Div1,
}
}
///sys_ck divided by 2
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == HPRE::Div2
}
///sys_ck divided by 4
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == HPRE::Div4
}
///sys_ck divided by 8
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == HPRE::Div8
}
///sys_ck divided by 16
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == HPRE::Div16
}
///sys_ck divided by 64
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == HPRE::Div64
}
///sys_ck divided by 128
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == HPRE::Div128
}
///sys_ck divided by 256
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == HPRE::Div256
}
///sys_ck divided by 512
#[inline(always)]
pub fn is_div512(&self) -> bool {
*self == HPRE::Div512
}
///sys_ck not divided
#[inline(always)]
pub fn is_div1(&self) -> bool {
matches!(self.variant(), HPRE::Div1)
}
}
///Field `HPRE` writer - Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk\[5:1\] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk\[5:1\] = rcc_aclk = sys_bus_ck.
pub type HPRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, HPRE, crate::Safe>;
impl<'a, REG> HPRE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
///sys_ck divided by 2
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div2)
}
///sys_ck divided by 4
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div4)
}
///sys_ck divided by 8
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div8)
}
///sys_ck divided by 16
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div16)
}
///sys_ck divided by 64
#[inline(always)]
pub fn div64(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div64)
}
///sys_ck divided by 128
#[inline(always)]
pub fn div128(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div128)
}
///sys_ck divided by 256
#[inline(always)]
pub fn div256(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div256)
}
///sys_ck divided by 512
#[inline(always)]
pub fn div512(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div512)
}
///sys_ck not divided
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(HPRE::Div1)
}
}
impl R {
///Bits 0:3 - Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk\[5:1\] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk\[5:1\] = rcc_aclk = sys_bus_ck.
#[inline(always)]
pub fn hpre(&self) -> HPRE_R {
HPRE_R::new((self.bits & 0x0f) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BMCFGR").field("hpre", &self.hpre()).finish()
}
}
impl W {
///Bits 0:3 - Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk\[5:1\] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk\[5:1\] = rcc_aclk = sys_bus_ck.
#[inline(always)]
pub fn hpre(&mut self) -> HPRE_W<BMCFGRrs> {
HPRE_W::new(self, 0)
}
}
/**RCC AHB clock configuration register
You can [`read`](crate::Reg::read) this register and get [`bmcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct BMCFGRrs;
impl crate::RegisterSpec for BMCFGRrs {
type Ux = u32;
}
///`read()` method returns [`bmcfgr::R`](R) reader structure
impl crate::Readable for BMCFGRrs {}
///`write(|w| ..)` method takes [`bmcfgr::W`](W) writer structure
impl crate::Writable for BMCFGRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets BMCFGR to value 0
impl crate::Resettable for BMCFGRrs {}