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///Register `AHB3ENR` reader
pub type R = crate::R<AHB3ENRrs>;
///Register `AHB3ENR` writer
pub type W = crate::W<AHB3ENRrs>;
/**RNG peripheral clocks enable Set and reset by software.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RNGEN {
///0: The selected clock is disabled
Disabled = 0,
///1: The selected clock is enabled
Enabled = 1,
}
impl From<RNGEN> for bool {
#[inline(always)]
fn from(variant: RNGEN) -> Self {
variant as u8 != 0
}
}
///Field `RNGEN` reader - RNG peripheral clocks enable Set and reset by software.
pub type RNGEN_R = crate::BitReader<RNGEN>;
impl RNGEN_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> RNGEN {
match self.bits {
false => RNGEN::Disabled,
true => RNGEN::Enabled,
}
}
///The selected clock is disabled
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RNGEN::Disabled
}
///The selected clock is enabled
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RNGEN::Enabled
}
}
///Field `RNGEN` writer - RNG peripheral clocks enable Set and reset by software.
pub type RNGEN_W<'a, REG> = crate::BitWriter<'a, REG, RNGEN>;
impl<'a, REG> RNGEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///The selected clock is disabled
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(RNGEN::Disabled)
}
///The selected clock is enabled
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(RNGEN::Enabled)
}
}
///Field `HASHEN` reader - HASH peripheral clock enable Set and reset by software.
pub use RNGEN_R as HASHEN_R;
///Field `HASHEN` writer - HASH peripheral clock enable Set and reset by software.
pub use RNGEN_W as HASHEN_W;
impl R {
///Bit 0 - RNG peripheral clocks enable Set and reset by software.
#[inline(always)]
pub fn rngen(&self) -> RNGEN_R {
RNGEN_R::new((self.bits & 1) != 0)
}
///Bit 1 - HASH peripheral clock enable Set and reset by software.
#[inline(always)]
pub fn hashen(&self) -> HASHEN_R {
HASHEN_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AHB3ENR")
.field("rngen", &self.rngen())
.field("hashen", &self.hashen())
.finish()
}
}
impl W {
///Bit 0 - RNG peripheral clocks enable Set and reset by software.
#[inline(always)]
pub fn rngen(&mut self) -> RNGEN_W<AHB3ENRrs> {
RNGEN_W::new(self, 0)
}
///Bit 1 - HASH peripheral clock enable Set and reset by software.
#[inline(always)]
pub fn hashen(&mut self) -> HASHEN_W<AHB3ENRrs> {
HASHEN_W::new(self, 1)
}
}
/**RCC AHB3 clock enable register
You can [`read`](crate::Reg::read) this register and get [`ahb3enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct AHB3ENRrs;
impl crate::RegisterSpec for AHB3ENRrs {
type Ux = u32;
}
///`read()` method returns [`ahb3enr::R`](R) reader structure
impl crate::Readable for AHB3ENRrs {}
///`write(|w| ..)` method takes [`ahb3enr::W`](W) writer structure
impl crate::Writable for AHB3ENRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets AHB3ENR to value 0
impl crate::Resettable for AHB3ENRrs {}