///Register `CR` reader
pub type R = crate::R<CRrs>;
///Register `CR` writer
pub type W = crate::W<CRrs>;
/**ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADENR {
///0: ADC disabled
Disabled = 0,
///1: ADC enabled
Enabled = 1,
}
impl From<ADENR> for bool {
#[inline(always)]
fn from(variant: ADENR) -> Self {
variant as u8 != 0
}
}
///Field `ADEN` reader - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
pub type ADEN_R = crate::BitReader<ADENR>;
impl ADEN_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADENR {
match self.bits {
false => ADENR::Disabled,
true => ADENR::Enabled,
}
}
///ADC disabled
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADENR::Disabled
}
///ADC enabled
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADENR::Enabled
}
}
/**ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADENW {
///1: Enable the ADC
Enabled = 1,
}
impl From<ADENW> for bool {
#[inline(always)]
fn from(variant: ADENW) -> Self {
variant as u8 != 0
}
}
///Field `ADEN` writer - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
pub type ADEN_W<'a, REG> = crate::BitWriter1S<'a, REG, ADENW>;
impl<'a, REG> ADEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Enable the ADC
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ADENW::Enabled)
}
}
/**ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADDISR {
///0: No disable command active
NotDisabling = 0,
///1: ADC disabling
Disabling = 1,
}
impl From<ADDISR> for bool {
#[inline(always)]
fn from(variant: ADDISR) -> Self {
variant as u8 != 0
}
}
///Field `ADDIS` reader - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
pub type ADDIS_R = crate::BitReader<ADDISR>;
impl ADDIS_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADDISR {
match self.bits {
false => ADDISR::NotDisabling,
true => ADDISR::Disabling,
}
}
///No disable command active
#[inline(always)]
pub fn is_not_disabling(&self) -> bool {
*self == ADDISR::NotDisabling
}
///ADC disabling
#[inline(always)]
pub fn is_disabling(&self) -> bool {
*self == ADDISR::Disabling
}
}
/**ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADDISW {
///1: Disable the ADC
Disable = 1,
}
impl From<ADDISW> for bool {
#[inline(always)]
fn from(variant: ADDISW) -> Self {
variant as u8 != 0
}
}
///Field `ADDIS` writer - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
pub type ADDIS_W<'a, REG> = crate::BitWriter1S<'a, REG, ADDISW>;
impl<'a, REG> ADDIS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Disable the ADC
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(ADDISW::Disable)
}
}
/**ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADSTARTR {
///0: No conversion ongoing
NotActive = 0,
///1: ADC operating and may be converting
Active = 1,
}
impl From<ADSTARTR> for bool {
#[inline(always)]
fn from(variant: ADSTARTR) -> Self {
variant as u8 != 0
}
}
///Field `ADSTART` reader - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
pub type ADSTART_R = crate::BitReader<ADSTARTR>;
impl ADSTART_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADSTARTR {
match self.bits {
false => ADSTARTR::NotActive,
true => ADSTARTR::Active,
}
}
///No conversion ongoing
#[inline(always)]
pub fn is_not_active(&self) -> bool {
*self == ADSTARTR::NotActive
}
///ADC operating and may be converting
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == ADSTARTR::Active
}
}
/**ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADSTARTW {
///1: Start the ADC conversion (may be delayed for hardware triggers)
StartConversion = 1,
}
impl From<ADSTARTW> for bool {
#[inline(always)]
fn from(variant: ADSTARTW) -> Self {
variant as u8 != 0
}
}
///Field `ADSTART` writer - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
pub type ADSTART_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTARTW>;
impl<'a, REG> ADSTART_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Start the ADC conversion (may be delayed for hardware triggers)
#[inline(always)]
pub fn start_conversion(self) -> &'a mut crate::W<REG> {
self.variant(ADSTARTW::StartConversion)
}
}
/**ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADSTPR {
///0: No stop command active
NotStopping = 0,
///1: ADC stopping conversion
Stopping = 1,
}
impl From<ADSTPR> for bool {
#[inline(always)]
fn from(variant: ADSTPR) -> Self {
variant as u8 != 0
}
}
///Field `ADSTP` reader - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
pub type ADSTP_R = crate::BitReader<ADSTPR>;
impl ADSTP_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADSTPR {
match self.bits {
false => ADSTPR::NotStopping,
true => ADSTPR::Stopping,
}
}
///No stop command active
#[inline(always)]
pub fn is_not_stopping(&self) -> bool {
*self == ADSTPR::NotStopping
}
///ADC stopping conversion
#[inline(always)]
pub fn is_stopping(&self) -> bool {
*self == ADSTPR::Stopping
}
}
/**ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADSTPW {
///1: Stop the active conversion
StopConversion = 1,
}
impl From<ADSTPW> for bool {
#[inline(always)]
fn from(variant: ADSTPW) -> Self {
variant as u8 != 0
}
}
///Field `ADSTP` writer - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
pub type ADSTP_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTPW>;
impl<'a, REG> ADSTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Stop the active conversion
#[inline(always)]
pub fn stop_conversion(self) -> &'a mut crate::W<REG> {
self.variant(ADSTPW::StopConversion)
}
}
/**ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADVREGEN {
///0: ADC voltage regulator disabled
Disabled = 0,
///1: ADC voltage regulator enabled
Enabled = 1,
}
impl From<ADVREGEN> for bool {
#[inline(always)]
fn from(variant: ADVREGEN) -> Self {
variant as u8 != 0
}
}
///Field `ADVREGEN` reader - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
pub type ADVREGEN_R = crate::BitReader<ADVREGEN>;
impl ADVREGEN_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADVREGEN {
match self.bits {
false => ADVREGEN::Disabled,
true => ADVREGEN::Enabled,
}
}
///ADC voltage regulator disabled
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADVREGEN::Disabled
}
///ADC voltage regulator enabled
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADVREGEN::Enabled
}
}
///Field `ADVREGEN` writer - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
pub type ADVREGEN_W<'a, REG> = crate::BitWriter<'a, REG, ADVREGEN>;
impl<'a, REG> ADVREGEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///ADC voltage regulator disabled
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ADVREGEN::Disabled)
}
///ADC voltage regulator enabled
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ADVREGEN::Enabled)
}
}
/**ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCALR {
///0: ADC calibration either not yet performed or completed
NotCalibrating = 0,
///1: ADC calibration in progress
Calibrating = 1,
}
impl From<ADCALR> for bool {
#[inline(always)]
fn from(variant: ADCALR) -> Self {
variant as u8 != 0
}
}
///Field `ADCAL` reader - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
pub type ADCAL_R = crate::BitReader<ADCALR>;
impl ADCAL_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> ADCALR {
match self.bits {
false => ADCALR::NotCalibrating,
true => ADCALR::Calibrating,
}
}
///ADC calibration either not yet performed or completed
#[inline(always)]
pub fn is_not_calibrating(&self) -> bool {
*self == ADCALR::NotCalibrating
}
///ADC calibration in progress
#[inline(always)]
pub fn is_calibrating(&self) -> bool {
*self == ADCALR::Calibrating
}
}
/**ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCALW {
///1: Start the ADC calibration sequence
StartCalibration = 1,
}
impl From<ADCALW> for bool {
#[inline(always)]
fn from(variant: ADCALW) -> Self {
variant as u8 != 0
}
}
///Field `ADCAL` writer - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
pub type ADCAL_W<'a, REG> = crate::BitWriter1S<'a, REG, ADCALW>;
impl<'a, REG> ADCAL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Start the ADC calibration sequence
#[inline(always)]
pub fn start_calibration(self) -> &'a mut crate::W<REG> {
self.variant(ADCALW::StartCalibration)
}
}
impl R {
///Bit 0 - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
#[inline(always)]
pub fn aden(&self) -> ADEN_R {
ADEN_R::new((self.bits & 1) != 0)
}
///Bit 1 - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
#[inline(always)]
pub fn addis(&self) -> ADDIS_R {
ADDIS_R::new(((self.bits >> 1) & 1) != 0)
}
///Bit 2 - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
#[inline(always)]
pub fn adstart(&self) -> ADSTART_R {
ADSTART_R::new(((self.bits >> 2) & 1) != 0)
}
///Bit 4 - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
#[inline(always)]
pub fn adstp(&self) -> ADSTP_R {
ADSTP_R::new(((self.bits >> 4) & 1) != 0)
}
///Bit 28 - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
#[inline(always)]
pub fn advregen(&self) -> ADVREGEN_R {
ADVREGEN_R::new(((self.bits >> 28) & 1) != 0)
}
///Bit 31 - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
#[inline(always)]
pub fn adcal(&self) -> ADCAL_R {
ADCAL_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CR")
.field("aden", &self.aden())
.field("addis", &self.addis())
.field("adstart", &self.adstart())
.field("adstp", &self.adstp())
.field("advregen", &self.advregen())
.field("adcal", &self.adcal())
.finish()
}
}
impl W {
///Bit 0 - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
#[inline(always)]
pub fn aden(&mut self) -> ADEN_W<CRrs> {
ADEN_W::new(self, 0)
}
///Bit 1 - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
#[inline(always)]
pub fn addis(&mut self) -> ADDIS_W<CRrs> {
ADDIS_W::new(self, 1)
}
///Bit 2 - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
#[inline(always)]
pub fn adstart(&mut self) -> ADSTART_W<CRrs> {
ADSTART_W::new(self, 2)
}
///Bit 4 - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
#[inline(always)]
pub fn adstp(&mut self) -> ADSTP_W<CRrs> {
ADSTP_W::new(self, 4)
}
///Bit 28 - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
#[inline(always)]
pub fn advregen(&mut self) -> ADVREGEN_W<CRrs> {
ADVREGEN_W::new(self, 28)
}
///Bit 31 - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
#[inline(always)]
pub fn adcal(&mut self) -> ADCAL_W<CRrs> {
ADCAL_W::new(self, 31)
}
}
/**ADC control register
You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G070.html#ADC:CR)*/
pub struct CRrs;
impl crate::RegisterSpec for CRrs {
type Ux = u32;
}
///`read()` method returns [`cr::R`](R) reader structure
impl crate::Readable for CRrs {}
///`write(|w| ..)` method takes [`cr::W`](W) writer structure
impl crate::Writable for CRrs {
type Safety = crate::Unsafe;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0017;
}
///`reset()` method sets CR to value 0
impl crate::Resettable for CRrs {}