#[doc = "Register `AHB3ENR` reader"]
pub struct R(crate::R<AHB3ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AHB3ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AHB3ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AHB3ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AHB3ENR` writer"]
pub struct W(crate::W<AHB3ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AHB3ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AHB3ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AHB3ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Flexible memory controller module clock enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FMCEN_A {
#[doc = "0: The selected clock is disabled"]
DISABLED = 0,
#[doc = "1: The selected clock is enabled"]
ENABLED = 1,
}
impl From<FMCEN_A> for bool {
#[inline(always)]
fn from(variant: FMCEN_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `FMCEN` reader - Flexible memory controller module clock enable"]
pub struct FMCEN_R(crate::FieldReader<bool, FMCEN_A>);
impl FMCEN_R {
pub(crate) fn new(bits: bool) -> Self {
FMCEN_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> FMCEN_A {
match self.bits {
false => FMCEN_A::DISABLED,
true => FMCEN_A::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
**self == FMCEN_A::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
**self == FMCEN_A::ENABLED
}
}
impl core::ops::Deref for FMCEN_R {
type Target = crate::FieldReader<bool, FMCEN_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FMCEN` writer - Flexible memory controller module clock enable"]
pub struct FMCEN_W<'a> {
w: &'a mut W,
}
impl<'a> FMCEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FMCEN_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(FMCEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(FMCEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Quad SPI memory controller clock enable"]
pub type QSPIEN_A = FMCEN_A;
#[doc = "Field `QSPIEN` reader - Quad SPI memory controller clock enable"]
pub type QSPIEN_R = FMCEN_R;
#[doc = "Field `QSPIEN` writer - Quad SPI memory controller clock enable"]
pub struct QSPIEN_W<'a> {
w: &'a mut W,
}
impl<'a> QSPIEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: QSPIEN_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(QSPIEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(QSPIEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
impl R {
#[doc = "Bit 0 - Flexible memory controller module clock enable"]
#[inline(always)]
pub fn fmcen(&self) -> FMCEN_R {
FMCEN_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Quad SPI memory controller clock enable"]
#[inline(always)]
pub fn qspien(&self) -> QSPIEN_R {
QSPIEN_R::new(((self.bits >> 1) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Flexible memory controller module clock enable"]
#[inline(always)]
pub fn fmcen(&mut self) -> FMCEN_W {
FMCEN_W { w: self }
}
#[doc = "Bit 1 - Quad SPI memory controller clock enable"]
#[inline(always)]
pub fn qspien(&mut self) -> QSPIEN_W {
QSPIEN_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "AHB3 peripheral clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahb3enr](index.html) module"]
pub struct AHB3ENR_SPEC;
impl crate::RegisterSpec for AHB3ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ahb3enr::R](R) reader structure"]
impl crate::Readable for AHB3ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ahb3enr::W](W) writer structure"]
impl crate::Writable for AHB3ENR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets AHB3ENR to value 0"]
impl crate::Resettable for AHB3ENR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}