rigless 0.2.2

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SWPMI` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `BRR` at offset `0x4`, resets to `0x0000_0001`, read-write.
    Brr = 1,
    /// `ISR` at offset `0xC`, resets to `0x0000_02C2`, read-only.
    Isr = 2,
    /// `ICR` at offset `0x10`, resets to `0x0000_0000`, write-only.
    Icr = 3,
    /// `IER` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Ier = 4,
    /// `RFL` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Rfl = 5,
    /// `TDR` at offset `0x1C`, resets to `0x0000_0000`, write-only.
    Tdr = 6,
    /// `RDR` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Rdr = 7,
    /// `OR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Or = 8,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 9] = [Self::Cr, Self::Brr, Self::Isr, Self::Icr, Self::Ier, Self::Rfl, Self::Tdr, Self::Rdr, Self::Or];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `RXDMA`, bit 0.
    pub const RXDMA: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TXDMA`, bit 1.
    pub const TXDMA: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `RXMODE`, bit 2.
    pub const RXMODE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TXMODE`, bit 3.
    pub const TXMODE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `LPBK`, bit 4.
    pub const LPBK: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `SWPACT`, bit 5.
    pub const SWPACT: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DEACT`, bit 10.
    pub const DEACT: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `SWPTEN`, bit 11.
    pub const SWPTEN: &FieldSpec = &super::REGISTERS[0].fields[7];
}

/// The fields of `BRR`.
pub mod brr {
    use super::FieldSpec;
    /// `BR`, bits 0..=7.
    pub const BR: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `RXBFF`, bit 0.
    pub const RXBFF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TXBEF`, bit 1.
    pub const TXBEF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `RXBERF`, bit 2.
    pub const RXBERF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `RXOVRF`, bit 3.
    pub const RXOVRF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `TXUNRF`, bit 4.
    pub const TXUNRF: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `RXNE`, bit 5.
    pub const RXNE: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `TXE`, bit 6.
    pub const TXE: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `TCF`, bit 7.
    pub const TCF: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `SRF`, bit 8.
    pub const SRF: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `SUSP`, bit 9.
    pub const SUSP: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `DEACTF`, bit 10.
    pub const DEACTF: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `RDYF`, bit 11.
    pub const RDYF: &FieldSpec = &super::REGISTERS[2].fields[11];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `CRXBFF`, bit 0.
    pub const CRXBFF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CTXBEF`, bit 1.
    pub const CTXBEF: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CRXBERF`, bit 2.
    pub const CRXBERF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `CRXOVRF`, bit 3.
    pub const CRXOVRF: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CTXUNRF`, bit 4.
    pub const CTXUNRF: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `CTCF`, bit 7.
    pub const CTCF: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `CSRF`, bit 8.
    pub const CSRF: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `CRDYF`, bit 11.
    pub const CRDYF: &FieldSpec = &super::REGISTERS[3].fields[7];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `RXBFIE`, bit 0.
    pub const RXBFIE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `TXBEIE`, bit 1.
    pub const TXBEIE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `RXBERIE`, bit 2.
    pub const RXBERIE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `RXOVRIE`, bit 3.
    pub const RXOVRIE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `TXUNRIE`, bit 4.
    pub const TXUNRIE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `RIE`, bit 5.
    pub const RIE: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `TIE`, bit 6.
    pub const TIE: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `TCIE`, bit 7.
    pub const TCIE: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `SRIE`, bit 8.
    pub const SRIE: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `RDYIE`, bit 11.
    pub const RDYIE: &FieldSpec = &super::REGISTERS[4].fields[9];
}

/// The fields of `RFL`.
pub mod rfl {
    use super::FieldSpec;
    /// `RFL`, bits 0..=4.
    pub const RFL: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `TDR`.
pub mod tdr {
    use super::FieldSpec;
    /// `TD`, bits 0..=31.
    pub const TD: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `RDR`.
pub mod rdr {
    use super::FieldSpec;
    /// `RD`, bits 0..=31.
    pub const RD: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `OR`.
pub mod or {
    use super::FieldSpec;
    /// `SWP_TBYP`, bit 0.
    pub const SWP_TBYP: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `SWP_CLASS`, bit 1.
    pub const SWP_CLASS: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 9] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXDMA", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDMA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXMODE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXMODE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPBK", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWPACT", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEACT", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWPTEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BRR", offset: 0x4, width: Width::W32, reset: 0x0000_0001, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0xC, width: Width::W32, reset: 0x0000_02C2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXBFF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXBEF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXBERF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVRF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNRF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNE", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXE", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCF", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SRF", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUSP", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEACTF", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDYF", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CRXBFF", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTXBEF", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRXBERF", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRXOVRF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTXUNRF", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCF", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSRF", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRDYF", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXBFIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXBEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXBERIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNRIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SRIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDYIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RFL", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFL", bit: 0, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TDR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TD", bit: 0, width: 32, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RDR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RD", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWP_TBYP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWP_CLASS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];