rigless 0.2.2

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SDMMC1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `POWER` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Power = 0,
    /// `CLKCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Clkcr = 1,
    /// `ARGR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Argr = 2,
    /// `CMDR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cmdr = 3,
    /// `RESPCMDR` at offset `0x10`, resets to `0xA3C5_DD01`, read-only.
    Respcmdr = 4,
    /// `RESP1R` at offset `0x14`, resets to `0x0000_0000`, read-only.
    Resp1r = 5,
    /// `RESP2R` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Resp2r = 6,
    /// `RESP3R` at offset `0x1C`, resets to `0x0000_0000`, read-only.
    Resp3r = 7,
    /// `RESP4R` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Resp4r = 8,
    /// `DTIMER` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Dtimer = 9,
    /// `DLENR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Dlenr = 10,
    /// `DCTRL` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Dctrl = 11,
    /// `DCNTR` at offset `0x30`, resets to `0x0000_0000`, read-only.
    Dcntr = 12,
    /// `STAR` at offset `0x34`, resets to `0x0000_0000`, read-only.
    Star = 13,
    /// `ICR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Icr = 14,
    /// `MASKR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Maskr = 15,
    /// `ACKTIMER` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Acktimer = 16,
    /// `IDMACTRLR` at offset `0x50`, resets to `0x0000_0000`, read-write.
    Idmactrlr = 17,
    /// `IDMABSIZER` at offset `0x54`, resets to `0x0000_0000`, read-write.
    Idmabsizer = 18,
    /// `IDMABASE0R` at offset `0x58`, resets to `0x0000_0000`, read-write.
    Idmabase0r = 19,
    /// `IDMABASE1R` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    Idmabase1r = 20,
    /// `FIFOR` at offset `0x80`, resets to `0x0000_0000`, read-write.
    Fifor = 21,
    /// `VER` at offset `0x3F4`, resets to `0x0000_0010`, read-only.
    Ver = 22,
    /// `ID` at offset `0x3F8`, resets to `0x0014_0022`, read-only.
    Id = 23,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 24] = [Self::Power, Self::Clkcr, Self::Argr, Self::Cmdr, Self::Respcmdr, Self::Resp1r, Self::Resp2r, Self::Resp3r, Self::Resp4r, Self::Dtimer, Self::Dlenr, Self::Dctrl, Self::Dcntr, Self::Star, Self::Icr, Self::Maskr, Self::Acktimer, Self::Idmactrlr, Self::Idmabsizer, Self::Idmabase0r, Self::Idmabase1r, Self::Fifor, Self::Ver, Self::Id];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `POWER`.
pub mod power {
    use super::FieldSpec;
    /// `PWRCTRL`, bits 0..=1.
    pub const PWRCTRL: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `VSWITCH`, bit 2.
    pub const VSWITCH: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `VSWITCHEN`, bit 3.
    pub const VSWITCHEN: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `DIRPOL`, bit 4.
    pub const DIRPOL: &FieldSpec = &super::REGISTERS[0].fields[3];
}

/// The fields of `CLKCR`.
pub mod clkcr {
    use super::FieldSpec;
    /// `CLKDIV`, bits 0..=9.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `PWRSAV`, bit 12.
    pub const PWRSAV: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `WIDBUS`, bits 14..=15.
    pub const WIDBUS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `NEGEDGE`, bit 16.
    pub const NEGEDGE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `HWFC_EN`, bit 17.
    pub const HWFC_EN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `DDR`, bit 18.
    pub const DDR: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `BUSSPEED`, bit 19.
    pub const BUSSPEED: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `SELCLKRX`, bits 20..=21.
    pub const SELCLKRX: &FieldSpec = &super::REGISTERS[1].fields[7];
}

/// The fields of `ARGR`.
pub mod argr {
    use super::FieldSpec;
    /// `CMDARG`, bits 0..=31.
    pub const CMDARG: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `CMDR`.
pub mod cmdr {
    use super::FieldSpec;
    /// `CMDINDEX`, bits 0..=5.
    pub const CMDINDEX: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CMDTRANS`, bit 6.
    pub const CMDTRANS: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CMDSTOP`, bit 7.
    pub const CMDSTOP: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `WAITRESP`, bits 8..=9.
    pub const WAITRESP: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `WAITINT`, bit 10.
    pub const WAITINT: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `WAITPEND`, bit 11.
    pub const WAITPEND: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `CPSMEN`, bit 12.
    pub const CPSMEN: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `DTHOLD`, bit 13.
    pub const DTHOLD: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `BOOTMODE`, bit 14.
    pub const BOOTMODE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `BOOTEN`, bit 15.
    pub const BOOTEN: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `CMDSUSPEND`, bit 16.
    pub const CMDSUSPEND: &FieldSpec = &super::REGISTERS[3].fields[10];
}

/// The fields of `RESPCMDR`.
pub mod respcmdr {
    use super::FieldSpec;
    /// `RESPCMD`, bits 0..=5.
    pub const RESPCMD: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `RESP1R`.
pub mod resp1r {
    use super::FieldSpec;
    /// `CARDSTATUS1`, bits 0..=31.
    pub const CARDSTATUS1: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `RESP2R`.
pub mod resp2r {
    use super::FieldSpec;
    /// `CARDSTATUS2`, bits 0..=31.
    pub const CARDSTATUS2: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `RESP3R`.
pub mod resp3r {
    use super::FieldSpec;
    /// `CARDSTATUS3`, bits 0..=31.
    pub const CARDSTATUS3: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `RESP4R`.
pub mod resp4r {
    use super::FieldSpec;
    /// `CARDSTATUS4`, bits 0..=31.
    pub const CARDSTATUS4: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `DTIMER`.
pub mod dtimer {
    use super::FieldSpec;
    /// `DATATIME`, bits 0..=31.
    pub const DATATIME: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `DLENR`.
pub mod dlenr {
    use super::FieldSpec;
    /// `DATALENGTH`, bits 0..=24.
    pub const DATALENGTH: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `DCTRL`.
pub mod dctrl {
    use super::FieldSpec;
    /// `DTEN`, bit 0.
    pub const DTEN: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `DTDIR`, bit 1.
    pub const DTDIR: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `DTMODE`, bits 2..=3.
    pub const DTMODE: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `DBLOCKSIZE`, bits 4..=7.
    pub const DBLOCKSIZE: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `RWSTART`, bit 8.
    pub const RWSTART: &FieldSpec = &super::REGISTERS[11].fields[4];
    /// `RWSTOP`, bit 9.
    pub const RWSTOP: &FieldSpec = &super::REGISTERS[11].fields[5];
    /// `RWMOD`, bit 10.
    pub const RWMOD: &FieldSpec = &super::REGISTERS[11].fields[6];
    /// `SDIOEN`, bit 11.
    pub const SDIOEN: &FieldSpec = &super::REGISTERS[11].fields[7];
    /// `BOOTACKEN`, bit 12.
    pub const BOOTACKEN: &FieldSpec = &super::REGISTERS[11].fields[8];
    /// `FIFORST`, bit 13.
    pub const FIFORST: &FieldSpec = &super::REGISTERS[11].fields[9];
}

/// The fields of `DCNTR`.
pub mod dcntr {
    use super::FieldSpec;
    /// `DATACOUNT`, bits 0..=24.
    pub const DATACOUNT: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `STAR`.
pub mod star {
    use super::FieldSpec;
    /// `CCRCFAIL`, bit 0.
    pub const CCRCFAIL: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `DCRCFAIL`, bit 1.
    pub const DCRCFAIL: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `CTIMEOUT`, bit 2.
    pub const CTIMEOUT: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `DTIMEOUT`, bit 3.
    pub const DTIMEOUT: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `TXUNDERR`, bit 4.
    pub const TXUNDERR: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `RXOVERR`, bit 5.
    pub const RXOVERR: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `CMDREND`, bit 6.
    pub const CMDREND: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `CMDSENT`, bit 7.
    pub const CMDSENT: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `DATAEND`, bit 8.
    pub const DATAEND: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `DHOLD`, bit 9.
    pub const DHOLD: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `DBCKEND`, bit 10.
    pub const DBCKEND: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `DABORT`, bit 11.
    pub const DABORT: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `DPSMACT`, bit 12.
    pub const DPSMACT: &FieldSpec = &super::REGISTERS[13].fields[12];
    /// `CPSMACT`, bit 13.
    pub const CPSMACT: &FieldSpec = &super::REGISTERS[13].fields[13];
    /// `TXFIFOHE`, bit 14.
    pub const TXFIFOHE: &FieldSpec = &super::REGISTERS[13].fields[14];
    /// `RXFIFOHF`, bit 15.
    pub const RXFIFOHF: &FieldSpec = &super::REGISTERS[13].fields[15];
    /// `TXFIFOF`, bit 16.
    pub const TXFIFOF: &FieldSpec = &super::REGISTERS[13].fields[16];
    /// `RXFIFOF`, bit 17.
    pub const RXFIFOF: &FieldSpec = &super::REGISTERS[13].fields[17];
    /// `TXFIFOE`, bit 18.
    pub const TXFIFOE: &FieldSpec = &super::REGISTERS[13].fields[18];
    /// `RXFIFOE`, bit 19.
    pub const RXFIFOE: &FieldSpec = &super::REGISTERS[13].fields[19];
    /// `BUSYD0`, bit 20.
    pub const BUSYD0: &FieldSpec = &super::REGISTERS[13].fields[20];
    /// `BUSYD0END`, bit 21.
    pub const BUSYD0END: &FieldSpec = &super::REGISTERS[13].fields[21];
    /// `SDIOIT`, bit 22.
    pub const SDIOIT: &FieldSpec = &super::REGISTERS[13].fields[22];
    /// `ACKFAIL`, bit 23.
    pub const ACKFAIL: &FieldSpec = &super::REGISTERS[13].fields[23];
    /// `ACKTIMEOUT`, bit 24.
    pub const ACKTIMEOUT: &FieldSpec = &super::REGISTERS[13].fields[24];
    /// `VSWEND`, bit 25.
    pub const VSWEND: &FieldSpec = &super::REGISTERS[13].fields[25];
    /// `CKSTOP`, bit 26.
    pub const CKSTOP: &FieldSpec = &super::REGISTERS[13].fields[26];
    /// `IDMATE`, bit 27.
    pub const IDMATE: &FieldSpec = &super::REGISTERS[13].fields[27];
    /// `IDMABTC`, bit 28.
    pub const IDMABTC: &FieldSpec = &super::REGISTERS[13].fields[28];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `CCRCFAILC`, bit 0.
    pub const CCRCFAILC: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `DCRCFAILC`, bit 1.
    pub const DCRCFAILC: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `CTIMEOUTC`, bit 2.
    pub const CTIMEOUTC: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `DTIMEOUTC`, bit 3.
    pub const DTIMEOUTC: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `TXUNDERRC`, bit 4.
    pub const TXUNDERRC: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `RXOVERRC`, bit 5.
    pub const RXOVERRC: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `CMDRENDC`, bit 6.
    pub const CMDRENDC: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `CMDSENTC`, bit 7.
    pub const CMDSENTC: &FieldSpec = &super::REGISTERS[14].fields[7];
    /// `DATAENDC`, bit 8.
    pub const DATAENDC: &FieldSpec = &super::REGISTERS[14].fields[8];
    /// `DHOLDC`, bit 9.
    pub const DHOLDC: &FieldSpec = &super::REGISTERS[14].fields[9];
    /// `DBCKENDC`, bit 10.
    pub const DBCKENDC: &FieldSpec = &super::REGISTERS[14].fields[10];
    /// `DABORTC`, bit 11.
    pub const DABORTC: &FieldSpec = &super::REGISTERS[14].fields[11];
    /// `BUSYD0ENDC`, bit 21.
    pub const BUSYD0ENDC: &FieldSpec = &super::REGISTERS[14].fields[12];
    /// `SDIOITC`, bit 22.
    pub const SDIOITC: &FieldSpec = &super::REGISTERS[14].fields[13];
    /// `ACKFAILC`, bit 23.
    pub const ACKFAILC: &FieldSpec = &super::REGISTERS[14].fields[14];
    /// `ACKTIMEOUTC`, bit 24.
    pub const ACKTIMEOUTC: &FieldSpec = &super::REGISTERS[14].fields[15];
    /// `VSWENDC`, bit 25.
    pub const VSWENDC: &FieldSpec = &super::REGISTERS[14].fields[16];
    /// `CKSTOPC`, bit 26.
    pub const CKSTOPC: &FieldSpec = &super::REGISTERS[14].fields[17];
    /// `IDMATEC`, bit 27.
    pub const IDMATEC: &FieldSpec = &super::REGISTERS[14].fields[18];
    /// `IDMABTCC`, bit 28.
    pub const IDMABTCC: &FieldSpec = &super::REGISTERS[14].fields[19];
}

/// The fields of `MASKR`.
pub mod maskr {
    use super::FieldSpec;
    /// `CCRCFAILIE`, bit 0.
    pub const CCRCFAILIE: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `DCRCFAILIE`, bit 1.
    pub const DCRCFAILIE: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `CTIMEOUTIE`, bit 2.
    pub const CTIMEOUTIE: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `DTIMEOUTIE`, bit 3.
    pub const DTIMEOUTIE: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `TXUNDERRIE`, bit 4.
    pub const TXUNDERRIE: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `RXOVERRIE`, bit 5.
    pub const RXOVERRIE: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `CMDRENDIE`, bit 6.
    pub const CMDRENDIE: &FieldSpec = &super::REGISTERS[15].fields[6];
    /// `CMDSENTIE`, bit 7.
    pub const CMDSENTIE: &FieldSpec = &super::REGISTERS[15].fields[7];
    /// `DATAENDIE`, bit 8.
    pub const DATAENDIE: &FieldSpec = &super::REGISTERS[15].fields[8];
    /// `DHOLDIE`, bit 9.
    pub const DHOLDIE: &FieldSpec = &super::REGISTERS[15].fields[9];
    /// `DBCKENDIE`, bit 10.
    pub const DBCKENDIE: &FieldSpec = &super::REGISTERS[15].fields[10];
    /// `DABORTIE`, bit 11.
    pub const DABORTIE: &FieldSpec = &super::REGISTERS[15].fields[11];
    /// `TXFIFOHEIE`, bit 14.
    pub const TXFIFOHEIE: &FieldSpec = &super::REGISTERS[15].fields[12];
    /// `RXFIFOHFIE`, bit 15.
    pub const RXFIFOHFIE: &FieldSpec = &super::REGISTERS[15].fields[13];
    /// `RXFIFOFIE`, bit 17.
    pub const RXFIFOFIE: &FieldSpec = &super::REGISTERS[15].fields[14];
    /// `TXFIFOEIE`, bit 18.
    pub const TXFIFOEIE: &FieldSpec = &super::REGISTERS[15].fields[15];
    /// `BUSYD0ENDIE`, bit 21.
    pub const BUSYD0ENDIE: &FieldSpec = &super::REGISTERS[15].fields[16];
    /// `SDIOITIE`, bit 22.
    pub const SDIOITIE: &FieldSpec = &super::REGISTERS[15].fields[17];
    /// `ACKFAILIE`, bit 23.
    pub const ACKFAILIE: &FieldSpec = &super::REGISTERS[15].fields[18];
    /// `ACKTIMEOUTIE`, bit 24.
    pub const ACKTIMEOUTIE: &FieldSpec = &super::REGISTERS[15].fields[19];
    /// `VSWENDIE`, bit 25.
    pub const VSWENDIE: &FieldSpec = &super::REGISTERS[15].fields[20];
    /// `CKSTOPIE`, bit 26.
    pub const CKSTOPIE: &FieldSpec = &super::REGISTERS[15].fields[21];
    /// `IDMABTCIE`, bit 28.
    pub const IDMABTCIE: &FieldSpec = &super::REGISTERS[15].fields[22];
}

/// The fields of `ACKTIMER`.
pub mod acktimer {
    use super::FieldSpec;
    /// `ACKTIME`, bits 0..=24.
    pub const ACKTIME: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `IDMACTRLR`.
pub mod idmactrlr {
    use super::FieldSpec;
    /// `IDMAEN`, bit 0.
    pub const IDMAEN: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `IDMABMODE`, bit 1.
    pub const IDMABMODE: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `IDMABACT`, bit 2.
    pub const IDMABACT: &FieldSpec = &super::REGISTERS[17].fields[2];
}

/// The fields of `IDMABSIZER`.
pub mod idmabsizer {
    use super::FieldSpec;
    /// `IDMABNDT`, bits 5..=12.
    pub const IDMABNDT: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `IDMABASE0R`.
pub mod idmabase0r {
    use super::FieldSpec;
    /// `IDMABASE0`, bits 0..=31.
    pub const IDMABASE0: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The fields of `IDMABASE1R`.
pub mod idmabase1r {
    use super::FieldSpec;
    /// `IDMABASE1`, bits 0..=31.
    pub const IDMABASE1: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The fields of `FIFOR`.
pub mod fifor {
    use super::FieldSpec;
    /// `FIFODATA`, bits 0..=31.
    pub const FIFODATA: &FieldSpec = &super::REGISTERS[21].fields[0];
}

/// The fields of `VER`.
pub mod ver {
    use super::FieldSpec;
    /// `MINREV`, bits 0..=3.
    pub const MINREV: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `MAJREV`, bits 4..=7.
    pub const MAJREV: &FieldSpec = &super::REGISTERS[22].fields[1];
}

/// The fields of `ID`.
pub mod id {
    use super::FieldSpec;
    /// `IP_ID`, bits 0..=31.
    pub const IP_ID: &FieldSpec = &super::REGISTERS[23].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 24] = [
    RegisterSpec { name: "POWER", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWRCTRL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSWITCH", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSWITCHEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIRPOL", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CLKCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLKDIV", bit: 0, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRSAV", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WIDBUS", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NEGEDGE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HWFC_EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DDR", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSSPEED", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SELCLKRX", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARGR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMDARG", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CMDR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMDINDEX", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDTRANS", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSTOP", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITRESP", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITINT", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPEND", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSMEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTHOLD", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOTMODE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOTEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSUSPEND", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESPCMDR", offset: 0x10, width: Width::W32, reset: 0xA3C5_DD01, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RESPCMD", bit: 0, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP1R", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS1", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP2R", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP3R", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS3", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP4R", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS4", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DTIMER", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATATIME", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DLENR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATALENGTH", bit: 0, width: 25, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCTRL", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTDIR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTMODE", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBLOCKSIZE", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWSTART", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWSTOP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOTACKEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FIFORST", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCNTR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATACOUNT", bit: 0, width: 25, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "STAR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAIL", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAIL", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUT", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUT", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERR", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERR", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDREND", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENT", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAEND", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DHOLD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKEND", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DABORT", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DPSMACT", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSMACT", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOHE", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOHF", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOF", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOE", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOE", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSYD0", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSYD0END", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOIT", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKFAIL", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKTIMEOUT", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSWEND", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTOP", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMATE", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMABTC", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAILC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAILC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUTC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUTC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERRC", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDRENDC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENTC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAENDC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DHOLDC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKENDC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DABORTC", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSYD0ENDC", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOITC", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKFAILC", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKTIMEOUTC", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSWENDC", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTOPC", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMATEC", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMABTCC", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MASKR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAILIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAILIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERRIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERRIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDRENDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENTIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAENDIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DHOLDIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKENDIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DABORTIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOHEIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOHFIE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOFIE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOEIE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSYD0ENDIE", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOITIE", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKFAILIE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACKTIMEOUTIE", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSWENDIE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTOPIE", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMABTCIE", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ACKTIMER", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ACKTIME", bit: 0, width: 25, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDMACTRLR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDMAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMABMODE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMABACT", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDMABSIZER", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDMABNDT", bit: 5, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDMABASE0R", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDMABASE0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDMABASE1R", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDMABASE1", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FIFOR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FIFODATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "VER", offset: 0x3F4, width: Width::W32, reset: 0x0000_0010, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MINREV", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MAJREV", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ID", offset: 0x3F8, width: Width::W32, reset: 0x0014_0022, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IP_ID", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];