rigless 0.2.2

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_DMA` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DMAMR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Dmamr = 0,
    /// `DMASBMR` at offset `0x4`, resets to `0x0101_0000`, read-write.
    Dmasbmr = 1,
    /// `DMAISR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Dmaisr = 2,
    /// `DMADSR` at offset `0xC`, resets to `0x0000_0000`, read-only.
    Dmadsr = 3,
    /// `DMACCR` at offset `0x100`, resets to `0x0000_0000`, read-write.
    Dmaccr = 4,
    /// `DMACTxCR` at offset `0x104`, resets to `0x0000_0000`, read-write.
    Dmactxcr = 5,
    /// `DMACRxCR` at offset `0x108`, resets to `0x0000_0000`, read-write.
    Dmacrxcr = 6,
    /// `DMACTxDLAR` at offset `0x114`, resets to `0x0000_0000`, read-write.
    Dmactxdlar = 7,
    /// `DMACRxDLAR` at offset `0x11C`, resets to `0x0000_0000`, read-write.
    Dmacrxdlar = 8,
    /// `DMACTxDTPR` at offset `0x120`, resets to `0x0000_0000`, read-write.
    Dmactxdtpr = 9,
    /// `DMACRxDTPR` at offset `0x128`, resets to `0x0000_0000`, read-write.
    Dmacrxdtpr = 10,
    /// `DMACTxRLR` at offset `0x12C`, resets to `0x0000_0000`, read-write.
    Dmactxrlr = 11,
    /// `DMACRxRLR` at offset `0x130`, resets to `0x0000_0000`, read-write.
    Dmacrxrlr = 12,
    /// `DMACIER` at offset `0x134`, resets to `0x0000_0000`, read-write.
    Dmacier = 13,
    /// `DMACRxIWTR` at offset `0x138`, resets to `0x0000_0000`, read-write.
    Dmacrxiwtr = 14,
    /// `DMACCATxDR` at offset `0x144`, resets to `0x0000_0000`, read-only.
    Dmaccatxdr = 15,
    /// `DMACCARxDR` at offset `0x14C`, resets to `0x0000_0000`, read-only.
    Dmaccarxdr = 16,
    /// `DMACCATxBR` at offset `0x154`, resets to `0x0000_0000`, read-only.
    Dmaccatxbr = 17,
    /// `DMACCARxBR` at offset `0x15C`, resets to `0x0000_0000`, read-only.
    Dmaccarxbr = 18,
    /// `DMACSR` at offset `0x160`, resets to `0x0000_0000`, read-write.
    Dmacsr = 19,
    /// `DMACMFCR` at offset `0x16C`, resets to `0x0000_0000`, read-only.
    Dmacmfcr = 20,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 21] = [Self::Dmamr, Self::Dmasbmr, Self::Dmaisr, Self::Dmadsr, Self::Dmaccr, Self::Dmactxcr, Self::Dmacrxcr, Self::Dmactxdlar, Self::Dmacrxdlar, Self::Dmactxdtpr, Self::Dmacrxdtpr, Self::Dmactxrlr, Self::Dmacrxrlr, Self::Dmacier, Self::Dmacrxiwtr, Self::Dmaccatxdr, Self::Dmaccarxdr, Self::Dmaccatxbr, Self::Dmaccarxbr, Self::Dmacsr, Self::Dmacmfcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DMAMR`.
pub mod dmamr {
    use super::FieldSpec;
    /// `SWR`, bit 0.
    pub const SWR: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `DA`, bit 1, read-only.
    pub const DA: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TXPR`, bit 11, read-only.
    pub const TXPR: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `PR`, bits 12..=14, read-only.
    pub const PR: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `INTM`, bit 16.
    pub const INTM: &FieldSpec = &super::REGISTERS[0].fields[4];
}

/// The fields of `DMASBMR`.
pub mod dmasbmr {
    use super::FieldSpec;
    /// `FB`, bit 0.
    pub const FB: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `AAL`, bit 12.
    pub const AAL: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `MB`, bit 14, read-only.
    pub const MB: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `RB`, bit 15, read-only.
    pub const RB: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The fields of `DMAISR`.
pub mod dmaisr {
    use super::FieldSpec;
    /// `DC0IS`, bit 0.
    pub const DC0IS: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `MTLIS`, bit 16.
    pub const MTLIS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `MACIS`, bit 17.
    pub const MACIS: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `DMADSR`.
pub mod dmadsr {
    use super::FieldSpec;
    /// `AXWHSTS`, bit 0.
    pub const AXWHSTS: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `RPS0`, bits 8..=11.
    pub const RPS0: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `TPS0`, bits 12..=15.
    pub const TPS0: &FieldSpec = &super::REGISTERS[3].fields[2];
}

/// The fields of `DMACCR`.
pub mod dmaccr {
    use super::FieldSpec;
    /// `MSS`, bits 0..=13.
    pub const MSS: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `PBLX8`, bit 16.
    pub const PBLX8: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `DSL`, bits 18..=20.
    pub const DSL: &FieldSpec = &super::REGISTERS[4].fields[2];
}

/// The fields of `DMACTxCR`.
pub mod dmactxcr {
    use super::FieldSpec;
    /// `ST`, bit 0.
    pub const ST: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `OSF`, bit 4.
    pub const OSF: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `TSE`, bit 12.
    pub const TSE: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `TXPBL`, bits 16..=21.
    pub const TXPBL: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `DMACRxCR`.
pub mod dmacrxcr {
    use super::FieldSpec;
    /// `SR`, bit 0.
    pub const SR: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `RBSZ`, bits 1..=14.
    pub const RBSZ: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `RXPBL`, bits 16..=21.
    pub const RXPBL: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `RPF`, bit 31.
    pub const RPF: &FieldSpec = &super::REGISTERS[6].fields[3];
}

/// The fields of `DMACTxDLAR`.
pub mod dmactxdlar {
    use super::FieldSpec;
    /// `TDESLA`, bits 2..=31.
    pub const TDESLA: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `DMACRxDLAR`.
pub mod dmacrxdlar {
    use super::FieldSpec;
    /// `RDESLA`, bits 2..=31.
    pub const RDESLA: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `DMACTxDTPR`.
pub mod dmactxdtpr {
    use super::FieldSpec;
    /// `TDT`, bits 2..=31.
    pub const TDT: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `DMACRxDTPR`.
pub mod dmacrxdtpr {
    use super::FieldSpec;
    /// `RDT`, bits 2..=31.
    pub const RDT: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `DMACTxRLR`.
pub mod dmactxrlr {
    use super::FieldSpec;
    /// `TDRL`, bits 0..=9.
    pub const TDRL: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `DMACRxRLR`.
pub mod dmacrxrlr {
    use super::FieldSpec;
    /// `RDRL`, bits 0..=9.
    pub const RDRL: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `DMACIER`.
pub mod dmacier {
    use super::FieldSpec;
    /// `TIE`, bit 0.
    pub const TIE: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `TXSE`, bit 1.
    pub const TXSE: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `TBUE`, bit 2.
    pub const TBUE: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `RIE`, bit 6.
    pub const RIE: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `RBUE`, bit 7.
    pub const RBUE: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `RSE`, bit 8.
    pub const RSE: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `RWTE`, bit 9.
    pub const RWTE: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `ETIE`, bit 10.
    pub const ETIE: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `ERIE`, bit 11.
    pub const ERIE: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `FBEE`, bit 12.
    pub const FBEE: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `CDEE`, bit 13.
    pub const CDEE: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `AIE`, bit 14.
    pub const AIE: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `NIE`, bit 15.
    pub const NIE: &FieldSpec = &super::REGISTERS[13].fields[12];
}

/// The fields of `DMACRxIWTR`.
pub mod dmacrxiwtr {
    use super::FieldSpec;
    /// `RWT`, bits 0..=7.
    pub const RWT: &FieldSpec = &super::REGISTERS[14].fields[0];
}

/// The fields of `DMACCATxDR`.
pub mod dmaccatxdr {
    use super::FieldSpec;
    /// `CURTDESAPTR`, bits 0..=31.
    pub const CURTDESAPTR: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `DMACCARxDR`.
pub mod dmaccarxdr {
    use super::FieldSpec;
    /// `CURRDESAPTR`, bits 0..=31.
    pub const CURRDESAPTR: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `DMACCATxBR`.
pub mod dmaccatxbr {
    use super::FieldSpec;
    /// `CURTBUFAPTR`, bits 0..=31.
    pub const CURTBUFAPTR: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The fields of `DMACCARxBR`.
pub mod dmaccarxbr {
    use super::FieldSpec;
    /// `CURRBUFAPTR`, bits 0..=31.
    pub const CURRBUFAPTR: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `DMACSR`.
pub mod dmacsr {
    use super::FieldSpec;
    /// `TI`, bit 0.
    pub const TI: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `TPS`, bit 1.
    pub const TPS: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `TBU`, bit 2.
    pub const TBU: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `RI`, bit 6.
    pub const RI: &FieldSpec = &super::REGISTERS[19].fields[3];
    /// `RBU`, bit 7.
    pub const RBU: &FieldSpec = &super::REGISTERS[19].fields[4];
    /// `RPS`, bit 8.
    pub const RPS: &FieldSpec = &super::REGISTERS[19].fields[5];
    /// `RWT`, bit 9.
    pub const RWT: &FieldSpec = &super::REGISTERS[19].fields[6];
    /// `ET`, bit 10.
    pub const ET: &FieldSpec = &super::REGISTERS[19].fields[7];
    /// `ER`, bit 11.
    pub const ER: &FieldSpec = &super::REGISTERS[19].fields[8];
    /// `FBE`, bit 12.
    pub const FBE: &FieldSpec = &super::REGISTERS[19].fields[9];
    /// `CDE`, bit 13.
    pub const CDE: &FieldSpec = &super::REGISTERS[19].fields[10];
    /// `AIS`, bit 14.
    pub const AIS: &FieldSpec = &super::REGISTERS[19].fields[11];
    /// `NIS`, bit 15.
    pub const NIS: &FieldSpec = &super::REGISTERS[19].fields[12];
    /// `TEB`, bits 16..=18, read-only.
    pub const TEB: &FieldSpec = &super::REGISTERS[19].fields[13];
    /// `REB`, bits 19..=21, read-only.
    pub const REB: &FieldSpec = &super::REGISTERS[19].fields[14];
}

/// The fields of `DMACMFCR`.
pub mod dmacmfcr {
    use super::FieldSpec;
    /// `MFC`, bits 0..=10.
    pub const MFC: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `MFCO`, bit 15.
    pub const MFCO: &FieldSpec = &super::REGISTERS[20].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 21] = [
    RegisterSpec { name: "DMAMR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DA", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXPR", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR", bit: 12, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INTM", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMASBMR", offset: 0x4, width: Width::W32, reset: 0x0101_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AAL", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MB", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RB", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAISR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DC0IS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTLIS", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MACIS", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMADSR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AXWHSTS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPS0", bit: 8, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPS0", bit: 12, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACCR", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MSS", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBLX8", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DSL", bit: 18, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACTxCR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXPBL", bit: 16, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACRxCR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBSZ", bit: 1, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXPBL", bit: 16, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPF", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACTxDLAR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TDESLA", bit: 2, width: 30, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACRxDLAR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDESLA", bit: 2, width: 30, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACTxDTPR", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TDT", bit: 2, width: 30, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACRxDTPR", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDT", bit: 2, width: 30, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACTxRLR", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TDRL", bit: 0, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACRxRLR", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDRL", bit: 0, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACIER", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBUE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBUE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWTE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FBEE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDEE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NIE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACRxIWTR", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RWT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACCATxDR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CURTDESAPTR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACCARxDR", offset: 0x14C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CURRDESAPTR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACCATxBR", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CURTBUFAPTR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACCARxBR", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CURRBUFAPTR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACSR", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TI", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBU", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RI", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBU", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPS", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWT", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ET", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ER", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FBE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AIS", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NIS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEB", bit: 16, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REB", bit: 19, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACMFCR", offset: 0x16C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MFC", bit: 0, width: 11, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MFCO", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];