rigless 0.2.2

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `GPIOA` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MODER` at offset `0x0`, resets to `0xABFF_FFFF`, read-write.
    Moder = 0,
    /// `OTYPER` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Otyper = 1,
    /// `OSPEEDR` at offset `0x8`, resets to `0x0C00_0000`, read-write.
    Ospeedr = 2,
    /// `PUPDR` at offset `0xC`, resets to `0x1210_0000`, read-write.
    Pupdr = 3,
    /// `IDR` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Idr = 4,
    /// `ODR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Odr = 5,
    /// `BSRR` at offset `0x18`, resets to `0x0000_0000`, write-only.
    Bsrr = 6,
    /// `LCKR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Lckr = 7,
    /// `AFRL` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Afrl = 8,
    /// `AFRH` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Afrh = 9,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 10] = [Self::Moder, Self::Otyper, Self::Ospeedr, Self::Pupdr, Self::Idr, Self::Odr, Self::Bsrr, Self::Lckr, Self::Afrl, Self::Afrh];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MODER`.
pub mod moder {
    use super::FieldSpec;
    /// `MODE0`, bits 0..=1.
    pub const MODE0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MODE1`, bits 2..=3.
    pub const MODE1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `MODE2`, bits 4..=5.
    pub const MODE2: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `MODE3`, bits 6..=7.
    pub const MODE3: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `MODE4`, bits 8..=9.
    pub const MODE4: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `MODE5`, bits 10..=11.
    pub const MODE5: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `MODE6`, bits 12..=13.
    pub const MODE6: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `MODE7`, bits 14..=15.
    pub const MODE7: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `MODE8`, bits 16..=17.
    pub const MODE8: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MODE9`, bits 18..=19.
    pub const MODE9: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `MODE10`, bits 20..=21.
    pub const MODE10: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `MODE11`, bits 22..=23.
    pub const MODE11: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `MODE12`, bits 24..=25.
    pub const MODE12: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `MODE13`, bits 26..=27.
    pub const MODE13: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `MODE14`, bits 28..=29.
    pub const MODE14: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `MODE15`, bits 30..=31.
    pub const MODE15: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `OTYPER`.
pub mod otyper {
    use super::FieldSpec;
    /// `OT0`, bit 0.
    pub const OT0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `OT1`, bit 1.
    pub const OT1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `OT2`, bit 2.
    pub const OT2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `OT3`, bit 3.
    pub const OT3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `OT4`, bit 4.
    pub const OT4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `OT5`, bit 5.
    pub const OT5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `OT6`, bit 6.
    pub const OT6: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `OT7`, bit 7.
    pub const OT7: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `OT8`, bit 8.
    pub const OT8: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `OT9`, bit 9.
    pub const OT9: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `OT10`, bit 10.
    pub const OT10: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `OT11`, bit 11.
    pub const OT11: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `OT12`, bit 12.
    pub const OT12: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `OT13`, bit 13.
    pub const OT13: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `OT14`, bit 14.
    pub const OT14: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `OT15`, bit 15.
    pub const OT15: &FieldSpec = &super::REGISTERS[1].fields[15];
}

/// The fields of `OSPEEDR`.
pub mod ospeedr {
    use super::FieldSpec;
    /// `OSPEED0`, bits 0..=1.
    pub const OSPEED0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `OSPEED1`, bits 2..=3.
    pub const OSPEED1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `OSPEED2`, bits 4..=5.
    pub const OSPEED2: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `OSPEED3`, bits 6..=7.
    pub const OSPEED3: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `OSPEED4`, bits 8..=9.
    pub const OSPEED4: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `OSPEED5`, bits 10..=11.
    pub const OSPEED5: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `OSPEED6`, bits 12..=13.
    pub const OSPEED6: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `OSPEED7`, bits 14..=15.
    pub const OSPEED7: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `OSPEED8`, bits 16..=17.
    pub const OSPEED8: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `OSPEED9`, bits 18..=19.
    pub const OSPEED9: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `OSPEED10`, bits 20..=21.
    pub const OSPEED10: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `OSPEED11`, bits 22..=23.
    pub const OSPEED11: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `OSPEED12`, bits 24..=25.
    pub const OSPEED12: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `OSPEED13`, bits 26..=27.
    pub const OSPEED13: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `OSPEED14`, bits 28..=29.
    pub const OSPEED14: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `OSPEED15`, bits 30..=31.
    pub const OSPEED15: &FieldSpec = &super::REGISTERS[2].fields[15];
}

/// The fields of `PUPDR`.
pub mod pupdr {
    use super::FieldSpec;
    /// `PUPD0`, bits 0..=1.
    pub const PUPD0: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `PUPD1`, bits 2..=3.
    pub const PUPD1: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `PUPD2`, bits 4..=5.
    pub const PUPD2: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `PUPD3`, bits 6..=7.
    pub const PUPD3: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `PUPD4`, bits 8..=9.
    pub const PUPD4: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `PUPD5`, bits 10..=11.
    pub const PUPD5: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `PUPD6`, bits 12..=13.
    pub const PUPD6: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `PUPD7`, bits 14..=15.
    pub const PUPD7: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `PUPD8`, bits 16..=17.
    pub const PUPD8: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `PUPD9`, bits 18..=19.
    pub const PUPD9: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `PUPD10`, bits 20..=21.
    pub const PUPD10: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `PUPD11`, bits 22..=23.
    pub const PUPD11: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `PUPD12`, bits 24..=25.
    pub const PUPD12: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `PUPD13`, bits 26..=27.
    pub const PUPD13: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `PUPD14`, bits 28..=29.
    pub const PUPD14: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `PUPD15`, bits 30..=31.
    pub const PUPD15: &FieldSpec = &super::REGISTERS[3].fields[15];
}

/// The fields of `IDR`.
pub mod idr {
    use super::FieldSpec;
    /// `ID0`, bit 0.
    pub const ID0: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `ID1`, bit 1.
    pub const ID1: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `ID2`, bit 2.
    pub const ID2: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `ID3`, bit 3.
    pub const ID3: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `ID4`, bit 4.
    pub const ID4: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `ID5`, bit 5.
    pub const ID5: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `ID6`, bit 6.
    pub const ID6: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `ID7`, bit 7.
    pub const ID7: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `ID8`, bit 8.
    pub const ID8: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `ID9`, bit 9.
    pub const ID9: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `ID10`, bit 10.
    pub const ID10: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `ID11`, bit 11.
    pub const ID11: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `ID12`, bit 12.
    pub const ID12: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `ID13`, bit 13.
    pub const ID13: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `ID14`, bit 14.
    pub const ID14: &FieldSpec = &super::REGISTERS[4].fields[14];
    /// `ID15`, bit 15.
    pub const ID15: &FieldSpec = &super::REGISTERS[4].fields[15];
}

/// The fields of `ODR`.
pub mod odr {
    use super::FieldSpec;
    /// `OD0`, bit 0.
    pub const OD0: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `OD1`, bit 1.
    pub const OD1: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `OD2`, bit 2.
    pub const OD2: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `OD3`, bit 3.
    pub const OD3: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `OD4`, bit 4.
    pub const OD4: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `OD5`, bit 5.
    pub const OD5: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `OD6`, bit 6.
    pub const OD6: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `OD7`, bit 7.
    pub const OD7: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `OD8`, bit 8.
    pub const OD8: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `OD9`, bit 9.
    pub const OD9: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `OD10`, bit 10.
    pub const OD10: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `OD11`, bit 11.
    pub const OD11: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `OD12`, bit 12.
    pub const OD12: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `OD13`, bit 13.
    pub const OD13: &FieldSpec = &super::REGISTERS[5].fields[13];
    /// `OD14`, bit 14.
    pub const OD14: &FieldSpec = &super::REGISTERS[5].fields[14];
    /// `OD15`, bit 15.
    pub const OD15: &FieldSpec = &super::REGISTERS[5].fields[15];
}

/// The fields of `BSRR`.
pub mod bsrr {
    use super::FieldSpec;
    /// `BS0`, bit 0.
    pub const BS0: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `BS1`, bit 1.
    pub const BS1: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `BS2`, bit 2.
    pub const BS2: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `BS3`, bit 3.
    pub const BS3: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `BS4`, bit 4.
    pub const BS4: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `BS5`, bit 5.
    pub const BS5: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `BS6`, bit 6.
    pub const BS6: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `BS7`, bit 7.
    pub const BS7: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `BS8`, bit 8.
    pub const BS8: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `BS9`, bit 9.
    pub const BS9: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `BS10`, bit 10.
    pub const BS10: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `BS11`, bit 11.
    pub const BS11: &FieldSpec = &super::REGISTERS[6].fields[11];
    /// `BS12`, bit 12.
    pub const BS12: &FieldSpec = &super::REGISTERS[6].fields[12];
    /// `BS13`, bit 13.
    pub const BS13: &FieldSpec = &super::REGISTERS[6].fields[13];
    /// `BS14`, bit 14.
    pub const BS14: &FieldSpec = &super::REGISTERS[6].fields[14];
    /// `BS15`, bit 15.
    pub const BS15: &FieldSpec = &super::REGISTERS[6].fields[15];
    /// `BR0`, bit 16.
    pub const BR0: &FieldSpec = &super::REGISTERS[6].fields[16];
    /// `BR1`, bit 17.
    pub const BR1: &FieldSpec = &super::REGISTERS[6].fields[17];
    /// `BR2`, bit 18.
    pub const BR2: &FieldSpec = &super::REGISTERS[6].fields[18];
    /// `BR3`, bit 19.
    pub const BR3: &FieldSpec = &super::REGISTERS[6].fields[19];
    /// `BR4`, bit 20.
    pub const BR4: &FieldSpec = &super::REGISTERS[6].fields[20];
    /// `BR5`, bit 21.
    pub const BR5: &FieldSpec = &super::REGISTERS[6].fields[21];
    /// `BR6`, bit 22.
    pub const BR6: &FieldSpec = &super::REGISTERS[6].fields[22];
    /// `BR7`, bit 23.
    pub const BR7: &FieldSpec = &super::REGISTERS[6].fields[23];
    /// `BR8`, bit 24.
    pub const BR8: &FieldSpec = &super::REGISTERS[6].fields[24];
    /// `BR9`, bit 25.
    pub const BR9: &FieldSpec = &super::REGISTERS[6].fields[25];
    /// `BR10`, bit 26.
    pub const BR10: &FieldSpec = &super::REGISTERS[6].fields[26];
    /// `BR11`, bit 27.
    pub const BR11: &FieldSpec = &super::REGISTERS[6].fields[27];
    /// `BR12`, bit 28.
    pub const BR12: &FieldSpec = &super::REGISTERS[6].fields[28];
    /// `BR13`, bit 29.
    pub const BR13: &FieldSpec = &super::REGISTERS[6].fields[29];
    /// `BR14`, bit 30.
    pub const BR14: &FieldSpec = &super::REGISTERS[6].fields[30];
    /// `BR15`, bit 31.
    pub const BR15: &FieldSpec = &super::REGISTERS[6].fields[31];
}

/// The fields of `LCKR`.
pub mod lckr {
    use super::FieldSpec;
    /// `LCK0`, bit 0.
    pub const LCK0: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `LCK1`, bit 1.
    pub const LCK1: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `LCK2`, bit 2.
    pub const LCK2: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `LCK3`, bit 3.
    pub const LCK3: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `LCK4`, bit 4.
    pub const LCK4: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `LCK5`, bit 5.
    pub const LCK5: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `LCK6`, bit 6.
    pub const LCK6: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `LCK7`, bit 7.
    pub const LCK7: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `LCK8`, bit 8.
    pub const LCK8: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `LCK9`, bit 9.
    pub const LCK9: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `LCK10`, bit 10.
    pub const LCK10: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `LCK11`, bit 11.
    pub const LCK11: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `LCK12`, bit 12.
    pub const LCK12: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `LCK13`, bit 13.
    pub const LCK13: &FieldSpec = &super::REGISTERS[7].fields[13];
    /// `LCK14`, bit 14.
    pub const LCK14: &FieldSpec = &super::REGISTERS[7].fields[14];
    /// `LCK15`, bit 15.
    pub const LCK15: &FieldSpec = &super::REGISTERS[7].fields[15];
    /// `LCKK`, bit 16.
    pub const LCKK: &FieldSpec = &super::REGISTERS[7].fields[16];
}

/// The fields of `AFRL`.
pub mod afrl {
    use super::FieldSpec;
    /// `AFSEL0`, bits 0..=3.
    pub const AFSEL0: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `AFSEL1`, bits 4..=7.
    pub const AFSEL1: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `AFSEL2`, bits 8..=11.
    pub const AFSEL2: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `AFSEL3`, bits 12..=15.
    pub const AFSEL3: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `AFSEL4`, bits 16..=19.
    pub const AFSEL4: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `AFSEL5`, bits 20..=23.
    pub const AFSEL5: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `AFSEL6`, bits 24..=27.
    pub const AFSEL6: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `AFSEL7`, bits 28..=31.
    pub const AFSEL7: &FieldSpec = &super::REGISTERS[8].fields[7];
}

/// The fields of `AFRH`.
pub mod afrh {
    use super::FieldSpec;
    /// `AFSEL8`, bits 0..=3.
    pub const AFSEL8: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `AFSEL9`, bits 4..=7.
    pub const AFSEL9: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `AFSEL10`, bits 8..=11.
    pub const AFSEL10: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `AFSEL11`, bits 12..=15.
    pub const AFSEL11: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `AFSEL12`, bits 16..=19.
    pub const AFSEL12: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `AFSEL13`, bits 20..=23.
    pub const AFSEL13: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `AFSEL14`, bits 24..=27.
    pub const AFSEL14: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `AFSEL15`, bits 28..=31.
    pub const AFSEL15: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 10] = [
    RegisterSpec { name: "MODER", offset: 0x0, width: Width::W32, reset: 0xABFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OTYPER", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OT0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OSPEEDR", offset: 0x8, width: Width::W32, reset: 0x0C00_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OSPEED0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEED15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PUPDR", offset: 0xC, width: Width::W32, reset: 0x1210_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PUPD0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPD15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ID0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ID15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ODR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OD0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OD15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BSRR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BS0", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS1", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS2", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS3", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS4", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS5", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS6", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS7", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS8", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS9", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS10", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS11", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS12", bit: 12, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS13", bit: 13, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS14", bit: 14, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS15", bit: 15, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR0", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR1", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR2", bit: 18, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR3", bit: 19, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR4", bit: 20, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR5", bit: 21, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR6", bit: 22, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR7", bit: 23, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR8", bit: 24, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR9", bit: 25, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR10", bit: 26, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR11", bit: 27, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR12", bit: 28, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR13", bit: 29, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR14", bit: 30, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR15", bit: 31, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LCKR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LCK0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCKK", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AFRL", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AFSEL0", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL1", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL2", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL3", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL4", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL5", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL6", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL7", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AFRH", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AFSEL8", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL9", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL10", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL11", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL12", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL13", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL14", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSEL15", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];