// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `HASH` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
Cr = 0,
/// `DIN` at offset `0x4`, resets to `0x0000_0000`, read-write.
Din = 1,
/// `STR` at offset `0x8`, resets to `0x0000_0000`, read-write.
Str = 2,
/// `HR0` at offset `0xC`, resets to `0x0000_0000`, read-only.
Hr0 = 3,
/// `HR1` at offset `0x10`, resets to `0x0000_0000`, read-only.
Hr1 = 4,
/// `HR2` at offset `0x14`, resets to `0x0000_0000`, read-only.
Hr2 = 5,
/// `HR3` at offset `0x18`, resets to `0x0000_0000`, read-only.
Hr3 = 6,
/// `HR4` at offset `0x1C`, resets to `0x0000_0000`, read-only.
Hr4 = 7,
/// `IMR` at offset `0x20`, resets to `0x0000_0000`, read-write.
Imr = 8,
/// `SR` at offset `0x24`, resets to `0x0000_0001`, read-write.
Sr = 9,
/// `CSR0` at offset `0xF8`, resets to `0x0000_0000`, read-write.
Csr0 = 10,
/// `CSR1` at offset `0xFC`, resets to `0x0000_0000`, read-write.
Csr1 = 11,
/// `CSR2` at offset `0x100`, resets to `0x0000_0000`, read-write.
Csr2 = 12,
/// `CSR3` at offset `0x104`, resets to `0x0000_0000`, read-write.
Csr3 = 13,
/// `CSR4` at offset `0x108`, resets to `0x0000_0000`, read-write.
Csr4 = 14,
/// `CSR5` at offset `0x10C`, resets to `0x0000_0000`, read-write.
Csr5 = 15,
/// `CSR6` at offset `0x110`, resets to `0x0000_0000`, read-write.
Csr6 = 16,
/// `CSR7` at offset `0x114`, resets to `0x0000_0000`, read-write.
Csr7 = 17,
/// `CSR8` at offset `0x118`, resets to `0x0000_0000`, read-write.
Csr8 = 18,
/// `CSR9` at offset `0x11C`, resets to `0x0000_0000`, read-write.
Csr9 = 19,
/// `CSR10` at offset `0x120`, resets to `0x0000_0000`, read-write.
Csr10 = 20,
/// `CSR11` at offset `0x124`, resets to `0x0000_0000`, read-write.
Csr11 = 21,
/// `CSR12` at offset `0x128`, resets to `0x0000_0000`, read-write.
Csr12 = 22,
/// `CSR13` at offset `0x12C`, resets to `0x0000_0000`, read-write.
Csr13 = 23,
/// `CSR14` at offset `0x130`, resets to `0x0000_0000`, read-write.
Csr14 = 24,
/// `CSR15` at offset `0x134`, resets to `0x0000_0000`, read-write.
Csr15 = 25,
/// `CSR16` at offset `0x138`, resets to `0x0000_0000`, read-write.
Csr16 = 26,
/// `CSR17` at offset `0x13C`, resets to `0x0000_0000`, read-write.
Csr17 = 27,
/// `CSR18` at offset `0x140`, resets to `0x0000_0000`, read-write.
Csr18 = 28,
/// `CSR19` at offset `0x144`, resets to `0x0000_0000`, read-write.
Csr19 = 29,
/// `CSR20` at offset `0x148`, resets to `0x0000_0000`, read-write.
Csr20 = 30,
/// `CSR21` at offset `0x14C`, resets to `0x0000_0000`, read-write.
Csr21 = 31,
/// `CSR22` at offset `0x150`, resets to `0x0000_0000`, read-write.
Csr22 = 32,
/// `CSR23` at offset `0x154`, resets to `0x0000_0000`, read-write.
Csr23 = 33,
/// `CSR24` at offset `0x158`, resets to `0x0000_0000`, read-write.
Csr24 = 34,
/// `CSR25` at offset `0x15C`, resets to `0x0000_0000`, read-write.
Csr25 = 35,
/// `CSR26` at offset `0x160`, resets to `0x0000_0000`, read-write.
Csr26 = 36,
/// `CSR27` at offset `0x164`, resets to `0x0000_0000`, read-write.
Csr27 = 37,
/// `CSR28` at offset `0x168`, resets to `0x0000_0000`, read-write.
Csr28 = 38,
/// `CSR29` at offset `0x16C`, resets to `0x0000_0000`, read-write.
Csr29 = 39,
/// `CSR30` at offset `0x170`, resets to `0x0000_0000`, read-write.
Csr30 = 40,
/// `CSR31` at offset `0x174`, resets to `0x0000_0000`, read-write.
Csr31 = 41,
/// `CSR32` at offset `0x178`, resets to `0x0000_0000`, read-write.
Csr32 = 42,
/// `CSR33` at offset `0x17C`, resets to `0x0000_0000`, read-write.
Csr33 = 43,
/// `CSR34` at offset `0x180`, resets to `0x0000_0000`, read-write.
Csr34 = 44,
/// `CSR35` at offset `0x184`, resets to `0x0000_0000`, read-write.
Csr35 = 45,
/// `CSR36` at offset `0x188`, resets to `0x0000_0000`, read-write.
Csr36 = 46,
/// `CSR37` at offset `0x18C`, resets to `0x0000_0000`, read-write.
Csr37 = 47,
/// `CSR38` at offset `0x190`, resets to `0x0000_0000`, read-write.
Csr38 = 48,
/// `CSR39` at offset `0x194`, resets to `0x0000_0000`, read-write.
Csr39 = 49,
/// `CSR40` at offset `0x198`, resets to `0x0000_0000`, read-write.
Csr40 = 50,
/// `CSR41` at offset `0x19C`, resets to `0x0000_0000`, read-write.
Csr41 = 51,
/// `CSR42` at offset `0x1A0`, resets to `0x0000_0000`, read-write.
Csr42 = 52,
/// `CSR43` at offset `0x1A4`, resets to `0x0000_0000`, read-write.
Csr43 = 53,
/// `CSR44` at offset `0x1A8`, resets to `0x0000_0000`, read-write.
Csr44 = 54,
/// `CSR45` at offset `0x1AC`, resets to `0x0000_0000`, read-write.
Csr45 = 55,
/// `CSR46` at offset `0x1B0`, resets to `0x0000_0000`, read-write.
Csr46 = 56,
/// `CSR47` at offset `0x1B4`, resets to `0x0000_0000`, read-write.
Csr47 = 57,
/// `CSR48` at offset `0x1B8`, resets to `0x0000_0000`, read-write.
Csr48 = 58,
/// `CSR49` at offset `0x1BC`, resets to `0x0000_0000`, read-write.
Csr49 = 59,
/// `CSR50` at offset `0x1C0`, resets to `0x0000_0000`, read-write.
Csr50 = 60,
/// `CSR51` at offset `0x1C4`, resets to `0x0000_0000`, read-write.
Csr51 = 61,
/// `CSR52` at offset `0x1C8`, resets to `0x0000_0000`, read-write.
Csr52 = 62,
/// `CSR53` at offset `0x1CC`, resets to `0x0000_0000`, read-write.
Csr53 = 63,
/// `HASH_HR0` at offset `0x310`, resets to `0x0000_0000`, read-only.
HashHr0 = 64,
/// `HASH_HR1` at offset `0x314`, resets to `0x0000_0000`, read-only.
HashHr1 = 65,
/// `HASH_HR2` at offset `0x318`, resets to `0x0000_0000`, read-only.
HashHr2 = 66,
/// `HASH_HR3` at offset `0x31C`, resets to `0x0000_0000`, read-only.
HashHr3 = 67,
/// `HASH_HR4` at offset `0x320`, resets to `0x0000_0000`, read-only.
HashHr4 = 68,
/// `HASH_HR5` at offset `0x324`, resets to `0x0000_0000`, read-only.
HashHr5 = 69,
/// `HASH_HR6` at offset `0x328`, resets to `0x0000_0000`, read-only.
HashHr6 = 70,
/// `HASH_HR7` at offset `0x32C`, resets to `0x0000_0000`, read-only.
HashHr7 = 71,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 72] = [Self::Cr, Self::Din, Self::Str, Self::Hr0, Self::Hr1, Self::Hr2, Self::Hr3, Self::Hr4, Self::Imr, Self::Sr, Self::Csr0, Self::Csr1, Self::Csr2, Self::Csr3, Self::Csr4, Self::Csr5, Self::Csr6, Self::Csr7, Self::Csr8, Self::Csr9, Self::Csr10, Self::Csr11, Self::Csr12, Self::Csr13, Self::Csr14, Self::Csr15, Self::Csr16, Self::Csr17, Self::Csr18, Self::Csr19, Self::Csr20, Self::Csr21, Self::Csr22, Self::Csr23, Self::Csr24, Self::Csr25, Self::Csr26, Self::Csr27, Self::Csr28, Self::Csr29, Self::Csr30, Self::Csr31, Self::Csr32, Self::Csr33, Self::Csr34, Self::Csr35, Self::Csr36, Self::Csr37, Self::Csr38, Self::Csr39, Self::Csr40, Self::Csr41, Self::Csr42, Self::Csr43, Self::Csr44, Self::Csr45, Self::Csr46, Self::Csr47, Self::Csr48, Self::Csr49, Self::Csr50, Self::Csr51, Self::Csr52, Self::Csr53, Self::HashHr0, Self::HashHr1, Self::HashHr2, Self::HashHr3, Self::HashHr4, Self::HashHr5, Self::HashHr6, Self::HashHr7];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `CR`.
pub mod cr {
use super::FieldSpec;
/// `INIT`, bit 2, write-only.
pub const INIT: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `DMAE`, bit 3.
pub const DMAE: &FieldSpec = &super::REGISTERS[0].fields[1];
/// `DATATYPE`, bits 4..=5.
pub const DATATYPE: &FieldSpec = &super::REGISTERS[0].fields[2];
/// `MODE`, bit 6.
pub const MODE: &FieldSpec = &super::REGISTERS[0].fields[3];
/// `ALGO0`, bit 7.
pub const ALGO0: &FieldSpec = &super::REGISTERS[0].fields[4];
/// `NBW`, bits 8..=11, read-only.
pub const NBW: &FieldSpec = &super::REGISTERS[0].fields[5];
/// `DINNE`, bit 12, read-only.
pub const DINNE: &FieldSpec = &super::REGISTERS[0].fields[6];
/// `MDMAT`, bit 13.
pub const MDMAT: &FieldSpec = &super::REGISTERS[0].fields[7];
/// `LKEY`, bit 16.
pub const LKEY: &FieldSpec = &super::REGISTERS[0].fields[8];
/// `ALGO1`, bit 18.
pub const ALGO1: &FieldSpec = &super::REGISTERS[0].fields[9];
}
/// The fields of `DIN`.
pub mod din {
use super::FieldSpec;
/// `DATAIN`, bits 0..=31.
pub const DATAIN: &FieldSpec = &super::REGISTERS[1].fields[0];
}
/// The fields of `STR`.
pub mod str {
use super::FieldSpec;
/// `NBLW`, bits 0..=4.
pub const NBLW: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `DCAL`, bit 8, write-only.
pub const DCAL: &FieldSpec = &super::REGISTERS[2].fields[1];
}
/// The fields of `HR0`.
pub mod hr0 {
use super::FieldSpec;
/// `H0`, bits 0..=31.
pub const H0: &FieldSpec = &super::REGISTERS[3].fields[0];
}
/// The fields of `HR1`.
pub mod hr1 {
use super::FieldSpec;
/// `H1`, bits 0..=31.
pub const H1: &FieldSpec = &super::REGISTERS[4].fields[0];
}
/// The fields of `HR2`.
pub mod hr2 {
use super::FieldSpec;
/// `H2`, bits 0..=31.
pub const H2: &FieldSpec = &super::REGISTERS[5].fields[0];
}
/// The fields of `HR3`.
pub mod hr3 {
use super::FieldSpec;
/// `H3`, bits 0..=31.
pub const H3: &FieldSpec = &super::REGISTERS[6].fields[0];
}
/// The fields of `HR4`.
pub mod hr4 {
use super::FieldSpec;
/// `H4`, bits 0..=31.
pub const H4: &FieldSpec = &super::REGISTERS[7].fields[0];
}
/// The fields of `IMR`.
pub mod imr {
use super::FieldSpec;
/// `DINIE`, bit 0.
pub const DINIE: &FieldSpec = &super::REGISTERS[8].fields[0];
/// `DCIE`, bit 1.
pub const DCIE: &FieldSpec = &super::REGISTERS[8].fields[1];
}
/// The fields of `SR`.
pub mod sr {
use super::FieldSpec;
/// `DINIS`, bit 0.
pub const DINIS: &FieldSpec = &super::REGISTERS[9].fields[0];
/// `DCIS`, bit 1.
pub const DCIS: &FieldSpec = &super::REGISTERS[9].fields[1];
/// `DMAS`, bit 2, read-only.
pub const DMAS: &FieldSpec = &super::REGISTERS[9].fields[2];
/// `BUSY`, bit 3, read-only.
pub const BUSY: &FieldSpec = &super::REGISTERS[9].fields[3];
}
/// The fields of `CSR0`.
pub mod csr0 {
use super::FieldSpec;
/// `CSR0`, bits 0..=31.
pub const CSR0: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `CSR1`.
pub mod csr1 {
use super::FieldSpec;
/// `CSR1`, bits 0..=31.
pub const CSR1: &FieldSpec = &super::REGISTERS[11].fields[0];
}
/// The fields of `CSR2`.
pub mod csr2 {
use super::FieldSpec;
/// `CSR2`, bits 0..=31.
pub const CSR2: &FieldSpec = &super::REGISTERS[12].fields[0];
}
/// The fields of `CSR3`.
pub mod csr3 {
use super::FieldSpec;
/// `CSR3`, bits 0..=31.
pub const CSR3: &FieldSpec = &super::REGISTERS[13].fields[0];
}
/// The fields of `CSR4`.
pub mod csr4 {
use super::FieldSpec;
/// `CSR4`, bits 0..=31.
pub const CSR4: &FieldSpec = &super::REGISTERS[14].fields[0];
}
/// The fields of `CSR5`.
pub mod csr5 {
use super::FieldSpec;
/// `CSR5`, bits 0..=31.
pub const CSR5: &FieldSpec = &super::REGISTERS[15].fields[0];
}
/// The fields of `CSR6`.
pub mod csr6 {
use super::FieldSpec;
/// `CSR6`, bits 0..=31.
pub const CSR6: &FieldSpec = &super::REGISTERS[16].fields[0];
}
/// The fields of `CSR7`.
pub mod csr7 {
use super::FieldSpec;
/// `CSR7`, bits 0..=31.
pub const CSR7: &FieldSpec = &super::REGISTERS[17].fields[0];
}
/// The fields of `CSR8`.
pub mod csr8 {
use super::FieldSpec;
/// `CSR8`, bits 0..=31.
pub const CSR8: &FieldSpec = &super::REGISTERS[18].fields[0];
}
/// The fields of `CSR9`.
pub mod csr9 {
use super::FieldSpec;
/// `CSR9`, bits 0..=31.
pub const CSR9: &FieldSpec = &super::REGISTERS[19].fields[0];
}
/// The fields of `CSR10`.
pub mod csr10 {
use super::FieldSpec;
/// `CSR10`, bits 0..=31.
pub const CSR10: &FieldSpec = &super::REGISTERS[20].fields[0];
}
/// The fields of `CSR11`.
pub mod csr11 {
use super::FieldSpec;
/// `CSR11`, bits 0..=31.
pub const CSR11: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `CSR12`.
pub mod csr12 {
use super::FieldSpec;
/// `CSR12`, bits 0..=31.
pub const CSR12: &FieldSpec = &super::REGISTERS[22].fields[0];
}
/// The fields of `CSR13`.
pub mod csr13 {
use super::FieldSpec;
/// `CSR13`, bits 0..=31.
pub const CSR13: &FieldSpec = &super::REGISTERS[23].fields[0];
}
/// The fields of `CSR14`.
pub mod csr14 {
use super::FieldSpec;
/// `CSR14`, bits 0..=31.
pub const CSR14: &FieldSpec = &super::REGISTERS[24].fields[0];
}
/// The fields of `CSR15`.
pub mod csr15 {
use super::FieldSpec;
/// `CSR15`, bits 0..=31.
pub const CSR15: &FieldSpec = &super::REGISTERS[25].fields[0];
}
/// The fields of `CSR16`.
pub mod csr16 {
use super::FieldSpec;
/// `CSR16`, bits 0..=31.
pub const CSR16: &FieldSpec = &super::REGISTERS[26].fields[0];
}
/// The fields of `CSR17`.
pub mod csr17 {
use super::FieldSpec;
/// `CSR17`, bits 0..=31.
pub const CSR17: &FieldSpec = &super::REGISTERS[27].fields[0];
}
/// The fields of `CSR18`.
pub mod csr18 {
use super::FieldSpec;
/// `CSR18`, bits 0..=31.
pub const CSR18: &FieldSpec = &super::REGISTERS[28].fields[0];
}
/// The fields of `CSR19`.
pub mod csr19 {
use super::FieldSpec;
/// `CSR19`, bits 0..=31.
pub const CSR19: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `CSR20`.
pub mod csr20 {
use super::FieldSpec;
/// `CSR20`, bits 0..=31.
pub const CSR20: &FieldSpec = &super::REGISTERS[30].fields[0];
}
/// The fields of `CSR21`.
pub mod csr21 {
use super::FieldSpec;
/// `CSR21`, bits 0..=31.
pub const CSR21: &FieldSpec = &super::REGISTERS[31].fields[0];
}
/// The fields of `CSR22`.
pub mod csr22 {
use super::FieldSpec;
/// `CSR22`, bits 0..=31.
pub const CSR22: &FieldSpec = &super::REGISTERS[32].fields[0];
}
/// The fields of `CSR23`.
pub mod csr23 {
use super::FieldSpec;
/// `CSR23`, bits 0..=31.
pub const CSR23: &FieldSpec = &super::REGISTERS[33].fields[0];
}
/// The fields of `CSR24`.
pub mod csr24 {
use super::FieldSpec;
/// `CSR24`, bits 0..=31.
pub const CSR24: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `CSR25`.
pub mod csr25 {
use super::FieldSpec;
/// `CSR25`, bits 0..=31.
pub const CSR25: &FieldSpec = &super::REGISTERS[35].fields[0];
}
/// The fields of `CSR26`.
pub mod csr26 {
use super::FieldSpec;
/// `CSR26`, bits 0..=31.
pub const CSR26: &FieldSpec = &super::REGISTERS[36].fields[0];
}
/// The fields of `CSR27`.
pub mod csr27 {
use super::FieldSpec;
/// `CSR27`, bits 0..=31.
pub const CSR27: &FieldSpec = &super::REGISTERS[37].fields[0];
}
/// The fields of `CSR28`.
pub mod csr28 {
use super::FieldSpec;
/// `CSR28`, bits 0..=31.
pub const CSR28: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The fields of `CSR29`.
pub mod csr29 {
use super::FieldSpec;
/// `CSR29`, bits 0..=31.
pub const CSR29: &FieldSpec = &super::REGISTERS[39].fields[0];
}
/// The fields of `CSR30`.
pub mod csr30 {
use super::FieldSpec;
/// `CSR30`, bits 0..=31.
pub const CSR30: &FieldSpec = &super::REGISTERS[40].fields[0];
}
/// The fields of `CSR31`.
pub mod csr31 {
use super::FieldSpec;
/// `CSR31`, bits 0..=31.
pub const CSR31: &FieldSpec = &super::REGISTERS[41].fields[0];
}
/// The fields of `CSR32`.
pub mod csr32 {
use super::FieldSpec;
/// `CSR32`, bits 0..=31.
pub const CSR32: &FieldSpec = &super::REGISTERS[42].fields[0];
}
/// The fields of `CSR33`.
pub mod csr33 {
use super::FieldSpec;
/// `CSR33`, bits 0..=31.
pub const CSR33: &FieldSpec = &super::REGISTERS[43].fields[0];
}
/// The fields of `CSR34`.
pub mod csr34 {
use super::FieldSpec;
/// `CSR34`, bits 0..=31.
pub const CSR34: &FieldSpec = &super::REGISTERS[44].fields[0];
}
/// The fields of `CSR35`.
pub mod csr35 {
use super::FieldSpec;
/// `CSR35`, bits 0..=31.
pub const CSR35: &FieldSpec = &super::REGISTERS[45].fields[0];
}
/// The fields of `CSR36`.
pub mod csr36 {
use super::FieldSpec;
/// `CSR36`, bits 0..=31.
pub const CSR36: &FieldSpec = &super::REGISTERS[46].fields[0];
}
/// The fields of `CSR37`.
pub mod csr37 {
use super::FieldSpec;
/// `CSR37`, bits 0..=31.
pub const CSR37: &FieldSpec = &super::REGISTERS[47].fields[0];
}
/// The fields of `CSR38`.
pub mod csr38 {
use super::FieldSpec;
/// `CSR38`, bits 0..=31.
pub const CSR38: &FieldSpec = &super::REGISTERS[48].fields[0];
}
/// The fields of `CSR39`.
pub mod csr39 {
use super::FieldSpec;
/// `CSR39`, bits 0..=31.
pub const CSR39: &FieldSpec = &super::REGISTERS[49].fields[0];
}
/// The fields of `CSR40`.
pub mod csr40 {
use super::FieldSpec;
/// `CSR40`, bits 0..=31.
pub const CSR40: &FieldSpec = &super::REGISTERS[50].fields[0];
}
/// The fields of `CSR41`.
pub mod csr41 {
use super::FieldSpec;
/// `CSR41`, bits 0..=31.
pub const CSR41: &FieldSpec = &super::REGISTERS[51].fields[0];
}
/// The fields of `CSR42`.
pub mod csr42 {
use super::FieldSpec;
/// `CSR42`, bits 0..=31.
pub const CSR42: &FieldSpec = &super::REGISTERS[52].fields[0];
}
/// The fields of `CSR43`.
pub mod csr43 {
use super::FieldSpec;
/// `CSR43`, bits 0..=31.
pub const CSR43: &FieldSpec = &super::REGISTERS[53].fields[0];
}
/// The fields of `CSR44`.
pub mod csr44 {
use super::FieldSpec;
/// `CSR44`, bits 0..=31.
pub const CSR44: &FieldSpec = &super::REGISTERS[54].fields[0];
}
/// The fields of `CSR45`.
pub mod csr45 {
use super::FieldSpec;
/// `CSR45`, bits 0..=31.
pub const CSR45: &FieldSpec = &super::REGISTERS[55].fields[0];
}
/// The fields of `CSR46`.
pub mod csr46 {
use super::FieldSpec;
/// `CSR46`, bits 0..=31.
pub const CSR46: &FieldSpec = &super::REGISTERS[56].fields[0];
}
/// The fields of `CSR47`.
pub mod csr47 {
use super::FieldSpec;
/// `CSR47`, bits 0..=31.
pub const CSR47: &FieldSpec = &super::REGISTERS[57].fields[0];
}
/// The fields of `CSR48`.
pub mod csr48 {
use super::FieldSpec;
/// `CSR48`, bits 0..=31.
pub const CSR48: &FieldSpec = &super::REGISTERS[58].fields[0];
}
/// The fields of `CSR49`.
pub mod csr49 {
use super::FieldSpec;
/// `CSR49`, bits 0..=31.
pub const CSR49: &FieldSpec = &super::REGISTERS[59].fields[0];
}
/// The fields of `CSR50`.
pub mod csr50 {
use super::FieldSpec;
/// `CSR50`, bits 0..=31.
pub const CSR50: &FieldSpec = &super::REGISTERS[60].fields[0];
}
/// The fields of `CSR51`.
pub mod csr51 {
use super::FieldSpec;
/// `CSR51`, bits 0..=31.
pub const CSR51: &FieldSpec = &super::REGISTERS[61].fields[0];
}
/// The fields of `CSR52`.
pub mod csr52 {
use super::FieldSpec;
/// `CSR52`, bits 0..=31.
pub const CSR52: &FieldSpec = &super::REGISTERS[62].fields[0];
}
/// The fields of `CSR53`.
pub mod csr53 {
use super::FieldSpec;
/// `CSR53`, bits 0..=31.
pub const CSR53: &FieldSpec = &super::REGISTERS[63].fields[0];
}
/// The fields of `HASH_HR0`.
pub mod hash_hr0 {
use super::FieldSpec;
/// `H0`, bits 0..=31.
pub const H0: &FieldSpec = &super::REGISTERS[64].fields[0];
}
/// The fields of `HASH_HR1`.
pub mod hash_hr1 {
use super::FieldSpec;
/// `H1`, bits 0..=31.
pub const H1: &FieldSpec = &super::REGISTERS[65].fields[0];
}
/// The fields of `HASH_HR2`.
pub mod hash_hr2 {
use super::FieldSpec;
/// `H2`, bits 0..=31.
pub const H2: &FieldSpec = &super::REGISTERS[66].fields[0];
}
/// The fields of `HASH_HR3`.
pub mod hash_hr3 {
use super::FieldSpec;
/// `H3`, bits 0..=31.
pub const H3: &FieldSpec = &super::REGISTERS[67].fields[0];
}
/// The fields of `HASH_HR4`.
pub mod hash_hr4 {
use super::FieldSpec;
/// `H4`, bits 0..=31.
pub const H4: &FieldSpec = &super::REGISTERS[68].fields[0];
}
/// The fields of `HASH_HR5`.
pub mod hash_hr5 {
use super::FieldSpec;
/// `H5`, bits 0..=31.
pub const H5: &FieldSpec = &super::REGISTERS[69].fields[0];
}
/// The fields of `HASH_HR6`.
pub mod hash_hr6 {
use super::FieldSpec;
/// `H6`, bits 0..=31.
pub const H6: &FieldSpec = &super::REGISTERS[70].fields[0];
}
/// The fields of `HASH_HR7`.
pub mod hash_hr7 {
use super::FieldSpec;
/// `H7`, bits 0..=31.
pub const H7: &FieldSpec = &super::REGISTERS[71].fields[0];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 72] = [
RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "INIT", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMAE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DATATYPE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MODE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALGO0", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NBW", bit: 8, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINNE", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDMAT", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LKEY", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALGO1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DIN", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DATAIN", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "STR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "NBLW", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCAL", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HR0", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H0", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HR1", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H1", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HR2", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HR3", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H3", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HR4", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H4", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "IMR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DINIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SR", offset: 0x24, width: Width::W32, reset: 0x0000_0001, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DINIS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMAS", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BUSY", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR0", offset: 0xF8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR1", offset: 0xFC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR1", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR2", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR2", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR3", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR3", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR4", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR4", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR5", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR5", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR6", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR6", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR7", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR7", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR8", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR8", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR9", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR9", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR10", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR10", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR11", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR11", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR12", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR12", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR13", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR13", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR14", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR14", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR15", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR15", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR16", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR16", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR17", offset: 0x13C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR17", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR18", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR18", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR19", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR19", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR20", offset: 0x148, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR20", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR21", offset: 0x14C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR21", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR22", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR22", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR23", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR23", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR24", offset: 0x158, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR24", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR25", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR25", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR26", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR26", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR27", offset: 0x164, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR27", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR28", offset: 0x168, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR28", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR29", offset: 0x16C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR29", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR30", offset: 0x170, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR30", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR31", offset: 0x174, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR31", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR32", offset: 0x178, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR32", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR33", offset: 0x17C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR33", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR34", offset: 0x180, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR34", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR35", offset: 0x184, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR35", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR36", offset: 0x188, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR36", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR37", offset: 0x18C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR37", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR38", offset: 0x190, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR38", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR39", offset: 0x194, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR39", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR40", offset: 0x198, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR40", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR41", offset: 0x19C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR41", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR42", offset: 0x1A0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR42", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR43", offset: 0x1A4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR43", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR44", offset: 0x1A8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR44", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR45", offset: 0x1AC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR45", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR46", offset: 0x1B0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR46", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR47", offset: 0x1B4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR47", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR48", offset: 0x1B8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR48", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR49", offset: 0x1BC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR49", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR50", offset: 0x1C0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR50", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR51", offset: 0x1C4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR51", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR52", offset: 0x1C8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR52", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR53", offset: 0x1CC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CSR53", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR0", offset: 0x310, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H0", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR1", offset: 0x314, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H1", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR2", offset: 0x318, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR3", offset: 0x31C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H3", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR4", offset: 0x320, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H4", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR5", offset: 0x324, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H5", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR6", offset: 0x328, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H6", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HASH_HR7", offset: 0x32C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "H7", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
];