Module lpc54606_pac::syscon

LPC5460x System configuration (SYSCON)

Modules

adcclkdiv	ADC clock divider
adcclksel	ADC clock source select
ahbclkctrl0	AHB Clock control n
ahbclkctrl1	AHB Clock control n
ahbclkctrl2	AHB Clock control n
ahbclkctrlclr	Clear bits in AHBCLKCTRLn
ahbclkctrlset	Set bits in AHBCLKCTRLn
ahbclkdiv	AHB clock divider
ahbmatprio	AHB multilayer matrix priority control
armtraceclkdiv	ARM Trace clock divider
asyncapbctrl	Asynchronous APB Control
audpllclksel	Audio PLL clock source select
audpllctrl	Audio PLL control
audpllfrac	Audio PLL fractional divider control
audpllmdec	Audio PLL M divider
audpllndec	Audio PLL N divider
audpllpdec	Audio PLL P divider
audpllstat	Audio PLL status
autocgor	Auto Clock-Gate Override Register
bodctrl	Brown-Out Detect control
can0clkdiv	MCAN0 clock divider
can1clkdiv	MCAN1 clock divider
clkoutdiv	CLKOUT clock divider
clkoutsela	CLKOUT clock source select A
device_id0	Part ID register
device_id1	Boot ROM and die revision register
dmicclkdiv	DMIC clock divider
dmicclksel	Digital microphone (DMIC) subsystem clock select
emcclkdiv	EMC clock divider
emcdlycal	EMC delay chain calibration control
emcdlyctrl	EMC clock delay control
emcsysctrl	EMC system control
ethphysel	Ethernet PHY Selection
ethsbdctrl	Ethernet SBD flow control
fclksel	Flexcomm 0 clock source select
flashcfg	Flash wait states configuration
freqmectrl	Frequency measure register
frgclksel	Fractional Rate Generator clock source select
frgctrl	Fractional rate divider
froctrl	FRO oscillator control
frohfclkdiv	FROHF clock divider
hwwake	Configures special cases of hardware wake-up
jtagidcode	JTAG ID code register
lcdclkdiv	LCD clock divider
lcdclksel	LCD clock source select
mainclksela	Main clock source select A
mainclkselb	Main clock source select B
mclkclksel	MCLK clock source select
mclkdiv	I2S MCLK clock divider
mclkio	MCLK input/output control
nmisrc	NMI Source Select
pdruncfg0	Power configuration register
pdruncfg1	Power configuration register
pdruncfgclr0	Power configuration clear register
pdruncfgclr1	Power configuration clear register
pdruncfgset0	Power configuration set register
pdruncfgset1	Power configuration set register
pdsleepcfg0	Sleep configuration register
pdsleepcfg1	Sleep configuration register
pioporcap	POR captured value of port n
piorescap	Reset captured value of port n
presetctrl0	Peripheral reset control n
presetctrl1	Peripheral reset control n
presetctrl2	Peripheral reset control n
presetctrlclr	Clear bits in PRESETCTRLn
presetctrlset	Set bits in PRESETCTRLn
rtcoscctrl	RTC oscillator 32 kHz output control
sc0clkdiv	Smartcard0 clock divider
sc1clkdiv	Smartcard1 clock divider
sctclkdiv	SCT/PWM clock divider
sctclksel	SCTimer/PWM clock source select
sdioclkctrl	SDIO CCLKIN phase and delay control
sdioclkdiv	SDIO clock divider
sdioclksel	SDIO clock source select
spificlkdiv	SPIFI clock divider
spificlksel	SPIFI clock source select
starter0	Start logic 0 wake-up enable register
starter1	Start logic 0 wake-up enable register
starterclr	Clear bits in STARTER0
starterset	Set bits in STARTER
sysoscctrl	System oscillator control
syspllclksel	PLL clock source select
syspllctrl	System PLL control
syspllmdec	System PLL M divider
syspllndec	PLL N divider
syspllpdec	PLL P divider
syspllstat	PLL status
sysrststat	System reset status register
systckcal	System tick counter calibration
systickclkdiv	SYSTICK clock divider
usb0clksel	USB0 clock source select
usb0clkdiv	USB0 clock divider
usb0clkctrl	USB0 clock control
usb0clkstat	USB0 clock status
usb1clksel	USB1 clock source select
usb1clkdiv	USB1 clock divider
usb1clkctrl	USB1 clock control
usb1clkstat	USB1 clock status
usbpllctrl	USB PLL control
usbpllstat	USB PLL status
wdtoscctrl	Watchdog oscillator control

Structs

RegisterBlock

Register block

Type Definitions

ADCCLKDIV	ADC clock divider
ADCCLKSEL	ADC clock source select
AHBCLKCTRL0	AHB Clock control n
AHBCLKCTRL1	AHB Clock control n
AHBCLKCTRL2	AHB Clock control n
AHBCLKCTRLCLR	Clear bits in AHBCLKCTRLn
AHBCLKCTRLSET	Set bits in AHBCLKCTRLn
AHBCLKDIV	AHB clock divider
AHBMATPRIO	AHB multilayer matrix priority control
ARMTRACECLKDIV	ARM Trace clock divider
ASYNCAPBCTRL	Asynchronous APB Control
AUDPLLCLKSEL	Audio PLL clock source select
AUDPLLCTRL	Audio PLL control
AUDPLLFRAC	Audio PLL fractional divider control
AUDPLLMDEC	Audio PLL M divider
AUDPLLNDEC	Audio PLL N divider
AUDPLLPDEC	Audio PLL P divider
AUDPLLSTAT	Audio PLL status
AUTOCGOR	Auto Clock-Gate Override Register
BODCTRL	Brown-Out Detect control
CAN0CLKDIV	MCAN0 clock divider
CAN1CLKDIV	MCAN1 clock divider
CLKOUTDIV	CLKOUT clock divider
CLKOUTSELA	CLKOUT clock source select A
DEVICE_ID0	Part ID register
DEVICE_ID1	Boot ROM and die revision register
DMICCLKDIV	DMIC clock divider
DMICCLKSEL	Digital microphone (DMIC) subsystem clock select
EMCCLKDIV	EMC clock divider
EMCDLYCAL	EMC delay chain calibration control
EMCDLYCTRL	EMC clock delay control
EMCSYSCTRL	EMC system control
ETHPHYSEL	Ethernet PHY Selection
ETHSBDCTRL	Ethernet SBD flow control
FCLKSEL	Flexcomm 0 clock source select
FLASHCFG	Flash wait states configuration
FREQMECTRL	Frequency measure register
FRGCLKSEL	Fractional Rate Generator clock source select
FRGCTRL	Fractional rate divider
FROCTRL	FRO oscillator control
FROHFCLKDIV	FROHF clock divider
HWWAKE	Configures special cases of hardware wake-up
JTAGIDCODE	JTAG ID code register
LCDCLKDIV	LCD clock divider
LCDCLKSEL	LCD clock source select
MAINCLKSELA	Main clock source select A
MAINCLKSELB	Main clock source select B
MCLKCLKSEL	MCLK clock source select
MCLKDIV	I2S MCLK clock divider
MCLKIO	MCLK input/output control
NMISRC	NMI Source Select
PDRUNCFG0	Power configuration register
PDRUNCFG1	Power configuration register
PDRUNCFGCLR0	Power configuration clear register
PDRUNCFGCLR1	Power configuration clear register
PDRUNCFGSET0	Power configuration set register
PDRUNCFGSET1	Power configuration set register
PDSLEEPCFG0	Sleep configuration register
PDSLEEPCFG1	Sleep configuration register
PIOPORCAP	POR captured value of port n
PIORESCAP	Reset captured value of port n
PRESETCTRL0	Peripheral reset control n
PRESETCTRL1	Peripheral reset control n
PRESETCTRL2	Peripheral reset control n
PRESETCTRLCLR	Clear bits in PRESETCTRLn
PRESETCTRLSET	Set bits in PRESETCTRLn
RTCOSCCTRL	RTC oscillator 32 kHz output control
SC0CLKDIV	Smartcard0 clock divider
SC1CLKDIV	Smartcard1 clock divider
SCTCLKDIV	SCT/PWM clock divider
SCTCLKSEL	SCTimer/PWM clock source select
SDIOCLKCTRL	SDIO CCLKIN phase and delay control
SDIOCLKDIV	SDIO clock divider
SDIOCLKSEL	SDIO clock source select
SPIFICLKDIV	SPIFI clock divider
SPIFICLKSEL	SPIFI clock source select
STARTER0	Start logic 0 wake-up enable register
STARTER1	Start logic 0 wake-up enable register
STARTERCLR	Clear bits in STARTER0
STARTERSET	Set bits in STARTER
SYSOSCCTRL	System oscillator control
SYSPLLCLKSEL	PLL clock source select
SYSPLLCTRL	System PLL control
SYSPLLMDEC	System PLL M divider
SYSPLLNDEC	PLL N divider
SYSPLLPDEC	PLL P divider
SYSPLLSTAT	PLL status
SYSRSTSTAT	System reset status register
SYSTCKCAL	System tick counter calibration
SYSTICKCLKDIV	SYSTICK clock divider
USB0CLKSEL	USB0 clock source select
USB0CLKDIV	USB0 clock divider
USB0CLKCTRL	USB0 clock control
USB0CLKSTAT	USB0 clock status
USB1CLKSEL	USB1 clock source select
USB1CLKDIV	USB1 clock divider
USB1CLKCTRL	USB1 clock control
USB1CLKSTAT	USB1 clock status
USBPLLCTRL	USB PLL control
USBPLLSTAT	USB PLL status
WDTOSCCTRL	Watchdog oscillator control