[−][src]Type Definition lpc54606_pac::syscon::MCLKDIV
type MCLKDIV = Reg<u32, _MCLKDIV>;
I2S MCLK clock divider
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about available fields see mclkdiv module
Trait Implementations
impl Readable for MCLKDIV
[src]
read()
method returns mclkdiv::R reader structure
impl ResetValue for MCLKDIV
[src]
Register MCLKDIV reset()
's with value 0x4000_0000
impl Writable for MCLKDIV
[src]
write(|w| ..)
method takes mclkdiv::W writer structure