hc32f460_driver_sys 0.1.0

/* automatically generated by rust-bindgen 0.72.1 */

pub const __MPU_PRESENT: u32 = 1;
pub const __VTOR_PRESENT: u32 = 1;
pub const __NVIC_PRIO_BITS: u32 = 4;
pub const __Vendor_SysTickConfig: u32 = 0;
pub const __FPU_PRESENT: u32 = 1;
pub const EFM_BASE: u32 = 0;
pub const SRAM_BASE: u32 = 536838144;
pub const QSPI_BASE: u32 = 2550136832;
pub const CM_ADC1_BASE: u32 = 1074003968;
pub const CM_ADC2_BASE: u32 = 1074004992;
pub const CM_AES_BASE: u32 = 1073774592;
pub const CM_AOS_BASE: u32 = 1073809408;
pub const CM_CAN_BASE: u32 = 1074201600;
pub const CM_CMP1_BASE: u32 = 1074044928;
pub const CM_CMP2_BASE: u32 = 1074044944;
pub const CM_CMP3_BASE: u32 = 1074044960;
pub const CM_CMP_COMMON_BASE: u32 = 1074044928;
pub const CM_CMU_BASE: u32 = 1074085888;
pub const CM_CRC_BASE: u32 = 1073777664;
pub const CM_DBGC_BASE: u32 = 3758366720;
pub const CM_DCU1_BASE: u32 = 1074077696;
pub const CM_DCU2_BASE: u32 = 1074078720;
pub const CM_DCU3_BASE: u32 = 1074079744;
pub const CM_DCU4_BASE: u32 = 1074080768;
pub const CM_DMA1_BASE: u32 = 1074081792;
pub const CM_DMA2_BASE: u32 = 1074082816;
pub const CM_EFM_BASE: u32 = 1073808384;
pub const CM_EMB0_BASE: u32 = 1073839104;
pub const CM_EMB1_BASE: u32 = 1073839136;
pub const CM_EMB2_BASE: u32 = 1073839168;
pub const CM_EMB3_BASE: u32 = 1073839200;
pub const CM_FCM_BASE: u32 = 1074037760;
pub const CM_GPIO_BASE: u32 = 1074083840;
pub const CM_HASH_BASE: u32 = 1073775616;
pub const CM_I2C1_BASE: u32 = 1074061312;
pub const CM_I2C2_BASE: u32 = 1074062336;
pub const CM_I2C3_BASE: u32 = 1074063360;
pub const CM_I2S1_BASE: u32 = 1073864704;
pub const CM_I2S2_BASE: u32 = 1073865728;
pub const CM_I2S3_BASE: u32 = 1073881088;
pub const CM_I2S4_BASE: u32 = 1073882112;
pub const CM_ICG_BASE: u32 = 1024;
pub const CM_INTC_BASE: u32 = 1074073600;
pub const CM_KEYSCAN_BASE: u32 = 1074072576;
pub const CM_MPU_BASE: u32 = 1074069504;
pub const CM_OTS_BASE: u32 = 1074045952;
pub const CM_PERIC_BASE: u32 = 1074091008;
pub const CM_PWC_BASE: u32 = 1074036736;
pub const CM_QSPI_BASE: u32 = 2617245696;
pub const CM_RMU_BASE: u32 = 1074086080;
pub const CM_RTC_BASE: u32 = 1074053120;
pub const CM_SDIOC1_BASE: u32 = 1074199552;
pub const CM_SDIOC2_BASE: u32 = 1074200576;
pub const CM_SPI1_BASE: u32 = 1073856512;
pub const CM_SPI2_BASE: u32 = 1073857536;
pub const CM_SPI3_BASE: u32 = 1073872896;
pub const CM_SPI4_BASE: u32 = 1073873920;
pub const CM_SRAMC_BASE: u32 = 1074071552;
pub const CM_SWDT_BASE: u32 = 1074041856;
pub const CM_TMR0_1_BASE: u32 = 1073889280;
pub const CM_TMR0_2_BASE: u32 = 1073890304;
pub const CM_TMR4_1_BASE: u32 = 1073836032;
pub const CM_TMR4_2_BASE: u32 = 1073891328;
pub const CM_TMR4_3_BASE: u32 = 1073892352;
pub const CM_TMR4_ECER_BASE: u32 = 1074091016;
pub const CM_TMR6_1_BASE: u32 = 1073840128;
pub const CM_TMR6_2_BASE: u32 = 1073841152;
pub const CM_TMR6_3_BASE: u32 = 1073842176;
pub const CM_TMR6_COMMON_BASE: u32 = 1073840896;
pub const CM_TMRA_1_BASE: u32 = 1073827840;
pub const CM_TMRA_2_BASE: u32 = 1073828864;
pub const CM_TMRA_3_BASE: u32 = 1073829888;
pub const CM_TMRA_4_BASE: u32 = 1073830912;
pub const CM_TMRA_5_BASE: u32 = 1073831936;
pub const CM_TMRA_6_BASE: u32 = 1073832960;
pub const CM_TRNG_BASE: u32 = 1074008064;
pub const CM_USART1_BASE: u32 = 1073860608;
pub const CM_USART2_BASE: u32 = 1073861632;
pub const CM_USART3_BASE: u32 = 1073876992;
pub const CM_USART4_BASE: u32 = 1073878016;
pub const CM_USBFS_BASE: u32 = 1074528256;
pub const CM_WDT_BASE: u32 = 1074040832;
pub const ADC_STR_STRT: u32 = 1;
pub const ADC_CR0_MS_POS: u32 = 0;
pub const ADC_CR0_MS: u32 = 3;
pub const ADC_CR0_MS_0: u32 = 1;
pub const ADC_CR0_MS_1: u32 = 2;
pub const ADC_CR0_ACCSEL_POS: u32 = 4;
pub const ADC_CR0_ACCSEL: u32 = 48;
pub const ADC_CR0_ACCSEL_0: u32 = 16;
pub const ADC_CR0_ACCSEL_1: u32 = 32;
pub const ADC_CR0_CLREN_POS: u32 = 6;
pub const ADC_CR0_CLREN: u32 = 64;
pub const ADC_CR0_DFMT_POS: u32 = 7;
pub const ADC_CR0_DFMT: u32 = 128;
pub const ADC_CR0_AVCNT_POS: u32 = 8;
pub const ADC_CR0_AVCNT: u32 = 1792;
pub const ADC_CR1_RSCHSEL_POS: u32 = 2;
pub const ADC_CR1_RSCHSEL: u32 = 4;
pub const ADC_TRGSR_TRGSELA_POS: u32 = 0;
pub const ADC_TRGSR_TRGSELA: u32 = 3;
pub const ADC_TRGSR_TRGSELA_0: u32 = 1;
pub const ADC_TRGSR_TRGSELA_1: u32 = 2;
pub const ADC_TRGSR_TRGENA_POS: u32 = 7;
pub const ADC_TRGSR_TRGENA: u32 = 128;
pub const ADC_TRGSR_TRGSELB_POS: u32 = 8;
pub const ADC_TRGSR_TRGSELB: u32 = 768;
pub const ADC_TRGSR_TRGSELB_0: u32 = 256;
pub const ADC_TRGSR_TRGSELB_1: u32 = 512;
pub const ADC_TRGSR_TRGENB_POS: u32 = 15;
pub const ADC_TRGSR_TRGENB: u32 = 32768;
pub const ADC_CHSELRA_CHSELA: u32 = 131071;
pub const ADC_CHSELRB_CHSELB: u32 = 131071;
pub const ADC_AVCHSELR_AVCHSEL: u32 = 131071;
pub const ADC_SSTR0: u32 = 255;
pub const ADC_SSTR1: u32 = 255;
pub const ADC_SSTR2: u32 = 255;
pub const ADC_SSTR3: u32 = 255;
pub const ADC_SSTR4: u32 = 255;
pub const ADC_SSTR5: u32 = 255;
pub const ADC_SSTR6: u32 = 255;
pub const ADC_SSTR7: u32 = 255;
pub const ADC_SSTR8: u32 = 255;
pub const ADC_SSTR9: u32 = 255;
pub const ADC_SSTR10: u32 = 255;
pub const ADC_SSTR11: u32 = 255;
pub const ADC_SSTR12: u32 = 255;
pub const ADC_SSTR13: u32 = 255;
pub const ADC_SSTR14: u32 = 255;
pub const ADC_SSTR15: u32 = 255;
pub const ADC_SSTRL: u32 = 255;
pub const ADC_CHMUXR0_CH00MUX_POS: u32 = 0;
pub const ADC_CHMUXR0_CH00MUX: u32 = 15;
pub const ADC_CHMUXR0_CH01MUX_POS: u32 = 4;
pub const ADC_CHMUXR0_CH01MUX: u32 = 240;
pub const ADC_CHMUXR0_CH02MUX_POS: u32 = 8;
pub const ADC_CHMUXR0_CH02MUX: u32 = 3840;
pub const ADC_CHMUXR0_CH03MUX_POS: u32 = 12;
pub const ADC_CHMUXR0_CH03MUX: u32 = 61440;
pub const ADC_CHMUXR1_CH04MUX_POS: u32 = 0;
pub const ADC_CHMUXR1_CH04MUX: u32 = 15;
pub const ADC_CHMUXR1_CH05MUX_POS: u32 = 4;
pub const ADC_CHMUXR1_CH05MUX: u32 = 240;
pub const ADC_CHMUXR1_CH06MUX_POS: u32 = 8;
pub const ADC_CHMUXR1_CH06MUX: u32 = 3840;
pub const ADC_CHMUXR1_CH07MUX_POS: u32 = 12;
pub const ADC_CHMUXR1_CH07MUX: u32 = 61440;
pub const ADC_CHMUXR2_CH08MUX_POS: u32 = 0;
pub const ADC_CHMUXR2_CH08MUX: u32 = 15;
pub const ADC_CHMUXR2_CH09MUX_POS: u32 = 4;
pub const ADC_CHMUXR2_CH09MUX: u32 = 240;
pub const ADC_CHMUXR2_CH10MUX_POS: u32 = 8;
pub const ADC_CHMUXR2_CH10MUX: u32 = 3840;
pub const ADC_CHMUXR2_CH11MUX_POS: u32 = 12;
pub const ADC_CHMUXR2_CH11MUX: u32 = 61440;
pub const ADC_CHMUXR3_CH12MUX_POS: u32 = 0;
pub const ADC_CHMUXR3_CH12MUX: u32 = 15;
pub const ADC_CHMUXR3_CH13MUX_POS: u32 = 4;
pub const ADC_CHMUXR3_CH13MUX: u32 = 240;
pub const ADC_CHMUXR3_CH14MUX_POS: u32 = 8;
pub const ADC_CHMUXR3_CH14MUX: u32 = 3840;
pub const ADC_CHMUXR3_CH15MUX_POS: u32 = 12;
pub const ADC_CHMUXR3_CH15MUX: u32 = 61440;
pub const ADC_ISR_EOCAF_POS: u32 = 0;
pub const ADC_ISR_EOCAF: u32 = 1;
pub const ADC_ISR_EOCBF_POS: u32 = 1;
pub const ADC_ISR_EOCBF: u32 = 2;
pub const ADC_ICR_EOCAIEN_POS: u32 = 0;
pub const ADC_ICR_EOCAIEN: u32 = 1;
pub const ADC_ICR_EOCBIEN_POS: u32 = 1;
pub const ADC_ICR_EOCBIEN: u32 = 2;
pub const ADC_SYNCCR_SYNCEN_POS: u32 = 0;
pub const ADC_SYNCCR_SYNCEN: u32 = 1;
pub const ADC_SYNCCR_SYNCMD_POS: u32 = 4;
pub const ADC_SYNCCR_SYNCMD: u32 = 112;
pub const ADC_SYNCCR_SYNCDLY_POS: u32 = 8;
pub const ADC_SYNCCR_SYNCDLY: u32 = 65280;
pub const ADC_DR0: u32 = 65535;
pub const ADC_DR1: u32 = 65535;
pub const ADC_DR2: u32 = 65535;
pub const ADC_DR3: u32 = 65535;
pub const ADC_DR4: u32 = 65535;
pub const ADC_DR5: u32 = 65535;
pub const ADC_DR6: u32 = 65535;
pub const ADC_DR7: u32 = 65535;
pub const ADC_DR8: u32 = 65535;
pub const ADC_DR9: u32 = 65535;
pub const ADC_DR10: u32 = 65535;
pub const ADC_DR11: u32 = 65535;
pub const ADC_DR12: u32 = 65535;
pub const ADC_DR13: u32 = 65535;
pub const ADC_DR14: u32 = 65535;
pub const ADC_DR15: u32 = 65535;
pub const ADC_DR16: u32 = 65535;
pub const ADC_AWDCR_AWDEN_POS: u32 = 0;
pub const ADC_AWDCR_AWDEN: u32 = 1;
pub const ADC_AWDCR_AWDMD_POS: u32 = 4;
pub const ADC_AWDCR_AWDMD: u32 = 16;
pub const ADC_AWDCR_AWDSS_POS: u32 = 6;
pub const ADC_AWDCR_AWDSS: u32 = 192;
pub const ADC_AWDCR_AWDSS_0: u32 = 64;
pub const ADC_AWDCR_AWDSS_1: u32 = 128;
pub const ADC_AWDCR_AWDIEN_POS: u32 = 8;
pub const ADC_AWDCR_AWDIEN: u32 = 256;
pub const ADC_AWDDR0: u32 = 65535;
pub const ADC_AWDDR1: u32 = 65535;
pub const ADC_AWDCHSR_AWDCH: u32 = 131071;
pub const ADC_AWDSR_AWDF: u32 = 131071;
pub const ADC_PGACR_PGACTL: u32 = 15;
pub const ADC_PGAGSR_GAIN: u32 = 15;
pub const ADC_PGAINSR0_PGAINSEL: u32 = 511;
pub const ADC_PGAINSR0_PGAINSEL_0: u32 = 1;
pub const ADC_PGAINSR0_PGAINSEL_1: u32 = 2;
pub const ADC_PGAINSR0_PGAINSEL_2: u32 = 4;
pub const ADC_PGAINSR0_PGAINSEL_3: u32 = 8;
pub const ADC_PGAINSR0_PGAINSEL_4: u32 = 16;
pub const ADC_PGAINSR0_PGAINSEL_5: u32 = 32;
pub const ADC_PGAINSR0_PGAINSEL_6: u32 = 64;
pub const ADC_PGAINSR0_PGAINSEL_7: u32 = 128;
pub const ADC_PGAINSR0_PGAINSEL_8: u32 = 256;
pub const ADC_PGAINSR1_PGAVSSEN: u32 = 1;
pub const AES_CR_START_POS: u32 = 0;
pub const AES_CR_START: u32 = 1;
pub const AES_CR_MODE_POS: u32 = 1;
pub const AES_CR_MODE: u32 = 2;
pub const AES_DR0: u32 = 4294967295;
pub const AES_DR1: u32 = 4294967295;
pub const AES_DR2: u32 = 4294967295;
pub const AES_DR3: u32 = 4294967295;
pub const AES_KR0: u32 = 4294967295;
pub const AES_KR1: u32 = 4294967295;
pub const AES_KR2: u32 = 4294967295;
pub const AES_KR3: u32 = 4294967295;
pub const AOS_INTSFTTRG_STRG: u32 = 1;
pub const AOS_DCU_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DCU_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DCU_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DCU_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DCU_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DCU_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA1_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA1_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA1_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA1_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA1_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA1_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA2_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA2_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA2_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA2_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA2_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA2_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA_RC_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA_RC_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA_RC_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA_RC_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA_RC_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA_RC_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMR6_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMR6_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMR6_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMR6_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMR6_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMR6_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMR0_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMR0_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMR0_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMR0_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMR0_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMR0_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_PEVNT_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_PEVNT_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_PEVNT_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_PEVNT_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_PEVNT_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_PEVNT_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMRA_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMRA_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMRA_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMRA_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMRA_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMRA_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_OTS_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_OTS_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_OTS_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_OTS_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_OTS_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_OTS_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_ADC1_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_ADC1_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_ADC1_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_ADC1_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_ADC1_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_ADC1_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_ADC2_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_ADC2_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_ADC2_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_ADC2_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_ADC2_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_ADC2_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_COMTRG1_COMTRG: u32 = 511;
pub const AOS_COMTRG2_COMTRG: u32 = 511;
pub const AOS_PEVNTDIRR_PDIR: u32 = 65535;
pub const AOS_PEVNTIDR_PIN: u32 = 65535;
pub const AOS_PEVNTODR_POUT: u32 = 65535;
pub const AOS_PEVNTORR_POR: u32 = 65535;
pub const AOS_PEVNTOSR_POS: u32 = 65535;
pub const AOS_PEVNTRISR_RIS: u32 = 65535;
pub const AOS_PEVNTFALR_FAL: u32 = 65535;
pub const AOS_PEVNTNFCR_NFEN1_POS: u32 = 0;
pub const AOS_PEVNTNFCR_NFEN1: u32 = 1;
pub const AOS_PEVNTNFCR_DIVS1_POS: u32 = 1;
pub const AOS_PEVNTNFCR_DIVS1: u32 = 6;
pub const AOS_PEVNTNFCR_NFEN2_POS: u32 = 8;
pub const AOS_PEVNTNFCR_NFEN2: u32 = 256;
pub const AOS_PEVNTNFCR_DIVS2_POS: u32 = 9;
pub const AOS_PEVNTNFCR_DIVS2: u32 = 1536;
pub const AOS_PEVNTNFCR_NFEN3_POS: u32 = 16;
pub const AOS_PEVNTNFCR_NFEN3: u32 = 65536;
pub const AOS_PEVNTNFCR_DIVS3_POS: u32 = 17;
pub const AOS_PEVNTNFCR_DIVS3: u32 = 393216;
pub const AOS_PEVNTNFCR_NFEN4_POS: u32 = 24;
pub const AOS_PEVNTNFCR_NFEN4: u32 = 16777216;
pub const AOS_PEVNTNFCR_DIVS4_POS: u32 = 25;
pub const AOS_PEVNTNFCR_DIVS4: u32 = 100663296;
pub const CAN_RBUF: u32 = 4294967295;
pub const CAN_TBUF: u32 = 4294967295;
pub const CAN_CFG_STAT_BUSOFF_POS: u32 = 0;
pub const CAN_CFG_STAT_BUSOFF: u32 = 1;
pub const CAN_CFG_STAT_TACTIVE_POS: u32 = 1;
pub const CAN_CFG_STAT_TACTIVE: u32 = 2;
pub const CAN_CFG_STAT_RACTIVE_POS: u32 = 2;
pub const CAN_CFG_STAT_RACTIVE: u32 = 4;
pub const CAN_CFG_STAT_TSSS_POS: u32 = 3;
pub const CAN_CFG_STAT_TSSS: u32 = 8;
pub const CAN_CFG_STAT_TPSS_POS: u32 = 4;
pub const CAN_CFG_STAT_TPSS: u32 = 16;
pub const CAN_CFG_STAT_LBMI_POS: u32 = 5;
pub const CAN_CFG_STAT_LBMI: u32 = 32;
pub const CAN_CFG_STAT_LBME_POS: u32 = 6;
pub const CAN_CFG_STAT_LBME: u32 = 64;
pub const CAN_CFG_STAT_RESET_POS: u32 = 7;
pub const CAN_CFG_STAT_RESET: u32 = 128;
pub const CAN_TCMD_TSA_POS: u32 = 0;
pub const CAN_TCMD_TSA: u32 = 1;
pub const CAN_TCMD_TSALL_POS: u32 = 1;
pub const CAN_TCMD_TSALL: u32 = 2;
pub const CAN_TCMD_TSONE_POS: u32 = 2;
pub const CAN_TCMD_TSONE: u32 = 4;
pub const CAN_TCMD_TPA_POS: u32 = 3;
pub const CAN_TCMD_TPA: u32 = 8;
pub const CAN_TCMD_TPE_POS: u32 = 4;
pub const CAN_TCMD_TPE: u32 = 16;
pub const CAN_TCMD_LOM_POS: u32 = 6;
pub const CAN_TCMD_LOM: u32 = 64;
pub const CAN_TCMD_TBSEL_POS: u32 = 7;
pub const CAN_TCMD_TBSEL: u32 = 128;
pub const CAN_TCTRL_TSSTAT_POS: u32 = 0;
pub const CAN_TCTRL_TSSTAT: u32 = 3;
pub const CAN_TCTRL_TSSTAT_0: u32 = 1;
pub const CAN_TCTRL_TSSTAT_1: u32 = 2;
pub const CAN_TCTRL_TTTBM_POS: u32 = 4;
pub const CAN_TCTRL_TTTBM: u32 = 16;
pub const CAN_TCTRL_TSMODE_POS: u32 = 5;
pub const CAN_TCTRL_TSMODE: u32 = 32;
pub const CAN_TCTRL_TSNEXT_POS: u32 = 6;
pub const CAN_TCTRL_TSNEXT: u32 = 64;
pub const CAN_RCTRL_RSTAT_POS: u32 = 0;
pub const CAN_RCTRL_RSTAT: u32 = 3;
pub const CAN_RCTRL_RSTAT_0: u32 = 1;
pub const CAN_RCTRL_RSTAT_1: u32 = 2;
pub const CAN_RCTRL_RBALL_POS: u32 = 3;
pub const CAN_RCTRL_RBALL: u32 = 8;
pub const CAN_RCTRL_RREL_POS: u32 = 4;
pub const CAN_RCTRL_RREL: u32 = 16;
pub const CAN_RCTRL_ROV_POS: u32 = 5;
pub const CAN_RCTRL_ROV: u32 = 32;
pub const CAN_RCTRL_ROM_POS: u32 = 6;
pub const CAN_RCTRL_ROM: u32 = 64;
pub const CAN_RCTRL_SACK_POS: u32 = 7;
pub const CAN_RCTRL_SACK: u32 = 128;
pub const CAN_RTIE_TSFF_POS: u32 = 0;
pub const CAN_RTIE_TSFF: u32 = 1;
pub const CAN_RTIE_EIE_POS: u32 = 1;
pub const CAN_RTIE_EIE: u32 = 2;
pub const CAN_RTIE_TSIE_POS: u32 = 2;
pub const CAN_RTIE_TSIE: u32 = 4;
pub const CAN_RTIE_TPIE_POS: u32 = 3;
pub const CAN_RTIE_TPIE: u32 = 8;
pub const CAN_RTIE_RAFIE_POS: u32 = 4;
pub const CAN_RTIE_RAFIE: u32 = 16;
pub const CAN_RTIE_RFIE_POS: u32 = 5;
pub const CAN_RTIE_RFIE: u32 = 32;
pub const CAN_RTIE_ROIE_POS: u32 = 6;
pub const CAN_RTIE_ROIE: u32 = 64;
pub const CAN_RTIE_RIE_POS: u32 = 7;
pub const CAN_RTIE_RIE: u32 = 128;
pub const CAN_RTIF_AIF_POS: u32 = 0;
pub const CAN_RTIF_AIF: u32 = 1;
pub const CAN_RTIF_EIF_POS: u32 = 1;
pub const CAN_RTIF_EIF: u32 = 2;
pub const CAN_RTIF_TSIF_POS: u32 = 2;
pub const CAN_RTIF_TSIF: u32 = 4;
pub const CAN_RTIF_TPIF_POS: u32 = 3;
pub const CAN_RTIF_TPIF: u32 = 8;
pub const CAN_RTIF_RAFIF_POS: u32 = 4;
pub const CAN_RTIF_RAFIF: u32 = 16;
pub const CAN_RTIF_RFIF_POS: u32 = 5;
pub const CAN_RTIF_RFIF: u32 = 32;
pub const CAN_RTIF_ROIF_POS: u32 = 6;
pub const CAN_RTIF_ROIF: u32 = 64;
pub const CAN_RTIF_RIF_POS: u32 = 7;
pub const CAN_RTIF_RIF: u32 = 128;
pub const CAN_ERRINT_BEIF_POS: u32 = 0;
pub const CAN_ERRINT_BEIF: u32 = 1;
pub const CAN_ERRINT_BEIE_POS: u32 = 1;
pub const CAN_ERRINT_BEIE: u32 = 2;
pub const CAN_ERRINT_ALIF_POS: u32 = 2;
pub const CAN_ERRINT_ALIF: u32 = 4;
pub const CAN_ERRINT_ALIE_POS: u32 = 3;
pub const CAN_ERRINT_ALIE: u32 = 8;
pub const CAN_ERRINT_EPIF_POS: u32 = 4;
pub const CAN_ERRINT_EPIF: u32 = 16;
pub const CAN_ERRINT_EPIE_POS: u32 = 5;
pub const CAN_ERRINT_EPIE: u32 = 32;
pub const CAN_ERRINT_EPASS_POS: u32 = 6;
pub const CAN_ERRINT_EPASS: u32 = 64;
pub const CAN_ERRINT_EWARN_POS: u32 = 7;
pub const CAN_ERRINT_EWARN: u32 = 128;
pub const CAN_LIMIT_EWL_POS: u32 = 0;
pub const CAN_LIMIT_EWL: u32 = 15;
pub const CAN_LIMIT_AFWL_POS: u32 = 4;
pub const CAN_LIMIT_AFWL: u32 = 240;
pub const CAN_SBT_S_SEG_1_POS: u32 = 0;
pub const CAN_SBT_S_SEG_1: u32 = 255;
pub const CAN_SBT_S_SEG_2_POS: u32 = 8;
pub const CAN_SBT_S_SEG_2: u32 = 32512;
pub const CAN_SBT_S_SJW_POS: u32 = 16;
pub const CAN_SBT_S_SJW: u32 = 8323072;
pub const CAN_SBT_S_PRESC_POS: u32 = 24;
pub const CAN_SBT_S_PRESC: u32 = 4278190080;
pub const CAN_EALCAP_ALC_POS: u32 = 0;
pub const CAN_EALCAP_ALC: u32 = 31;
pub const CAN_EALCAP_KOER_POS: u32 = 5;
pub const CAN_EALCAP_KOER: u32 = 224;
pub const CAN_RECNT: u32 = 255;
pub const CAN_TECNT: u32 = 255;
pub const CAN_ACFCTRL_ACFADR_POS: u32 = 0;
pub const CAN_ACFCTRL_ACFADR: u32 = 15;
pub const CAN_ACFCTRL_SELMASK_POS: u32 = 5;
pub const CAN_ACFCTRL_SELMASK: u32 = 32;
pub const CAN_ACFEN_AE_1_POS: u32 = 0;
pub const CAN_ACFEN_AE_1: u32 = 1;
pub const CAN_ACFEN_AE_2_POS: u32 = 1;
pub const CAN_ACFEN_AE_2: u32 = 2;
pub const CAN_ACFEN_AE_3_POS: u32 = 2;
pub const CAN_ACFEN_AE_3: u32 = 4;
pub const CAN_ACFEN_AE_4_POS: u32 = 3;
pub const CAN_ACFEN_AE_4: u32 = 8;
pub const CAN_ACFEN_AE_5_POS: u32 = 4;
pub const CAN_ACFEN_AE_5: u32 = 16;
pub const CAN_ACFEN_AE_6_POS: u32 = 5;
pub const CAN_ACFEN_AE_6: u32 = 32;
pub const CAN_ACFEN_AE_7_POS: u32 = 6;
pub const CAN_ACFEN_AE_7: u32 = 64;
pub const CAN_ACFEN_AE_8_POS: u32 = 7;
pub const CAN_ACFEN_AE_8: u32 = 128;
pub const CAN_ACF_ACODEORAMASK_POS: u32 = 0;
pub const CAN_ACF_ACODEORAMASK: u32 = 536870911;
pub const CAN_ACF_AIDE_POS: u32 = 29;
pub const CAN_ACF_AIDE: u32 = 536870912;
pub const CAN_ACF_AIDEE_POS: u32 = 30;
pub const CAN_ACF_AIDEE: u32 = 1073741824;
pub const CAN_TBSLOT_TBPTR_POS: u32 = 0;
pub const CAN_TBSLOT_TBPTR: u32 = 63;
pub const CAN_TBSLOT_TBF_POS: u32 = 6;
pub const CAN_TBSLOT_TBF: u32 = 64;
pub const CAN_TBSLOT_TBE_POS: u32 = 7;
pub const CAN_TBSLOT_TBE: u32 = 128;
pub const CAN_TTCFG_TTEN_POS: u32 = 0;
pub const CAN_TTCFG_TTEN: u32 = 1;
pub const CAN_TTCFG_T_PRESC_POS: u32 = 1;
pub const CAN_TTCFG_T_PRESC: u32 = 6;
pub const CAN_TTCFG_T_PRESC_0: u32 = 2;
pub const CAN_TTCFG_T_PRESC_1: u32 = 4;
pub const CAN_TTCFG_TTIF_POS: u32 = 3;
pub const CAN_TTCFG_TTIF: u32 = 8;
pub const CAN_TTCFG_TTIE_POS: u32 = 4;
pub const CAN_TTCFG_TTIE: u32 = 16;
pub const CAN_TTCFG_TEIF_POS: u32 = 5;
pub const CAN_TTCFG_TEIF: u32 = 32;
pub const CAN_TTCFG_WTIF_POS: u32 = 6;
pub const CAN_TTCFG_WTIF: u32 = 64;
pub const CAN_TTCFG_WTIE_POS: u32 = 7;
pub const CAN_TTCFG_WTIE: u32 = 128;
pub const CAN_REF_MSG_REF_ID_POS: u32 = 0;
pub const CAN_REF_MSG_REF_ID: u32 = 536870911;
pub const CAN_REF_MSG_REF_IDE_POS: u32 = 31;
pub const CAN_REF_MSG_REF_IDE: u32 = 2147483648;
pub const CAN_TRG_CFG_TTPTR_POS: u32 = 0;
pub const CAN_TRG_CFG_TTPTR: u32 = 63;
pub const CAN_TRG_CFG_TTYPE_POS: u32 = 8;
pub const CAN_TRG_CFG_TTYPE: u32 = 1792;
pub const CAN_TRG_CFG_TTYPE_0: u32 = 256;
pub const CAN_TRG_CFG_TTYPE_1: u32 = 512;
pub const CAN_TRG_CFG_TTYPE_2: u32 = 1024;
pub const CAN_TRG_CFG_TEW_POS: u32 = 12;
pub const CAN_TRG_CFG_TEW: u32 = 61440;
pub const CAN_TT_TRIG: u32 = 65535;
pub const CAN_TT_WTRIG: u32 = 65535;
pub const CMP_CTRL_FLTSL_POS: u32 = 0;
pub const CMP_CTRL_FLTSL: u32 = 7;
pub const CMP_CTRL_EDGSL_POS: u32 = 5;
pub const CMP_CTRL_EDGSL: u32 = 96;
pub const CMP_CTRL_EDGSL_0: u32 = 32;
pub const CMP_CTRL_EDGSL_1: u32 = 64;
pub const CMP_CTRL_IEN_POS: u32 = 7;
pub const CMP_CTRL_IEN: u32 = 128;
pub const CMP_CTRL_CVSEN_POS: u32 = 8;
pub const CMP_CTRL_CVSEN: u32 = 256;
pub const CMP_CTRL_OUTEN_POS: u32 = 12;
pub const CMP_CTRL_OUTEN: u32 = 4096;
pub const CMP_CTRL_INV_POS: u32 = 13;
pub const CMP_CTRL_INV: u32 = 8192;
pub const CMP_CTRL_CMPOE_POS: u32 = 14;
pub const CMP_CTRL_CMPOE: u32 = 16384;
pub const CMP_CTRL_CMPON_POS: u32 = 15;
pub const CMP_CTRL_CMPON: u32 = 32768;
pub const CMP_VLTSEL_RVSL_POS: u32 = 0;
pub const CMP_VLTSEL_RVSL: u32 = 15;
pub const CMP_VLTSEL_RVSL_0: u32 = 1;
pub const CMP_VLTSEL_RVSL_1: u32 = 2;
pub const CMP_VLTSEL_RVSL_2: u32 = 4;
pub const CMP_VLTSEL_RVSL_3: u32 = 8;
pub const CMP_VLTSEL_CVSL_POS: u32 = 8;
pub const CMP_VLTSEL_CVSL: u32 = 3840;
pub const CMP_VLTSEL_CVSL_0: u32 = 256;
pub const CMP_VLTSEL_CVSL_1: u32 = 512;
pub const CMP_VLTSEL_CVSL_2: u32 = 1024;
pub const CMP_VLTSEL_CVSL_3: u32 = 2048;
pub const CMP_VLTSEL_C4SL_POS: u32 = 12;
pub const CMP_VLTSEL_C4SL: u32 = 28672;
pub const CMP_VLTSEL_C4SL_0: u32 = 4096;
pub const CMP_VLTSEL_C4SL_1: u32 = 8192;
pub const CMP_VLTSEL_C4SL_2: u32 = 16384;
pub const CMP_OUTMON_OMON_POS: u32 = 0;
pub const CMP_OUTMON_OMON: u32 = 1;
pub const CMP_OUTMON_CVST_POS: u32 = 8;
pub const CMP_OUTMON_CVST: u32 = 3840;
pub const CMP_CVSSTB_STB: u32 = 15;
pub const CMP_CVSPRD_PRD: u32 = 255;
pub const CMP_COMMON_DADR1_DATA: u32 = 255;
pub const CMP_COMMON_DADR2_DATA: u32 = 255;
pub const CMP_COMMON_DACR_DA1EN_POS: u32 = 0;
pub const CMP_COMMON_DACR_DA1EN: u32 = 1;
pub const CMP_COMMON_DACR_DA2EN_POS: u32 = 1;
pub const CMP_COMMON_DACR_DA2EN: u32 = 2;
pub const CMP_COMMON_RVADC_DA1SW_POS: u32 = 0;
pub const CMP_COMMON_RVADC_DA1SW: u32 = 1;
pub const CMP_COMMON_RVADC_DA2SW_POS: u32 = 1;
pub const CMP_COMMON_RVADC_DA2SW: u32 = 2;
pub const CMP_COMMON_RVADC_VREFSW_POS: u32 = 4;
pub const CMP_COMMON_RVADC_VREFSW: u32 = 16;
pub const CMP_COMMON_RVADC_WPRT_POS: u32 = 8;
pub const CMP_COMMON_RVADC_WPRT: u32 = 65280;
pub const CMU_PERICKSEL_PERICKSEL: u32 = 15;
pub const CMU_I2SCKSEL_I2S1CKSEL_POS: u32 = 0;
pub const CMU_I2SCKSEL_I2S1CKSEL: u32 = 15;
pub const CMU_I2SCKSEL_I2S2CKSEL_POS: u32 = 4;
pub const CMU_I2SCKSEL_I2S2CKSEL: u32 = 240;
pub const CMU_I2SCKSEL_I2S3CKSEL_POS: u32 = 8;
pub const CMU_I2SCKSEL_I2S3CKSEL: u32 = 3840;
pub const CMU_I2SCKSEL_I2S4CKSEL_POS: u32 = 12;
pub const CMU_I2SCKSEL_I2S4CKSEL: u32 = 61440;
pub const CMU_SCFGR_PCLK0S_POS: u32 = 0;
pub const CMU_SCFGR_PCLK0S: u32 = 7;
pub const CMU_SCFGR_PCLK1S_POS: u32 = 4;
pub const CMU_SCFGR_PCLK1S: u32 = 112;
pub const CMU_SCFGR_PCLK2S_POS: u32 = 8;
pub const CMU_SCFGR_PCLK2S: u32 = 1792;
pub const CMU_SCFGR_PCLK3S_POS: u32 = 12;
pub const CMU_SCFGR_PCLK3S: u32 = 28672;
pub const CMU_SCFGR_PCLK4S_POS: u32 = 16;
pub const CMU_SCFGR_PCLK4S: u32 = 458752;
pub const CMU_SCFGR_EXCKS_POS: u32 = 20;
pub const CMU_SCFGR_EXCKS: u32 = 7340032;
pub const CMU_SCFGR_HCLKS_POS: u32 = 24;
pub const CMU_SCFGR_HCLKS: u32 = 117440512;
pub const CMU_USBCKCFGR_USBCKS_POS: u32 = 4;
pub const CMU_USBCKCFGR_USBCKS: u32 = 240;
pub const CMU_CKSWR_CKSW: u32 = 7;
pub const CMU_PLLCR_MPLLOFF: u32 = 1;
pub const CMU_UPLLCR_UPLLOFF: u32 = 1;
pub const CMU_XTALCR_XTALSTP: u32 = 1;
pub const CMU_HRCCR_HRCSTP: u32 = 1;
pub const CMU_MRCCR_MRCSTP: u32 = 1;
pub const CMU_OSCSTBSR_HRCSTBF_POS: u32 = 0;
pub const CMU_OSCSTBSR_HRCSTBF: u32 = 1;
pub const CMU_OSCSTBSR_XTALSTBF_POS: u32 = 3;
pub const CMU_OSCSTBSR_XTALSTBF: u32 = 8;
pub const CMU_OSCSTBSR_MPLLSTBF_POS: u32 = 5;
pub const CMU_OSCSTBSR_MPLLSTBF: u32 = 32;
pub const CMU_OSCSTBSR_UPLLSTBF_POS: u32 = 6;
pub const CMU_OSCSTBSR_UPLLSTBF: u32 = 64;
pub const CMU_MCOCFGR_MCOSEL_POS: u32 = 0;
pub const CMU_MCOCFGR_MCOSEL: u32 = 15;
pub const CMU_MCOCFGR_MCODIV_POS: u32 = 4;
pub const CMU_MCOCFGR_MCODIV: u32 = 112;
pub const CMU_MCOCFGR_MCOEN_POS: u32 = 7;
pub const CMU_MCOCFGR_MCOEN: u32 = 128;
pub const CMU_TPIUCKCFGR_TPIUCKS_POS: u32 = 0;
pub const CMU_TPIUCKCFGR_TPIUCKS: u32 = 3;
pub const CMU_TPIUCKCFGR_TPIUCKS_0: u32 = 1;
pub const CMU_TPIUCKCFGR_TPIUCKS_1: u32 = 2;
pub const CMU_TPIUCKCFGR_TPIUCKOE_POS: u32 = 7;
pub const CMU_TPIUCKCFGR_TPIUCKOE: u32 = 128;
pub const CMU_XTALSTDCR_XTALSTDIE_POS: u32 = 0;
pub const CMU_XTALSTDCR_XTALSTDIE: u32 = 1;
pub const CMU_XTALSTDCR_XTALSTDRE_POS: u32 = 1;
pub const CMU_XTALSTDCR_XTALSTDRE: u32 = 2;
pub const CMU_XTALSTDCR_XTALSTDRIS_POS: u32 = 2;
pub const CMU_XTALSTDCR_XTALSTDRIS: u32 = 4;
pub const CMU_XTALSTDCR_XTALSTDE_POS: u32 = 7;
pub const CMU_XTALSTDCR_XTALSTDE: u32 = 128;
pub const CMU_XTALSTDSR_XTALSTDF: u32 = 1;
pub const CMU_MRCTRM: u32 = 255;
pub const CMU_HRCTRM: u32 = 255;
pub const CMU_XTALSTBCR_XTALSTB: u32 = 15;
pub const CMU_XTALSTBCR_XTALSTB_0: u32 = 1;
pub const CMU_XTALSTBCR_XTALSTB_1: u32 = 2;
pub const CMU_XTALSTBCR_XTALSTB_2: u32 = 4;
pub const CMU_XTALSTBCR_XTALSTB_3: u32 = 8;
pub const CMU_PLLCFGR_MPLLM_POS: u32 = 0;
pub const CMU_PLLCFGR_MPLLM: u32 = 31;
pub const CMU_PLLCFGR_PLLSRC_POS: u32 = 7;
pub const CMU_PLLCFGR_PLLSRC: u32 = 128;
pub const CMU_PLLCFGR_MPLLN_POS: u32 = 8;
pub const CMU_PLLCFGR_MPLLN: u32 = 130816;
pub const CMU_PLLCFGR_MPLLR_POS: u32 = 20;
pub const CMU_PLLCFGR_MPLLR: u32 = 15728640;
pub const CMU_PLLCFGR_MPLLQ_POS: u32 = 24;
pub const CMU_PLLCFGR_MPLLQ: u32 = 251658240;
pub const CMU_PLLCFGR_MPLLP_POS: u32 = 28;
pub const CMU_PLLCFGR_MPLLP: u32 = 4026531840;
pub const CMU_UPLLCFGR_UPLLM_POS: u32 = 0;
pub const CMU_UPLLCFGR_UPLLM: u32 = 31;
pub const CMU_UPLLCFGR_UPLLN_POS: u32 = 8;
pub const CMU_UPLLCFGR_UPLLN: u32 = 130816;
pub const CMU_UPLLCFGR_UPLLR_POS: u32 = 20;
pub const CMU_UPLLCFGR_UPLLR: u32 = 15728640;
pub const CMU_UPLLCFGR_UPLLQ_POS: u32 = 24;
pub const CMU_UPLLCFGR_UPLLQ: u32 = 251658240;
pub const CMU_UPLLCFGR_UPLLP_POS: u32 = 28;
pub const CMU_UPLLCFGR_UPLLP: u32 = 4026531840;
pub const CMU_XTALCFGR_XTALDRV_POS: u32 = 4;
pub const CMU_XTALCFGR_XTALDRV: u32 = 48;
pub const CMU_XTALCFGR_XTALDRV_0: u32 = 16;
pub const CMU_XTALCFGR_XTALDRV_1: u32 = 32;
pub const CMU_XTALCFGR_XTALMS_POS: u32 = 6;
pub const CMU_XTALCFGR_XTALMS: u32 = 64;
pub const CMU_XTALCFGR_SUPDRV_POS: u32 = 7;
pub const CMU_XTALCFGR_SUPDRV: u32 = 128;
pub const CMU_XTAL32CR_XTAL32STP: u32 = 1;
pub const CMU_XTAL32CFGR_XTAL32DRV: u32 = 7;
pub const CMU_XTAL32CFGR_XTAL32DRV_0: u32 = 1;
pub const CMU_XTAL32CFGR_XTAL32DRV_1: u32 = 2;
pub const CMU_XTAL32CFGR_XTAL32DRV_2: u32 = 4;
pub const CMU_XTAL32NFR_XTAL32NF: u32 = 3;
pub const CMU_XTAL32NFR_XTAL32NF_0: u32 = 1;
pub const CMU_XTAL32NFR_XTAL32NF_1: u32 = 2;
pub const CMU_LRCCR_LRCSTP: u32 = 1;
pub const CMU_LRCTRM: u32 = 255;
pub const CRC_CR_CR_POS: u32 = 1;
pub const CRC_CR_CR: u32 = 2;
pub const CRC_CR_REFIN_POS: u32 = 2;
pub const CRC_CR_REFIN: u32 = 4;
pub const CRC_CR_REFOUT_POS: u32 = 3;
pub const CRC_CR_REFOUT: u32 = 8;
pub const CRC_CR_XOROUT_POS: u32 = 4;
pub const CRC_CR_XOROUT: u32 = 16;
pub const CRC_RESLT_CRC_REG_POS: u32 = 0;
pub const CRC_RESLT_CRC_REG: u32 = 65535;
pub const CRC_RESLT_CRCFLAG_16_POS: u32 = 16;
pub const CRC_RESLT_CRCFLAG_16: u32 = 65536;
pub const CRC_FLG_CRCFLAG_32: u32 = 1;
pub const CRC_DAT0: u32 = 4294967295;
pub const CRC_DAT1: u32 = 4294967295;
pub const CRC_DAT2: u32 = 4294967295;
pub const CRC_DAT3: u32 = 4294967295;
pub const CRC_DAT4: u32 = 4294967295;
pub const CRC_DAT5: u32 = 4294967295;
pub const CRC_DAT6: u32 = 4294967295;
pub const CRC_DAT7: u32 = 4294967295;
pub const CRC_DAT8: u32 = 4294967295;
pub const CRC_DAT9: u32 = 4294967295;
pub const CRC_DAT10: u32 = 4294967295;
pub const CRC_DAT11: u32 = 4294967295;
pub const CRC_DAT12: u32 = 4294967295;
pub const CRC_DAT13: u32 = 4294967295;
pub const CRC_DAT14: u32 = 4294967295;
pub const CRC_DAT15: u32 = 4294967295;
pub const CRC_DAT16: u32 = 4294967295;
pub const CRC_DAT17: u32 = 4294967295;
pub const CRC_DAT18: u32 = 4294967295;
pub const CRC_DAT19: u32 = 4294967295;
pub const CRC_DAT20: u32 = 4294967295;
pub const CRC_DAT21: u32 = 4294967295;
pub const CRC_DAT22: u32 = 4294967295;
pub const CRC_DAT23: u32 = 4294967295;
pub const CRC_DAT24: u32 = 4294967295;
pub const CRC_DAT25: u32 = 4294967295;
pub const CRC_DAT26: u32 = 4294967295;
pub const CRC_DAT27: u32 = 4294967295;
pub const CRC_DAT28: u32 = 4294967295;
pub const CRC_DAT29: u32 = 4294967295;
pub const CRC_DAT30: u32 = 4294967295;
pub const CRC_DAT31: u32 = 4294967295;
pub const DBGC_MCUDBGSTAT_CDBGPWRUPREQ_POS: u32 = 0;
pub const DBGC_MCUDBGSTAT_CDBGPWRUPREQ: u32 = 1;
pub const DBGC_MCUDBGSTAT_CDBGPWRUPACK_POS: u32 = 1;
pub const DBGC_MCUDBGSTAT_CDBGPWRUPACK: u32 = 2;
pub const DBGC_MCUSTPCTL_SWDTSTP_POS: u32 = 0;
pub const DBGC_MCUSTPCTL_SWDTSTP: u32 = 1;
pub const DBGC_MCUSTPCTL_WDTSTP_POS: u32 = 1;
pub const DBGC_MCUSTPCTL_WDTSTP: u32 = 2;
pub const DBGC_MCUSTPCTL_RTCSTP_POS: u32 = 2;
pub const DBGC_MCUSTPCTL_RTCSTP: u32 = 4;
pub const DBGC_MCUSTPCTL_TMR01STP_POS: u32 = 14;
pub const DBGC_MCUSTPCTL_TMR01STP: u32 = 16384;
pub const DBGC_MCUSTPCTL_TMR02STP_POS: u32 = 15;
pub const DBGC_MCUSTPCTL_TMR02STP: u32 = 32768;
pub const DBGC_MCUSTPCTL_TMR41STP_POS: u32 = 20;
pub const DBGC_MCUSTPCTL_TMR41STP: u32 = 1048576;
pub const DBGC_MCUSTPCTL_TMR42STP_POS: u32 = 21;
pub const DBGC_MCUSTPCTL_TMR42STP: u32 = 2097152;
pub const DBGC_MCUSTPCTL_TMR43STP_POS: u32 = 22;
pub const DBGC_MCUSTPCTL_TMR43STP: u32 = 4194304;
pub const DBGC_MCUSTPCTL_TM61STP_POS: u32 = 23;
pub const DBGC_MCUSTPCTL_TM61STP: u32 = 8388608;
pub const DBGC_MCUSTPCTL_TM62STP_POS: u32 = 24;
pub const DBGC_MCUSTPCTL_TM62STP: u32 = 16777216;
pub const DBGC_MCUSTPCTL_TMR63STP_POS: u32 = 25;
pub const DBGC_MCUSTPCTL_TMR63STP: u32 = 33554432;
pub const DBGC_MCUSTPCTL_TMRA1STP_POS: u32 = 26;
pub const DBGC_MCUSTPCTL_TMRA1STP: u32 = 67108864;
pub const DBGC_MCUSTPCTL_TMRA2STP_POS: u32 = 27;
pub const DBGC_MCUSTPCTL_TMRA2STP: u32 = 134217728;
pub const DBGC_MCUSTPCTL_TMRA3STP_POS: u32 = 28;
pub const DBGC_MCUSTPCTL_TMRA3STP: u32 = 268435456;
pub const DBGC_MCUSTPCTL_TMRA4STP_POS: u32 = 29;
pub const DBGC_MCUSTPCTL_TMRA4STP: u32 = 536870912;
pub const DBGC_MCUSTPCTL_TMRA5STP_POS: u32 = 30;
pub const DBGC_MCUSTPCTL_TMRA5STP: u32 = 1073741824;
pub const DBGC_MCUSTPCTL_TMRA6STP_POS: u32 = 31;
pub const DBGC_MCUSTPCTL_TMRA6STP: u32 = 2147483648;
pub const DBGC_MCUTRACECTL_TRACEMODE_POS: u32 = 0;
pub const DBGC_MCUTRACECTL_TRACEMODE: u32 = 3;
pub const DBGC_MCUTRACECTL_TRACEMODE_0: u32 = 1;
pub const DBGC_MCUTRACECTL_TRACEMODE_1: u32 = 2;
pub const DBGC_MCUTRACECTL_TRACEIOEN_POS: u32 = 2;
pub const DBGC_MCUTRACECTL_TRACEIOEN: u32 = 4;
pub const DCU_CTL_MODE_POS: u32 = 0;
pub const DCU_CTL_MODE: u32 = 7;
pub const DCU_CTL_DATASIZE_POS: u32 = 3;
pub const DCU_CTL_DATASIZE: u32 = 24;
pub const DCU_CTL_DATASIZE_0: u32 = 8;
pub const DCU_CTL_DATASIZE_1: u32 = 16;
pub const DCU_CTL_COMPTRG_POS: u32 = 8;
pub const DCU_CTL_COMPTRG: u32 = 256;
pub const DCU_CTL_INTEN_POS: u32 = 31;
pub const DCU_CTL_INTEN: u32 = 2147483648;
pub const DCU_FLAG_FLAG_OP_POS: u32 = 0;
pub const DCU_FLAG_FLAG_OP: u32 = 1;
pub const DCU_FLAG_FLAG_LS2_POS: u32 = 1;
pub const DCU_FLAG_FLAG_LS2: u32 = 2;
pub const DCU_FLAG_FLAG_EQ2_POS: u32 = 2;
pub const DCU_FLAG_FLAG_EQ2: u32 = 4;
pub const DCU_FLAG_FLAG_GT2_POS: u32 = 3;
pub const DCU_FLAG_FLAG_GT2: u32 = 8;
pub const DCU_FLAG_FLAG_LS1_POS: u32 = 4;
pub const DCU_FLAG_FLAG_LS1: u32 = 16;
pub const DCU_FLAG_FLAG_EQ1_POS: u32 = 5;
pub const DCU_FLAG_FLAG_EQ1: u32 = 32;
pub const DCU_FLAG_FLAG_GT1_POS: u32 = 6;
pub const DCU_FLAG_FLAG_GT1: u32 = 64;
pub const DCU_DATA0: u32 = 4294967295;
pub const DCU_DATA1: u32 = 4294967295;
pub const DCU_DATA2: u32 = 4294967295;
pub const DCU_FLAGCLR_CLR_OP_POS: u32 = 0;
pub const DCU_FLAGCLR_CLR_OP: u32 = 1;
pub const DCU_FLAGCLR_CLR_LS2_POS: u32 = 1;
pub const DCU_FLAGCLR_CLR_LS2: u32 = 2;
pub const DCU_FLAGCLR_CLR_EQ2_POS: u32 = 2;
pub const DCU_FLAGCLR_CLR_EQ2: u32 = 4;
pub const DCU_FLAGCLR_CLR_GT2_POS: u32 = 3;
pub const DCU_FLAGCLR_CLR_GT2: u32 = 8;
pub const DCU_FLAGCLR_CLR_LS1_POS: u32 = 4;
pub const DCU_FLAGCLR_CLR_LS1: u32 = 16;
pub const DCU_FLAGCLR_CLR_EQ1_POS: u32 = 5;
pub const DCU_FLAGCLR_CLR_EQ1: u32 = 32;
pub const DCU_FLAGCLR_CLR_GT1_POS: u32 = 6;
pub const DCU_FLAGCLR_CLR_GT1: u32 = 64;
pub const DCU_INTEVTSEL_SEL_OP_POS: u32 = 0;
pub const DCU_INTEVTSEL_SEL_OP: u32 = 1;
pub const DCU_INTEVTSEL_SEL_LS2_POS: u32 = 1;
pub const DCU_INTEVTSEL_SEL_LS2: u32 = 2;
pub const DCU_INTEVTSEL_SEL_EQ2_POS: u32 = 2;
pub const DCU_INTEVTSEL_SEL_EQ2: u32 = 4;
pub const DCU_INTEVTSEL_SEL_GT2_POS: u32 = 3;
pub const DCU_INTEVTSEL_SEL_GT2: u32 = 8;
pub const DCU_INTEVTSEL_SEL_LS1_POS: u32 = 4;
pub const DCU_INTEVTSEL_SEL_LS1: u32 = 16;
pub const DCU_INTEVTSEL_SEL_EQ1_POS: u32 = 5;
pub const DCU_INTEVTSEL_SEL_EQ1: u32 = 32;
pub const DCU_INTEVTSEL_SEL_GT1_POS: u32 = 6;
pub const DCU_INTEVTSEL_SEL_GT1: u32 = 64;
pub const DCU_INTEVTSEL_SEL_WIN_POS: u32 = 7;
pub const DCU_INTEVTSEL_SEL_WIN: u32 = 384;
pub const DCU_INTEVTSEL_SEL_WIN_0: u32 = 128;
pub const DCU_INTEVTSEL_SEL_WIN_1: u32 = 256;
pub const DMA_EN_EN: u32 = 1;
pub const DMA_INTSTAT0_TRNERR_POS: u32 = 0;
pub const DMA_INTSTAT0_TRNERR: u32 = 15;
pub const DMA_INTSTAT0_TRNERR_0: u32 = 1;
pub const DMA_INTSTAT0_TRNERR_1: u32 = 2;
pub const DMA_INTSTAT0_TRNERR_2: u32 = 4;
pub const DMA_INTSTAT0_TRNERR_3: u32 = 8;
pub const DMA_INTSTAT0_REQERR_POS: u32 = 16;
pub const DMA_INTSTAT0_REQERR: u32 = 983040;
pub const DMA_INTSTAT0_REQERR_0: u32 = 65536;
pub const DMA_INTSTAT0_REQERR_1: u32 = 131072;
pub const DMA_INTSTAT0_REQERR_2: u32 = 262144;
pub const DMA_INTSTAT0_REQERR_3: u32 = 524288;
pub const DMA_INTSTAT1_TC_POS: u32 = 0;
pub const DMA_INTSTAT1_TC: u32 = 15;
pub const DMA_INTSTAT1_TC_0: u32 = 1;
pub const DMA_INTSTAT1_TC_1: u32 = 2;
pub const DMA_INTSTAT1_TC_2: u32 = 4;
pub const DMA_INTSTAT1_TC_3: u32 = 8;
pub const DMA_INTSTAT1_BTC_POS: u32 = 16;
pub const DMA_INTSTAT1_BTC: u32 = 983040;
pub const DMA_INTSTAT1_BTC_0: u32 = 65536;
pub const DMA_INTSTAT1_BTC_1: u32 = 131072;
pub const DMA_INTSTAT1_BTC_2: u32 = 262144;
pub const DMA_INTSTAT1_BTC_3: u32 = 524288;
pub const DMA_INTMASK0_MSKTRNERR_POS: u32 = 0;
pub const DMA_INTMASK0_MSKTRNERR: u32 = 15;
pub const DMA_INTMASK0_MSKTRNERR_0: u32 = 1;
pub const DMA_INTMASK0_MSKTRNERR_1: u32 = 2;
pub const DMA_INTMASK0_MSKTRNERR_2: u32 = 4;
pub const DMA_INTMASK0_MSKTRNERR_3: u32 = 8;
pub const DMA_INTMASK0_MSKREQERR_POS: u32 = 16;
pub const DMA_INTMASK0_MSKREQERR: u32 = 983040;
pub const DMA_INTMASK0_MSKREQERR_0: u32 = 65536;
pub const DMA_INTMASK0_MSKREQERR_1: u32 = 131072;
pub const DMA_INTMASK0_MSKREQERR_2: u32 = 262144;
pub const DMA_INTMASK0_MSKREQERR_3: u32 = 524288;
pub const DMA_INTMASK1_MSKTC_POS: u32 = 0;
pub const DMA_INTMASK1_MSKTC: u32 = 15;
pub const DMA_INTMASK1_MSKTC_0: u32 = 1;
pub const DMA_INTMASK1_MSKTC_1: u32 = 2;
pub const DMA_INTMASK1_MSKTC_2: u32 = 4;
pub const DMA_INTMASK1_MSKTC_3: u32 = 8;
pub const DMA_INTMASK1_MSKBTC_POS: u32 = 16;
pub const DMA_INTMASK1_MSKBTC: u32 = 983040;
pub const DMA_INTMASK1_MSKBTC_0: u32 = 65536;
pub const DMA_INTMASK1_MSKBTC_1: u32 = 131072;
pub const DMA_INTMASK1_MSKBTC_2: u32 = 262144;
pub const DMA_INTMASK1_MSKBTC_3: u32 = 524288;
pub const DMA_INTCLR0_CLRTRNERR_POS: u32 = 0;
pub const DMA_INTCLR0_CLRTRNERR: u32 = 15;
pub const DMA_INTCLR0_CLRTRNERR_0: u32 = 1;
pub const DMA_INTCLR0_CLRTRNERR_1: u32 = 2;
pub const DMA_INTCLR0_CLRTRNERR_2: u32 = 4;
pub const DMA_INTCLR0_CLRTRNERR_3: u32 = 8;
pub const DMA_INTCLR0_CLRREQERR_POS: u32 = 16;
pub const DMA_INTCLR0_CLRREQERR: u32 = 983040;
pub const DMA_INTCLR0_CLRREQERR_0: u32 = 65536;
pub const DMA_INTCLR0_CLRREQERR_1: u32 = 131072;
pub const DMA_INTCLR0_CLRREQERR_2: u32 = 262144;
pub const DMA_INTCLR0_CLRREQERR_3: u32 = 524288;
pub const DMA_INTCLR1_CLRTC_POS: u32 = 0;
pub const DMA_INTCLR1_CLRTC: u32 = 15;
pub const DMA_INTCLR1_CLRTC_0: u32 = 1;
pub const DMA_INTCLR1_CLRTC_1: u32 = 2;
pub const DMA_INTCLR1_CLRTC_2: u32 = 4;
pub const DMA_INTCLR1_CLRTC_3: u32 = 8;
pub const DMA_INTCLR1_CLRBTC_POS: u32 = 16;
pub const DMA_INTCLR1_CLRBTC: u32 = 983040;
pub const DMA_INTCLR1_CLRBTC_0: u32 = 65536;
pub const DMA_INTCLR1_CLRBTC_1: u32 = 131072;
pub const DMA_INTCLR1_CLRBTC_2: u32 = 262144;
pub const DMA_INTCLR1_CLRBTC_3: u32 = 524288;
pub const DMA_CHEN_CHEN: u32 = 15;
pub const DMA_CHEN_CHEN_0: u32 = 1;
pub const DMA_CHEN_CHEN_1: u32 = 2;
pub const DMA_CHEN_CHEN_2: u32 = 4;
pub const DMA_CHEN_CHEN_3: u32 = 8;
pub const DMA_REQSTAT_CHREQ_POS: u32 = 0;
pub const DMA_REQSTAT_CHREQ: u32 = 15;
pub const DMA_REQSTAT_CHREQ_0: u32 = 1;
pub const DMA_REQSTAT_CHREQ_1: u32 = 2;
pub const DMA_REQSTAT_CHREQ_2: u32 = 4;
pub const DMA_REQSTAT_CHREQ_3: u32 = 8;
pub const DMA_REQSTAT_RCFGREQ_POS: u32 = 15;
pub const DMA_REQSTAT_RCFGREQ: u32 = 32768;
pub const DMA_CHSTAT_DMAACT_POS: u32 = 0;
pub const DMA_CHSTAT_DMAACT: u32 = 1;
pub const DMA_CHSTAT_RCFGACT_POS: u32 = 1;
pub const DMA_CHSTAT_RCFGACT: u32 = 2;
pub const DMA_CHSTAT_CHACT_POS: u32 = 16;
pub const DMA_CHSTAT_CHACT: u32 = 983040;
pub const DMA_CHSTAT_CHACT_0: u32 = 65536;
pub const DMA_CHSTAT_CHACT_1: u32 = 131072;
pub const DMA_CHSTAT_CHACT_2: u32 = 262144;
pub const DMA_CHSTAT_CHACT_3: u32 = 524288;
pub const DMA_RCFGCTL_RCFGEN_POS: u32 = 0;
pub const DMA_RCFGCTL_RCFGEN: u32 = 1;
pub const DMA_RCFGCTL_RCFGLLP_POS: u32 = 1;
pub const DMA_RCFGCTL_RCFGLLP: u32 = 2;
pub const DMA_RCFGCTL_RCFGCHS_POS: u32 = 8;
pub const DMA_RCFGCTL_RCFGCHS: u32 = 3840;
pub const DMA_RCFGCTL_RCFGCHS_0: u32 = 256;
pub const DMA_RCFGCTL_RCFGCHS_1: u32 = 512;
pub const DMA_RCFGCTL_RCFGCHS_2: u32 = 1024;
pub const DMA_RCFGCTL_RCFGCHS_3: u32 = 2048;
pub const DMA_RCFGCTL_SARMD_POS: u32 = 16;
pub const DMA_RCFGCTL_SARMD: u32 = 196608;
pub const DMA_RCFGCTL_SARMD_0: u32 = 65536;
pub const DMA_RCFGCTL_SARMD_1: u32 = 131072;
pub const DMA_RCFGCTL_DARMD_POS: u32 = 18;
pub const DMA_RCFGCTL_DARMD: u32 = 786432;
pub const DMA_RCFGCTL_DARMD_0: u32 = 262144;
pub const DMA_RCFGCTL_DARMD_1: u32 = 524288;
pub const DMA_RCFGCTL_CNTMD_POS: u32 = 20;
pub const DMA_RCFGCTL_CNTMD: u32 = 3145728;
pub const DMA_RCFGCTL_CNTMD_0: u32 = 1048576;
pub const DMA_RCFGCTL_CNTMD_1: u32 = 2097152;
pub const DMA_SWREQ_SWREQ_POS: u32 = 0;
pub const DMA_SWREQ_SWREQ: u32 = 255;
pub const DMA_SWREQ_SWREQ_0: u32 = 1;
pub const DMA_SWREQ_SWREQ_1: u32 = 2;
pub const DMA_SWREQ_SWREQ_2: u32 = 4;
pub const DMA_SWREQ_SWREQ_3: u32 = 8;
pub const DMA_SWREQ_SWREQ_4: u32 = 16;
pub const DMA_SWREQ_SWREQ_5: u32 = 32;
pub const DMA_SWREQ_SWREQ_6: u32 = 64;
pub const DMA_SWREQ_SWREQ_7: u32 = 128;
pub const DMA_SWREQ_SWRCFGREQ_POS: u32 = 15;
pub const DMA_SWREQ_SWRCFGREQ: u32 = 32768;
pub const DMA_SWREQ_SWREQWP_POS: u32 = 16;
pub const DMA_SWREQ_SWREQWP: u32 = 16711680;
pub const DMA_SWREQ_SWRCFGWP_POS: u32 = 24;
pub const DMA_SWREQ_SWRCFGWP: u32 = 4278190080;
pub const DMA_SAR: u32 = 4294967295;
pub const DMA_DAR: u32 = 4294967295;
pub const DMA_DTCTL_BLKSIZE_POS: u32 = 0;
pub const DMA_DTCTL_BLKSIZE: u32 = 1023;
pub const DMA_DTCTL_CNT_POS: u32 = 16;
pub const DMA_DTCTL_CNT: u32 = 4294901760;
pub const DMA_RPT_SRPT_POS: u32 = 0;
pub const DMA_RPT_SRPT: u32 = 1023;
pub const DMA_RPT_DRPT_POS: u32 = 16;
pub const DMA_RPT_DRPT: u32 = 67043328;
pub const DMA_RPTB_SRPTB_POS: u32 = 0;
pub const DMA_RPTB_SRPTB: u32 = 1023;
pub const DMA_RPTB_DRPTB_POS: u32 = 16;
pub const DMA_RPTB_DRPTB: u32 = 67043328;
pub const DMA_SNSEQCTL_SOFFSET_POS: u32 = 0;
pub const DMA_SNSEQCTL_SOFFSET: u32 = 1048575;
pub const DMA_SNSEQCTL_SNSCNT_POS: u32 = 20;
pub const DMA_SNSEQCTL_SNSCNT: u32 = 4293918720;
pub const DMA_SNSEQCTLB_SNSDIST_POS: u32 = 0;
pub const DMA_SNSEQCTLB_SNSDIST: u32 = 1048575;
pub const DMA_SNSEQCTLB_SNSCNTB_POS: u32 = 20;
pub const DMA_SNSEQCTLB_SNSCNTB: u32 = 4293918720;
pub const DMA_DNSEQCTL_DOFFSET_POS: u32 = 0;
pub const DMA_DNSEQCTL_DOFFSET: u32 = 1048575;
pub const DMA_DNSEQCTL_DNSCNT_POS: u32 = 20;
pub const DMA_DNSEQCTL_DNSCNT: u32 = 4293918720;
pub const DMA_DNSEQCTLB_DNSDIST_POS: u32 = 0;
pub const DMA_DNSEQCTLB_DNSDIST: u32 = 1048575;
pub const DMA_DNSEQCTLB_DNSCNTB_POS: u32 = 20;
pub const DMA_DNSEQCTLB_DNSCNTB: u32 = 4293918720;
pub const DMA_LLP_LLP_POS: u32 = 2;
pub const DMA_LLP_LLP: u32 = 4294967292;
pub const DMA_CHCTL_SINC_POS: u32 = 0;
pub const DMA_CHCTL_SINC: u32 = 3;
pub const DMA_CHCTL_SINC_0: u32 = 1;
pub const DMA_CHCTL_SINC_1: u32 = 2;
pub const DMA_CHCTL_DINC_POS: u32 = 2;
pub const DMA_CHCTL_DINC: u32 = 12;
pub const DMA_CHCTL_DINC_0: u32 = 4;
pub const DMA_CHCTL_DINC_1: u32 = 8;
pub const DMA_CHCTL_SRPTEN_POS: u32 = 4;
pub const DMA_CHCTL_SRPTEN: u32 = 16;
pub const DMA_CHCTL_DRPTEN_POS: u32 = 5;
pub const DMA_CHCTL_DRPTEN: u32 = 32;
pub const DMA_CHCTL_SNSEQEN_POS: u32 = 6;
pub const DMA_CHCTL_SNSEQEN: u32 = 64;
pub const DMA_CHCTL_DNSEQEN_POS: u32 = 7;
pub const DMA_CHCTL_DNSEQEN: u32 = 128;
pub const DMA_CHCTL_HSIZE_POS: u32 = 8;
pub const DMA_CHCTL_HSIZE: u32 = 768;
pub const DMA_CHCTL_HSIZE_0: u32 = 256;
pub const DMA_CHCTL_HSIZE_1: u32 = 512;
pub const DMA_CHCTL_LLPEN_POS: u32 = 10;
pub const DMA_CHCTL_LLPEN: u32 = 1024;
pub const DMA_CHCTL_LLPRUN_POS: u32 = 11;
pub const DMA_CHCTL_LLPRUN: u32 = 2048;
pub const DMA_CHCTL_IE_POS: u32 = 12;
pub const DMA_CHCTL_IE: u32 = 4096;
pub const DMA_MONSAR: u32 = 4294967295;
pub const DMA_MONDAR: u32 = 4294967295;
pub const DMA_MONDTCTL_BLKSIZE_POS: u32 = 0;
pub const DMA_MONDTCTL_BLKSIZE: u32 = 1023;
pub const DMA_MONDTCTL_CNT_POS: u32 = 16;
pub const DMA_MONDTCTL_CNT: u32 = 4294901760;
pub const DMA_MONRPT_SRPT_POS: u32 = 0;
pub const DMA_MONRPT_SRPT: u32 = 1023;
pub const DMA_MONRPT_DRPT_POS: u32 = 16;
pub const DMA_MONRPT_DRPT: u32 = 67043328;
pub const DMA_MONSNSEQCTL_SOFFSET_POS: u32 = 0;
pub const DMA_MONSNSEQCTL_SOFFSET: u32 = 1048575;
pub const DMA_MONSNSEQCTL_SNSCNT_POS: u32 = 20;
pub const DMA_MONSNSEQCTL_SNSCNT: u32 = 4293918720;
pub const DMA_MONDNSEQCTL_DOFFSET_POS: u32 = 0;
pub const DMA_MONDNSEQCTL_DOFFSET: u32 = 1048575;
pub const DMA_MONDNSEQCTL_DNSCNT_POS: u32 = 20;
pub const DMA_MONDNSEQCTL_DNSCNT: u32 = 4293918720;
pub const EFM_FAPRT_FAPRT: u32 = 65535;
pub const EFM_FSTP_FSTP: u32 = 1;
pub const EFM_FRMC_SLPMD_POS: u32 = 0;
pub const EFM_FRMC_SLPMD: u32 = 1;
pub const EFM_FRMC_FLWT_POS: u32 = 4;
pub const EFM_FRMC_FLWT: u32 = 240;
pub const EFM_FRMC_LVM_POS: u32 = 8;
pub const EFM_FRMC_LVM: u32 = 256;
pub const EFM_FRMC_CACHE_POS: u32 = 16;
pub const EFM_FRMC_CACHE: u32 = 65536;
pub const EFM_FRMC_CRST_POS: u32 = 24;
pub const EFM_FRMC_CRST: u32 = 16777216;
pub const EFM_FWMC_PEMODE_POS: u32 = 0;
pub const EFM_FWMC_PEMODE: u32 = 1;
pub const EFM_FWMC_PEMOD_POS: u32 = 4;
pub const EFM_FWMC_PEMOD: u32 = 112;
pub const EFM_FWMC_BUSHLDCTL_POS: u32 = 8;
pub const EFM_FWMC_BUSHLDCTL: u32 = 256;
pub const EFM_FSR_PEWERR_POS: u32 = 0;
pub const EFM_FSR_PEWERR: u32 = 1;
pub const EFM_FSR_PEPRTERR_POS: u32 = 1;
pub const EFM_FSR_PEPRTERR: u32 = 2;
pub const EFM_FSR_PGSZERR_POS: u32 = 2;
pub const EFM_FSR_PGSZERR: u32 = 4;
pub const EFM_FSR_PGMISMTCH_POS: u32 = 3;
pub const EFM_FSR_PGMISMTCH: u32 = 8;
pub const EFM_FSR_OPTEND_POS: u32 = 4;
pub const EFM_FSR_OPTEND: u32 = 16;
pub const EFM_FSR_COLERR_POS: u32 = 5;
pub const EFM_FSR_COLERR: u32 = 32;
pub const EFM_FSR_RDY_POS: u32 = 8;
pub const EFM_FSR_RDY: u32 = 256;
pub const EFM_FSCLR_PEWERRCLR_POS: u32 = 0;
pub const EFM_FSCLR_PEWERRCLR: u32 = 1;
pub const EFM_FSCLR_PEPRTERRCLR_POS: u32 = 1;
pub const EFM_FSCLR_PEPRTERRCLR: u32 = 2;
pub const EFM_FSCLR_PGSZERRCLR_POS: u32 = 2;
pub const EFM_FSCLR_PGSZERRCLR: u32 = 4;
pub const EFM_FSCLR_PGMISMTCHCLR_POS: u32 = 3;
pub const EFM_FSCLR_PGMISMTCHCLR: u32 = 8;
pub const EFM_FSCLR_OPTENDCLR_POS: u32 = 4;
pub const EFM_FSCLR_OPTENDCLR: u32 = 16;
pub const EFM_FSCLR_COLERRCLR_POS: u32 = 5;
pub const EFM_FSCLR_COLERRCLR: u32 = 32;
pub const EFM_FITE_PEERRITE_POS: u32 = 0;
pub const EFM_FITE_PEERRITE: u32 = 1;
pub const EFM_FITE_OPTENDITE_POS: u32 = 1;
pub const EFM_FITE_OPTENDITE: u32 = 2;
pub const EFM_FITE_COLERRITE_POS: u32 = 2;
pub const EFM_FITE_COLERRITE: u32 = 4;
pub const EFM_FSWP_FSWP: u32 = 1;
pub const EFM_FPMTSW_FPMTSW: u32 = 524287;
pub const EFM_FPMTEW_FPMTEW: u32 = 524287;
pub const EFM_UQID0: u32 = 4294967295;
pub const EFM_UQID1: u32 = 4294967295;
pub const EFM_UQID2: u32 = 4294967295;
pub const EFM_MMF_REMPRT_REMPRT: u32 = 65535;
pub const EFM_MMF_REMCR_RMSIZE_POS: u32 = 0;
pub const EFM_MMF_REMCR_RMSIZE: u32 = 31;
pub const EFM_MMF_REMCR_RMTADDR_POS: u32 = 12;
pub const EFM_MMF_REMCR_RMTADDR: u32 = 536866816;
pub const EFM_MMF_REMCR_EN_POS: u32 = 31;
pub const EFM_MMF_REMCR_EN: u32 = 2147483648;
pub const EMB_CTL_PORTINEN_POS: u32 = 0;
pub const EMB_CTL_PORTINEN: u32 = 1;
pub const EMB_CTL_CMPEN1_POS: u32 = 1;
pub const EMB_CTL_CMPEN1: u32 = 2;
pub const EMB_CTL_CMPEN2_POS: u32 = 2;
pub const EMB_CTL_CMPEN2: u32 = 4;
pub const EMB_CTL_CMPEN3_POS: u32 = 3;
pub const EMB_CTL_CMPEN3: u32 = 8;
pub const EMB_CTL_OSCSTPEN_POS: u32 = 5;
pub const EMB_CTL_OSCSTPEN: u32 = 32;
pub const EMB_CTL_PWMSEN0_POS: u32 = 6;
pub const EMB_CTL_PWMSEN0: u32 = 64;
pub const EMB_CTL_PWMSEN1_POS: u32 = 7;
pub const EMB_CTL_PWMSEN1: u32 = 128;
pub const EMB_CTL_PWMSEN2_POS: u32 = 8;
pub const EMB_CTL_PWMSEN2: u32 = 256;
pub const EMB_CTL_NFSEL_POS: u32 = 28;
pub const EMB_CTL_NFSEL: u32 = 805306368;
pub const EMB_CTL_NFEN_POS: u32 = 30;
pub const EMB_CTL_NFEN: u32 = 1073741824;
pub const EMB_CTL_INVSEL_POS: u32 = 31;
pub const EMB_CTL_INVSEL: u32 = 2147483648;
pub const EMB_PWMLV_PWMLV0_POS: u32 = 0;
pub const EMB_PWMLV_PWMLV0: u32 = 1;
pub const EMB_PWMLV_PWMLV1_POS: u32 = 1;
pub const EMB_PWMLV_PWMLV1: u32 = 2;
pub const EMB_PWMLV_PWMLV2_POS: u32 = 2;
pub const EMB_PWMLV_PWMLV2: u32 = 4;
pub const EMB_SOE_SOE: u32 = 1;
pub const EMB_STAT_PORTINF_POS: u32 = 0;
pub const EMB_STAT_PORTINF: u32 = 1;
pub const EMB_STAT_PWMSF_POS: u32 = 1;
pub const EMB_STAT_PWMSF: u32 = 2;
pub const EMB_STAT_CMPF_POS: u32 = 2;
pub const EMB_STAT_CMPF: u32 = 4;
pub const EMB_STAT_OSF_POS: u32 = 3;
pub const EMB_STAT_OSF: u32 = 8;
pub const EMB_STAT_PORTINST_POS: u32 = 4;
pub const EMB_STAT_PORTINST: u32 = 16;
pub const EMB_STAT_PWMST_POS: u32 = 5;
pub const EMB_STAT_PWMST: u32 = 32;
pub const EMB_STATCLR_PORTINFCLR_POS: u32 = 0;
pub const EMB_STATCLR_PORTINFCLR: u32 = 1;
pub const EMB_STATCLR_PWMSFCLR_POS: u32 = 1;
pub const EMB_STATCLR_PWMSFCLR: u32 = 2;
pub const EMB_STATCLR_CMPFCLR_POS: u32 = 2;
pub const EMB_STATCLR_CMPFCLR: u32 = 4;
pub const EMB_STATCLR_OSFCLR_POS: u32 = 3;
pub const EMB_STATCLR_OSFCLR: u32 = 8;
pub const EMB_INTEN_PORTININTEN_POS: u32 = 0;
pub const EMB_INTEN_PORTININTEN: u32 = 1;
pub const EMB_INTEN_PWMSINTEN_POS: u32 = 1;
pub const EMB_INTEN_PWMSINTEN: u32 = 2;
pub const EMB_INTEN_CMPINTEN_POS: u32 = 2;
pub const EMB_INTEN_CMPINTEN: u32 = 4;
pub const EMB_INTEN_OSINTEN_POS: u32 = 3;
pub const EMB_INTEN_OSINTEN: u32 = 8;
pub const FCM_LVR_LVR: u32 = 65535;
pub const FCM_UVR_UVR: u32 = 65535;
pub const FCM_CNTR_CNTR: u32 = 65535;
pub const FCM_STR_START: u32 = 1;
pub const FCM_MCCR_MDIVS_POS: u32 = 0;
pub const FCM_MCCR_MDIVS: u32 = 3;
pub const FCM_MCCR_MDIVS_0: u32 = 1;
pub const FCM_MCCR_MDIVS_1: u32 = 2;
pub const FCM_MCCR_MCKS_POS: u32 = 4;
pub const FCM_MCCR_MCKS: u32 = 240;
pub const FCM_RCCR_RDIVS_POS: u32 = 0;
pub const FCM_RCCR_RDIVS: u32 = 3;
pub const FCM_RCCR_RDIVS_0: u32 = 1;
pub const FCM_RCCR_RDIVS_1: u32 = 2;
pub const FCM_RCCR_RCKS_POS: u32 = 3;
pub const FCM_RCCR_RCKS: u32 = 120;
pub const FCM_RCCR_INEXS_POS: u32 = 7;
pub const FCM_RCCR_INEXS: u32 = 128;
pub const FCM_RCCR_DNFS_POS: u32 = 8;
pub const FCM_RCCR_DNFS: u32 = 768;
pub const FCM_RCCR_DNFS_0: u32 = 256;
pub const FCM_RCCR_DNFS_1: u32 = 512;
pub const FCM_RCCR_EDGES_POS: u32 = 12;
pub const FCM_RCCR_EDGES: u32 = 12288;
pub const FCM_RCCR_EDGES_0: u32 = 4096;
pub const FCM_RCCR_EDGES_1: u32 = 8192;
pub const FCM_RCCR_EXREFE_POS: u32 = 15;
pub const FCM_RCCR_EXREFE: u32 = 32768;
pub const FCM_RIER_ERRIE_POS: u32 = 0;
pub const FCM_RIER_ERRIE: u32 = 1;
pub const FCM_RIER_MENDIE_POS: u32 = 1;
pub const FCM_RIER_MENDIE: u32 = 2;
pub const FCM_RIER_OVFIE_POS: u32 = 2;
pub const FCM_RIER_OVFIE: u32 = 4;
pub const FCM_RIER_ERRINTRS_POS: u32 = 4;
pub const FCM_RIER_ERRINTRS: u32 = 16;
pub const FCM_RIER_ERRE_POS: u32 = 7;
pub const FCM_RIER_ERRE: u32 = 128;
pub const FCM_SR_ERRF_POS: u32 = 0;
pub const FCM_SR_ERRF: u32 = 1;
pub const FCM_SR_MENDF_POS: u32 = 1;
pub const FCM_SR_MENDF: u32 = 2;
pub const FCM_SR_OVF_POS: u32 = 2;
pub const FCM_SR_OVF: u32 = 4;
pub const FCM_CLR_ERRFCLR_POS: u32 = 0;
pub const FCM_CLR_ERRFCLR: u32 = 1;
pub const FCM_CLR_MENDFCLR_POS: u32 = 1;
pub const FCM_CLR_MENDFCLR: u32 = 2;
pub const FCM_CLR_OVFCLR_POS: u32 = 2;
pub const FCM_CLR_OVFCLR: u32 = 4;
pub const GPIO_PIDR_PIN00_POS: u32 = 0;
pub const GPIO_PIDR_PIN00: u32 = 1;
pub const GPIO_PIDR_PIN01_POS: u32 = 1;
pub const GPIO_PIDR_PIN01: u32 = 2;
pub const GPIO_PIDR_PIN02_POS: u32 = 2;
pub const GPIO_PIDR_PIN02: u32 = 4;
pub const GPIO_PIDR_PIN03_POS: u32 = 3;
pub const GPIO_PIDR_PIN03: u32 = 8;
pub const GPIO_PIDR_PIN04_POS: u32 = 4;
pub const GPIO_PIDR_PIN04: u32 = 16;
pub const GPIO_PIDR_PIN05_POS: u32 = 5;
pub const GPIO_PIDR_PIN05: u32 = 32;
pub const GPIO_PIDR_PIN06_POS: u32 = 6;
pub const GPIO_PIDR_PIN06: u32 = 64;
pub const GPIO_PIDR_PIN07_POS: u32 = 7;
pub const GPIO_PIDR_PIN07: u32 = 128;
pub const GPIO_PIDR_PIN08_POS: u32 = 8;
pub const GPIO_PIDR_PIN08: u32 = 256;
pub const GPIO_PIDR_PIN09_POS: u32 = 9;
pub const GPIO_PIDR_PIN09: u32 = 512;
pub const GPIO_PIDR_PIN10_POS: u32 = 10;
pub const GPIO_PIDR_PIN10: u32 = 1024;
pub const GPIO_PIDR_PIN11_POS: u32 = 11;
pub const GPIO_PIDR_PIN11: u32 = 2048;
pub const GPIO_PIDR_PIN12_POS: u32 = 12;
pub const GPIO_PIDR_PIN12: u32 = 4096;
pub const GPIO_PIDR_PIN13_POS: u32 = 13;
pub const GPIO_PIDR_PIN13: u32 = 8192;
pub const GPIO_PIDR_PIN14_POS: u32 = 14;
pub const GPIO_PIDR_PIN14: u32 = 16384;
pub const GPIO_PIDR_PIN15_POS: u32 = 15;
pub const GPIO_PIDR_PIN15: u32 = 32768;
pub const GPIO_PODR_POUT00_POS: u32 = 0;
pub const GPIO_PODR_POUT00: u32 = 1;
pub const GPIO_PODR_POUT01_POS: u32 = 1;
pub const GPIO_PODR_POUT01: u32 = 2;
pub const GPIO_PODR_POUT02_POS: u32 = 2;
pub const GPIO_PODR_POUT02: u32 = 4;
pub const GPIO_PODR_POUT03_POS: u32 = 3;
pub const GPIO_PODR_POUT03: u32 = 8;
pub const GPIO_PODR_POUT04_POS: u32 = 4;
pub const GPIO_PODR_POUT04: u32 = 16;
pub const GPIO_PODR_POUT05_POS: u32 = 5;
pub const GPIO_PODR_POUT05: u32 = 32;
pub const GPIO_PODR_POUT06_POS: u32 = 6;
pub const GPIO_PODR_POUT06: u32 = 64;
pub const GPIO_PODR_POUT07_POS: u32 = 7;
pub const GPIO_PODR_POUT07: u32 = 128;
pub const GPIO_PODR_POUT08_POS: u32 = 8;
pub const GPIO_PODR_POUT08: u32 = 256;
pub const GPIO_PODR_POUT09_POS: u32 = 9;
pub const GPIO_PODR_POUT09: u32 = 512;
pub const GPIO_PODR_POUT10_POS: u32 = 10;
pub const GPIO_PODR_POUT10: u32 = 1024;
pub const GPIO_PODR_POUT11_POS: u32 = 11;
pub const GPIO_PODR_POUT11: u32 = 2048;
pub const GPIO_PODR_POUT12_POS: u32 = 12;
pub const GPIO_PODR_POUT12: u32 = 4096;
pub const GPIO_PODR_POUT13_POS: u32 = 13;
pub const GPIO_PODR_POUT13: u32 = 8192;
pub const GPIO_PODR_POUT14_POS: u32 = 14;
pub const GPIO_PODR_POUT14: u32 = 16384;
pub const GPIO_PODR_POUT15_POS: u32 = 15;
pub const GPIO_PODR_POUT15: u32 = 32768;
pub const GPIO_POER_POUTE00_POS: u32 = 0;
pub const GPIO_POER_POUTE00: u32 = 1;
pub const GPIO_POER_POUTE01_POS: u32 = 1;
pub const GPIO_POER_POUTE01: u32 = 2;
pub const GPIO_POER_POUTE02_POS: u32 = 2;
pub const GPIO_POER_POUTE02: u32 = 4;
pub const GPIO_POER_POUTE03_POS: u32 = 3;
pub const GPIO_POER_POUTE03: u32 = 8;
pub const GPIO_POER_POUTE04_POS: u32 = 4;
pub const GPIO_POER_POUTE04: u32 = 16;
pub const GPIO_POER_POUTE05_POS: u32 = 5;
pub const GPIO_POER_POUTE05: u32 = 32;
pub const GPIO_POER_POUTE06_POS: u32 = 6;
pub const GPIO_POER_POUTE06: u32 = 64;
pub const GPIO_POER_POUTE07_POS: u32 = 7;
pub const GPIO_POER_POUTE07: u32 = 128;
pub const GPIO_POER_POUTE08_POS: u32 = 8;
pub const GPIO_POER_POUTE08: u32 = 256;
pub const GPIO_POER_POUTE09_POS: u32 = 9;
pub const GPIO_POER_POUTE09: u32 = 512;
pub const GPIO_POER_POUTE10_POS: u32 = 10;
pub const GPIO_POER_POUTE10: u32 = 1024;
pub const GPIO_POER_POUTE11_POS: u32 = 11;
pub const GPIO_POER_POUTE11: u32 = 2048;
pub const GPIO_POER_POUTE12_POS: u32 = 12;
pub const GPIO_POER_POUTE12: u32 = 4096;
pub const GPIO_POER_POUTE13_POS: u32 = 13;
pub const GPIO_POER_POUTE13: u32 = 8192;
pub const GPIO_POER_POUTE14_POS: u32 = 14;
pub const GPIO_POER_POUTE14: u32 = 16384;
pub const GPIO_POER_POUTE15_POS: u32 = 15;
pub const GPIO_POER_POUTE15: u32 = 32768;
pub const GPIO_POSR_POS00_POS: u32 = 0;
pub const GPIO_POSR_POS00: u32 = 1;
pub const GPIO_POSR_POS01_POS: u32 = 1;
pub const GPIO_POSR_POS01: u32 = 2;
pub const GPIO_POSR_POS02_POS: u32 = 2;
pub const GPIO_POSR_POS02: u32 = 4;
pub const GPIO_POSR_POS03_POS: u32 = 3;
pub const GPIO_POSR_POS03: u32 = 8;
pub const GPIO_POSR_POS04_POS: u32 = 4;
pub const GPIO_POSR_POS04: u32 = 16;
pub const GPIO_POSR_POS05_POS: u32 = 5;
pub const GPIO_POSR_POS05: u32 = 32;
pub const GPIO_POSR_POS06_POS: u32 = 6;
pub const GPIO_POSR_POS06: u32 = 64;
pub const GPIO_POSR_POS07_POS: u32 = 7;
pub const GPIO_POSR_POS07: u32 = 128;
pub const GPIO_POSR_POS08_POS: u32 = 8;
pub const GPIO_POSR_POS08: u32 = 256;
pub const GPIO_POSR_POS09_POS: u32 = 9;
pub const GPIO_POSR_POS09: u32 = 512;
pub const GPIO_POSR_POS10_POS: u32 = 10;
pub const GPIO_POSR_POS10: u32 = 1024;
pub const GPIO_POSR_POS11_POS: u32 = 11;
pub const GPIO_POSR_POS11: u32 = 2048;
pub const GPIO_POSR_POS12_POS: u32 = 12;
pub const GPIO_POSR_POS12: u32 = 4096;
pub const GPIO_POSR_POS13_POS: u32 = 13;
pub const GPIO_POSR_POS13: u32 = 8192;
pub const GPIO_POSR_POS14_POS: u32 = 14;
pub const GPIO_POSR_POS14: u32 = 16384;
pub const GPIO_POSR_POS15_POS: u32 = 15;
pub const GPIO_POSR_POS15: u32 = 32768;
pub const GPIO_PORR_POR00_POS: u32 = 0;
pub const GPIO_PORR_POR00: u32 = 1;
pub const GPIO_PORR_POR01_POS: u32 = 1;
pub const GPIO_PORR_POR01: u32 = 2;
pub const GPIO_PORR_POR02_POS: u32 = 2;
pub const GPIO_PORR_POR02: u32 = 4;
pub const GPIO_PORR_POR03_POS: u32 = 3;
pub const GPIO_PORR_POR03: u32 = 8;
pub const GPIO_PORR_POR04_POS: u32 = 4;
pub const GPIO_PORR_POR04: u32 = 16;
pub const GPIO_PORR_POR05_POS: u32 = 5;
pub const GPIO_PORR_POR05: u32 = 32;
pub const GPIO_PORR_POR06_POS: u32 = 6;
pub const GPIO_PORR_POR06: u32 = 64;
pub const GPIO_PORR_POR07_POS: u32 = 7;
pub const GPIO_PORR_POR07: u32 = 128;
pub const GPIO_PORR_POR08_POS: u32 = 8;
pub const GPIO_PORR_POR08: u32 = 256;
pub const GPIO_PORR_POR09_POS: u32 = 9;
pub const GPIO_PORR_POR09: u32 = 512;
pub const GPIO_PORR_POR10_POS: u32 = 10;
pub const GPIO_PORR_POR10: u32 = 1024;
pub const GPIO_PORR_POR11_POS: u32 = 11;
pub const GPIO_PORR_POR11: u32 = 2048;
pub const GPIO_PORR_POR12_POS: u32 = 12;
pub const GPIO_PORR_POR12: u32 = 4096;
pub const GPIO_PORR_POR13_POS: u32 = 13;
pub const GPIO_PORR_POR13: u32 = 8192;
pub const GPIO_PORR_POR14_POS: u32 = 14;
pub const GPIO_PORR_POR14: u32 = 16384;
pub const GPIO_PORR_POR15_POS: u32 = 15;
pub const GPIO_PORR_POR15: u32 = 32768;
pub const GPIO_POTR_POT00_POS: u32 = 0;
pub const GPIO_POTR_POT00: u32 = 1;
pub const GPIO_POTR_POT01_POS: u32 = 1;
pub const GPIO_POTR_POT01: u32 = 2;
pub const GPIO_POTR_POT02_POS: u32 = 2;
pub const GPIO_POTR_POT02: u32 = 4;
pub const GPIO_POTR_POT03_POS: u32 = 3;
pub const GPIO_POTR_POT03: u32 = 8;
pub const GPIO_POTR_POT04_POS: u32 = 4;
pub const GPIO_POTR_POT04: u32 = 16;
pub const GPIO_POTR_POT05_POS: u32 = 5;
pub const GPIO_POTR_POT05: u32 = 32;
pub const GPIO_POTR_POT06_POS: u32 = 6;
pub const GPIO_POTR_POT06: u32 = 64;
pub const GPIO_POTR_POT07_POS: u32 = 7;
pub const GPIO_POTR_POT07: u32 = 128;
pub const GPIO_POTR_POT08_POS: u32 = 8;
pub const GPIO_POTR_POT08: u32 = 256;
pub const GPIO_POTR_POT09_POS: u32 = 9;
pub const GPIO_POTR_POT09: u32 = 512;
pub const GPIO_POTR_POT10_POS: u32 = 10;
pub const GPIO_POTR_POT10: u32 = 1024;
pub const GPIO_POTR_POT11_POS: u32 = 11;
pub const GPIO_POTR_POT11: u32 = 2048;
pub const GPIO_POTR_POT12_POS: u32 = 12;
pub const GPIO_POTR_POT12: u32 = 4096;
pub const GPIO_POTR_POT13_POS: u32 = 13;
pub const GPIO_POTR_POT13: u32 = 8192;
pub const GPIO_POTR_POT14_POS: u32 = 14;
pub const GPIO_POTR_POT14: u32 = 16384;
pub const GPIO_POTR_POT15_POS: u32 = 15;
pub const GPIO_POTR_POT15: u32 = 32768;
pub const GPIO_PIDRH_PIN00_POS: u32 = 0;
pub const GPIO_PIDRH_PIN00: u32 = 1;
pub const GPIO_PIDRH_PIN01_POS: u32 = 1;
pub const GPIO_PIDRH_PIN01: u32 = 2;
pub const GPIO_PIDRH_PIN02_POS: u32 = 2;
pub const GPIO_PIDRH_PIN02: u32 = 4;
pub const GPIO_PODRH_POUT00_POS: u32 = 0;
pub const GPIO_PODRH_POUT00: u32 = 1;
pub const GPIO_PODRH_POUT01_POS: u32 = 1;
pub const GPIO_PODRH_POUT01: u32 = 2;
pub const GPIO_PODRH_POUT02_POS: u32 = 2;
pub const GPIO_PODRH_POUT02: u32 = 4;
pub const GPIO_POERH_POUTE00_POS: u32 = 0;
pub const GPIO_POERH_POUTE00: u32 = 1;
pub const GPIO_POERH_POUTE01_POS: u32 = 1;
pub const GPIO_POERH_POUTE01: u32 = 2;
pub const GPIO_POERH_POUTE02_POS: u32 = 2;
pub const GPIO_POERH_POUTE02: u32 = 4;
pub const GPIO_POSRH_POS00_POS: u32 = 0;
pub const GPIO_POSRH_POS00: u32 = 1;
pub const GPIO_POSRH_POS01_POS: u32 = 1;
pub const GPIO_POSRH_POS01: u32 = 2;
pub const GPIO_POSRH_POS02_POS: u32 = 2;
pub const GPIO_POSRH_POS02: u32 = 4;
pub const GPIO_PORRH_POR00_POS: u32 = 0;
pub const GPIO_PORRH_POR00: u32 = 1;
pub const GPIO_PORRH_POR01_POS: u32 = 1;
pub const GPIO_PORRH_POR01: u32 = 2;
pub const GPIO_PORRH_POR02_POS: u32 = 2;
pub const GPIO_PORRH_POR02: u32 = 4;
pub const GPIO_POTRH_POT00_POS: u32 = 0;
pub const GPIO_POTRH_POT00: u32 = 1;
pub const GPIO_POTRH_POT01_POS: u32 = 1;
pub const GPIO_POTRH_POT01: u32 = 2;
pub const GPIO_POTRH_POT02_POS: u32 = 2;
pub const GPIO_POTRH_POT02: u32 = 4;
pub const GPIO_PSPCR_SPFE: u32 = 31;
pub const GPIO_PSPCR_SPFE_0: u32 = 1;
pub const GPIO_PSPCR_SPFE_1: u32 = 2;
pub const GPIO_PSPCR_SPFE_2: u32 = 4;
pub const GPIO_PSPCR_SPFE_3: u32 = 8;
pub const GPIO_PSPCR_SPFE_4: u32 = 16;
pub const GPIO_PCCR_BFSEL_POS: u32 = 0;
pub const GPIO_PCCR_BFSEL: u32 = 15;
pub const GPIO_PCCR_BFSEL_0: u32 = 1;
pub const GPIO_PCCR_BFSEL_1: u32 = 2;
pub const GPIO_PCCR_BFSEL_2: u32 = 4;
pub const GPIO_PCCR_BFSEL_3: u32 = 8;
pub const GPIO_PCCR_RDWT_POS: u32 = 14;
pub const GPIO_PCCR_RDWT: u32 = 49152;
pub const GPIO_PCCR_RDWT_0: u32 = 16384;
pub const GPIO_PCCR_RDWT_1: u32 = 32768;
pub const GPIO_PINAER_PINAE: u32 = 63;
pub const GPIO_PINAER_PINAE_0: u32 = 1;
pub const GPIO_PINAER_PINAE_1: u32 = 2;
pub const GPIO_PINAER_PINAE_2: u32 = 4;
pub const GPIO_PINAER_PINAE_3: u32 = 8;
pub const GPIO_PINAER_PINAE_4: u32 = 16;
pub const GPIO_PINAER_PINAE_5: u32 = 32;
pub const GPIO_PWPR_WE_POS: u32 = 0;
pub const GPIO_PWPR_WE: u32 = 1;
pub const GPIO_PWPR_WP_POS: u32 = 8;
pub const GPIO_PWPR_WP: u32 = 65280;
pub const GPIO_PWPR_WP_0: u32 = 256;
pub const GPIO_PWPR_WP_1: u32 = 512;
pub const GPIO_PWPR_WP_2: u32 = 1024;
pub const GPIO_PWPR_WP_3: u32 = 2048;
pub const GPIO_PWPR_WP_4: u32 = 4096;
pub const GPIO_PWPR_WP_5: u32 = 8192;
pub const GPIO_PWPR_WP_6: u32 = 16384;
pub const GPIO_PWPR_WP_7: u32 = 32768;
pub const GPIO_PCR_POUT_POS: u32 = 0;
pub const GPIO_PCR_POUT: u32 = 1;
pub const GPIO_PCR_POUTE_POS: u32 = 1;
pub const GPIO_PCR_POUTE: u32 = 2;
pub const GPIO_PCR_NOD_POS: u32 = 2;
pub const GPIO_PCR_NOD: u32 = 4;
pub const GPIO_PCR_DRV_POS: u32 = 4;
pub const GPIO_PCR_DRV: u32 = 48;
pub const GPIO_PCR_DRV_0: u32 = 16;
pub const GPIO_PCR_DRV_1: u32 = 32;
pub const GPIO_PCR_PUU_POS: u32 = 6;
pub const GPIO_PCR_PUU: u32 = 64;
pub const GPIO_PCR_PIN_POS: u32 = 8;
pub const GPIO_PCR_PIN: u32 = 256;
pub const GPIO_PCR_INVE_POS: u32 = 9;
pub const GPIO_PCR_INVE: u32 = 512;
pub const GPIO_PCR_INTE_POS: u32 = 12;
pub const GPIO_PCR_INTE: u32 = 4096;
pub const GPIO_PCR_LTE_POS: u32 = 14;
pub const GPIO_PCR_LTE: u32 = 16384;
pub const GPIO_PCR_DDIS_POS: u32 = 15;
pub const GPIO_PCR_DDIS: u32 = 32768;
pub const GPIO_PFSR_FSEL_POS: u32 = 0;
pub const GPIO_PFSR_FSEL: u32 = 63;
pub const GPIO_PFSR_FSEL_0: u32 = 1;
pub const GPIO_PFSR_FSEL_1: u32 = 2;
pub const GPIO_PFSR_FSEL_2: u32 = 4;
pub const GPIO_PFSR_FSEL_3: u32 = 8;
pub const GPIO_PFSR_FSEL_4: u32 = 16;
pub const GPIO_PFSR_FSEL_5: u32 = 32;
pub const GPIO_PFSR_BFE_POS: u32 = 8;
pub const GPIO_PFSR_BFE: u32 = 256;
pub const HASH_CR_START_POS: u32 = 0;
pub const HASH_CR_START: u32 = 1;
pub const HASH_CR_FST_GRP_POS: u32 = 1;
pub const HASH_CR_FST_GRP: u32 = 2;
pub const HASH_HR7: u32 = 4294967295;
pub const HASH_HR6: u32 = 4294967295;
pub const HASH_HR5: u32 = 4294967295;
pub const HASH_HR4: u32 = 4294967295;
pub const HASH_HR3: u32 = 4294967295;
pub const HASH_HR2: u32 = 4294967295;
pub const HASH_HR1: u32 = 4294967295;
pub const HASH_HR0: u32 = 4294967295;
pub const HASH_DR15: u32 = 4294967295;
pub const HASH_DR14: u32 = 4294967295;
pub const HASH_DR13: u32 = 4294967295;
pub const HASH_DR12: u32 = 4294967295;
pub const HASH_DR11: u32 = 4294967295;
pub const HASH_DR10: u32 = 4294967295;
pub const HASH_DR9: u32 = 4294967295;
pub const HASH_DR8: u32 = 4294967295;
pub const HASH_DR7: u32 = 4294967295;
pub const HASH_DR6: u32 = 4294967295;
pub const HASH_DR5: u32 = 4294967295;
pub const HASH_DR4: u32 = 4294967295;
pub const HASH_DR3: u32 = 4294967295;
pub const HASH_DR2: u32 = 4294967295;
pub const HASH_DR1: u32 = 4294967295;
pub const HASH_DR0: u32 = 4294967295;
pub const I2C_CR1_PE_POS: u32 = 0;
pub const I2C_CR1_PE: u32 = 1;
pub const I2C_CR1_SMBUS_POS: u32 = 1;
pub const I2C_CR1_SMBUS: u32 = 2;
pub const I2C_CR1_SMBALRTEN_POS: u32 = 2;
pub const I2C_CR1_SMBALRTEN: u32 = 4;
pub const I2C_CR1_SMBDEFAULTEN_POS: u32 = 3;
pub const I2C_CR1_SMBDEFAULTEN: u32 = 8;
pub const I2C_CR1_SMBHOSTEN_POS: u32 = 4;
pub const I2C_CR1_SMBHOSTEN: u32 = 16;
pub const I2C_CR1_GCEN_POS: u32 = 6;
pub const I2C_CR1_GCEN: u32 = 64;
pub const I2C_CR1_RESTART_POS: u32 = 7;
pub const I2C_CR1_RESTART: u32 = 128;
pub const I2C_CR1_START_POS: u32 = 8;
pub const I2C_CR1_START: u32 = 256;
pub const I2C_CR1_STOP_POS: u32 = 9;
pub const I2C_CR1_STOP: u32 = 512;
pub const I2C_CR1_ACK_POS: u32 = 10;
pub const I2C_CR1_ACK: u32 = 1024;
pub const I2C_CR1_SWRST_POS: u32 = 15;
pub const I2C_CR1_SWRST: u32 = 32768;
pub const I2C_CR2_STARTIE_POS: u32 = 0;
pub const I2C_CR2_STARTIE: u32 = 1;
pub const I2C_CR2_SLADDR0IE_POS: u32 = 1;
pub const I2C_CR2_SLADDR0IE: u32 = 2;
pub const I2C_CR2_SLADDR1IE_POS: u32 = 2;
pub const I2C_CR2_SLADDR1IE: u32 = 4;
pub const I2C_CR2_TENDIE_POS: u32 = 3;
pub const I2C_CR2_TENDIE: u32 = 8;
pub const I2C_CR2_STOPIE_POS: u32 = 4;
pub const I2C_CR2_STOPIE: u32 = 16;
pub const I2C_CR2_RFULLIE_POS: u32 = 6;
pub const I2C_CR2_RFULLIE: u32 = 64;
pub const I2C_CR2_TEMPTYIE_POS: u32 = 7;
pub const I2C_CR2_TEMPTYIE: u32 = 128;
pub const I2C_CR2_ARLOIE_POS: u32 = 9;
pub const I2C_CR2_ARLOIE: u32 = 512;
pub const I2C_CR2_NACKIE_POS: u32 = 12;
pub const I2C_CR2_NACKIE: u32 = 4096;
pub const I2C_CR2_TMOUTIE_POS: u32 = 14;
pub const I2C_CR2_TMOUTIE: u32 = 16384;
pub const I2C_CR2_GENCALLIE_POS: u32 = 20;
pub const I2C_CR2_GENCALLIE: u32 = 1048576;
pub const I2C_CR2_SMBDEFAULTIE_POS: u32 = 21;
pub const I2C_CR2_SMBDEFAULTIE: u32 = 2097152;
pub const I2C_CR2_SMBHOSTIE_POS: u32 = 22;
pub const I2C_CR2_SMBHOSTIE: u32 = 4194304;
pub const I2C_CR2_SMBALRTIE_POS: u32 = 23;
pub const I2C_CR2_SMBALRTIE: u32 = 8388608;
pub const I2C_CR3_TMOUTEN_POS: u32 = 0;
pub const I2C_CR3_TMOUTEN: u32 = 1;
pub const I2C_CR3_LTMOUT_POS: u32 = 1;
pub const I2C_CR3_LTMOUT: u32 = 2;
pub const I2C_CR3_HTMOUT_POS: u32 = 2;
pub const I2C_CR3_HTMOUT: u32 = 4;
pub const I2C_CR3_FACKEN_POS: u32 = 7;
pub const I2C_CR3_FACKEN: u32 = 128;
pub const I2C_CR4_BUSWAIT_POS: u32 = 10;
pub const I2C_CR4_BUSWAIT: u32 = 1024;
pub const I2C_SLR0_SLADDR0_POS: u32 = 0;
pub const I2C_SLR0_SLADDR0: u32 = 1023;
pub const I2C_SLR0_SLADDR0EN_POS: u32 = 12;
pub const I2C_SLR0_SLADDR0EN: u32 = 4096;
pub const I2C_SLR0_ADDRMOD0_POS: u32 = 15;
pub const I2C_SLR0_ADDRMOD0: u32 = 32768;
pub const I2C_SLR1_SLADDR1_POS: u32 = 0;
pub const I2C_SLR1_SLADDR1: u32 = 1023;
pub const I2C_SLR1_SLADDR1EN_POS: u32 = 12;
pub const I2C_SLR1_SLADDR1EN: u32 = 4096;
pub const I2C_SLR1_ADDRMOD1_POS: u32 = 15;
pub const I2C_SLR1_ADDRMOD1: u32 = 32768;
pub const I2C_SLTR_TOUTLOW_POS: u32 = 0;
pub const I2C_SLTR_TOUTLOW: u32 = 65535;
pub const I2C_SLTR_TOUTHIGH_POS: u32 = 16;
pub const I2C_SLTR_TOUTHIGH: u32 = 4294901760;
pub const I2C_SR_STARTF_POS: u32 = 0;
pub const I2C_SR_STARTF: u32 = 1;
pub const I2C_SR_SLADDR0F_POS: u32 = 1;
pub const I2C_SR_SLADDR0F: u32 = 2;
pub const I2C_SR_SLADDR1F_POS: u32 = 2;
pub const I2C_SR_SLADDR1F: u32 = 4;
pub const I2C_SR_TENDF_POS: u32 = 3;
pub const I2C_SR_TENDF: u32 = 8;
pub const I2C_SR_STOPF_POS: u32 = 4;
pub const I2C_SR_STOPF: u32 = 16;
pub const I2C_SR_RFULLF_POS: u32 = 6;
pub const I2C_SR_RFULLF: u32 = 64;
pub const I2C_SR_TEMPTYF_POS: u32 = 7;
pub const I2C_SR_TEMPTYF: u32 = 128;
pub const I2C_SR_ARLOF_POS: u32 = 9;
pub const I2C_SR_ARLOF: u32 = 512;
pub const I2C_SR_ACKRF_POS: u32 = 10;
pub const I2C_SR_ACKRF: u32 = 1024;
pub const I2C_SR_NACKF_POS: u32 = 12;
pub const I2C_SR_NACKF: u32 = 4096;
pub const I2C_SR_TMOUTF_POS: u32 = 14;
pub const I2C_SR_TMOUTF: u32 = 16384;
pub const I2C_SR_MSL_POS: u32 = 16;
pub const I2C_SR_MSL: u32 = 65536;
pub const I2C_SR_BUSY_POS: u32 = 17;
pub const I2C_SR_BUSY: u32 = 131072;
pub const I2C_SR_TRA_POS: u32 = 18;
pub const I2C_SR_TRA: u32 = 262144;
pub const I2C_SR_GENCALLF_POS: u32 = 20;
pub const I2C_SR_GENCALLF: u32 = 1048576;
pub const I2C_SR_SMBDEFAULTF_POS: u32 = 21;
pub const I2C_SR_SMBDEFAULTF: u32 = 2097152;
pub const I2C_SR_SMBHOSTF_POS: u32 = 22;
pub const I2C_SR_SMBHOSTF: u32 = 4194304;
pub const I2C_SR_SMBALRTF_POS: u32 = 23;
pub const I2C_SR_SMBALRTF: u32 = 8388608;
pub const I2C_CLR_STARTFCLR_POS: u32 = 0;
pub const I2C_CLR_STARTFCLR: u32 = 1;
pub const I2C_CLR_SLADDR0FCLR_POS: u32 = 1;
pub const I2C_CLR_SLADDR0FCLR: u32 = 2;
pub const I2C_CLR_SLADDR1FCLR_POS: u32 = 2;
pub const I2C_CLR_SLADDR1FCLR: u32 = 4;
pub const I2C_CLR_TENDFCLR_POS: u32 = 3;
pub const I2C_CLR_TENDFCLR: u32 = 8;
pub const I2C_CLR_STOPFCLR_POS: u32 = 4;
pub const I2C_CLR_STOPFCLR: u32 = 16;
pub const I2C_CLR_RFULLFCLR_POS: u32 = 6;
pub const I2C_CLR_RFULLFCLR: u32 = 64;
pub const I2C_CLR_TEMPTYFCLR_POS: u32 = 7;
pub const I2C_CLR_TEMPTYFCLR: u32 = 128;
pub const I2C_CLR_ARLOFCLR_POS: u32 = 9;
pub const I2C_CLR_ARLOFCLR: u32 = 512;
pub const I2C_CLR_NACKFCLR_POS: u32 = 12;
pub const I2C_CLR_NACKFCLR: u32 = 4096;
pub const I2C_CLR_TMOUTFCLR_POS: u32 = 14;
pub const I2C_CLR_TMOUTFCLR: u32 = 16384;
pub const I2C_CLR_GENCALLFCLR_POS: u32 = 20;
pub const I2C_CLR_GENCALLFCLR: u32 = 1048576;
pub const I2C_CLR_SMBDEFAULTFCLR_POS: u32 = 21;
pub const I2C_CLR_SMBDEFAULTFCLR: u32 = 2097152;
pub const I2C_CLR_SMBHOSTFCLR_POS: u32 = 22;
pub const I2C_CLR_SMBHOSTFCLR: u32 = 4194304;
pub const I2C_CLR_SMBALRTFCLR_POS: u32 = 23;
pub const I2C_CLR_SMBALRTFCLR: u32 = 8388608;
pub const I2C_DTR_DT: u32 = 255;
pub const I2C_DRR_DR: u32 = 255;
pub const I2C_CCR_SLOWW_POS: u32 = 0;
pub const I2C_CCR_SLOWW: u32 = 31;
pub const I2C_CCR_SHIGHW_POS: u32 = 8;
pub const I2C_CCR_SHIGHW: u32 = 7936;
pub const I2C_CCR_CKDIV_POS: u32 = 16;
pub const I2C_CCR_CKDIV: u32 = 458752;
pub const I2C_FLTR_DNF_POS: u32 = 0;
pub const I2C_FLTR_DNF: u32 = 3;
pub const I2C_FLTR_DNF_0: u32 = 1;
pub const I2C_FLTR_DNF_1: u32 = 2;
pub const I2C_FLTR_DNFEN_POS: u32 = 4;
pub const I2C_FLTR_DNFEN: u32 = 16;
pub const I2C_FLTR_ANFEN_POS: u32 = 5;
pub const I2C_FLTR_ANFEN: u32 = 32;
pub const I2S_CTRL_TXE_POS: u32 = 0;
pub const I2S_CTRL_TXE: u32 = 1;
pub const I2S_CTRL_TXIE_POS: u32 = 1;
pub const I2S_CTRL_TXIE: u32 = 2;
pub const I2S_CTRL_RXE_POS: u32 = 2;
pub const I2S_CTRL_RXE: u32 = 4;
pub const I2S_CTRL_RXIE_POS: u32 = 3;
pub const I2S_CTRL_RXIE: u32 = 8;
pub const I2S_CTRL_EIE_POS: u32 = 4;
pub const I2S_CTRL_EIE: u32 = 16;
pub const I2S_CTRL_WMS_POS: u32 = 5;
pub const I2S_CTRL_WMS: u32 = 32;
pub const I2S_CTRL_ODD_POS: u32 = 6;
pub const I2S_CTRL_ODD: u32 = 64;
pub const I2S_CTRL_MCKOE_POS: u32 = 7;
pub const I2S_CTRL_MCKOE: u32 = 128;
pub const I2S_CTRL_TXBIRQWL_POS: u32 = 8;
pub const I2S_CTRL_TXBIRQWL: u32 = 1792;
pub const I2S_CTRL_RXBIRQWL_POS: u32 = 12;
pub const I2S_CTRL_RXBIRQWL: u32 = 28672;
pub const I2S_CTRL_FIFOR_POS: u32 = 16;
pub const I2S_CTRL_FIFOR: u32 = 65536;
pub const I2S_CTRL_I2SPLLSEL_POS: u32 = 18;
pub const I2S_CTRL_I2SPLLSEL: u32 = 262144;
pub const I2S_CTRL_SDOE_POS: u32 = 19;
pub const I2S_CTRL_SDOE: u32 = 524288;
pub const I2S_CTRL_LRCKOE_POS: u32 = 20;
pub const I2S_CTRL_LRCKOE: u32 = 1048576;
pub const I2S_CTRL_CKOE_POS: u32 = 21;
pub const I2S_CTRL_CKOE: u32 = 2097152;
pub const I2S_CTRL_DUPLEX_POS: u32 = 22;
pub const I2S_CTRL_DUPLEX: u32 = 4194304;
pub const I2S_CTRL_CLKSEL_POS: u32 = 23;
pub const I2S_CTRL_CLKSEL: u32 = 8388608;
pub const I2S_SR_TXBA_POS: u32 = 0;
pub const I2S_SR_TXBA: u32 = 1;
pub const I2S_SR_RXBA_POS: u32 = 1;
pub const I2S_SR_RXBA: u32 = 2;
pub const I2S_SR_TXBE_POS: u32 = 2;
pub const I2S_SR_TXBE: u32 = 4;
pub const I2S_SR_TXBF_POS: u32 = 3;
pub const I2S_SR_TXBF: u32 = 8;
pub const I2S_SR_RXBE_POS: u32 = 4;
pub const I2S_SR_RXBE: u32 = 16;
pub const I2S_SR_RXBF_POS: u32 = 5;
pub const I2S_SR_RXBF: u32 = 32;
pub const I2S_ER_TXERR_POS: u32 = 0;
pub const I2S_ER_TXERR: u32 = 1;
pub const I2S_ER_RXERR_POS: u32 = 1;
pub const I2S_ER_RXERR: u32 = 2;
pub const I2S_CFGR_I2SSTD_POS: u32 = 0;
pub const I2S_CFGR_I2SSTD: u32 = 3;
pub const I2S_CFGR_I2SSTD_0: u32 = 1;
pub const I2S_CFGR_I2SSTD_1: u32 = 2;
pub const I2S_CFGR_DATLEN_POS: u32 = 2;
pub const I2S_CFGR_DATLEN: u32 = 12;
pub const I2S_CFGR_DATLEN_0: u32 = 4;
pub const I2S_CFGR_DATLEN_1: u32 = 8;
pub const I2S_CFGR_CHLEN_POS: u32 = 4;
pub const I2S_CFGR_CHLEN: u32 = 16;
pub const I2S_CFGR_PCMSYNC_POS: u32 = 5;
pub const I2S_CFGR_PCMSYNC: u32 = 32;
pub const I2S_TXBUF: u32 = 4294967295;
pub const I2S_RXBUF: u32 = 4294967295;
pub const I2S_PR_I2SDIV: u32 = 255;
pub const ICG_ICG0_SWDTAUTS_POS: u32 = 0;
pub const ICG_ICG0_SWDTAUTS: u32 = 1;
pub const ICG_ICG0_SWDTITS_POS: u32 = 1;
pub const ICG_ICG0_SWDTITS: u32 = 2;
pub const ICG_ICG0_SWDTPERI_POS: u32 = 2;
pub const ICG_ICG0_SWDTPERI: u32 = 12;
pub const ICG_ICG0_SWDTPERI_0: u32 = 4;
pub const ICG_ICG0_SWDTPERI_1: u32 = 8;
pub const ICG_ICG0_SWDTCKS_POS: u32 = 4;
pub const ICG_ICG0_SWDTCKS: u32 = 240;
pub const ICG_ICG0_SWDTWDPT_POS: u32 = 8;
pub const ICG_ICG0_SWDTWDPT: u32 = 3840;
pub const ICG_ICG0_SWDTSLPOFF_POS: u32 = 12;
pub const ICG_ICG0_SWDTSLPOFF: u32 = 4096;
pub const ICG_ICG0_WDTAUTS_POS: u32 = 16;
pub const ICG_ICG0_WDTAUTS: u32 = 65536;
pub const ICG_ICG0_WDTITS_POS: u32 = 17;
pub const ICG_ICG0_WDTITS: u32 = 131072;
pub const ICG_ICG0_WDTPERI_POS: u32 = 18;
pub const ICG_ICG0_WDTPERI: u32 = 786432;
pub const ICG_ICG0_WDTPERI_0: u32 = 262144;
pub const ICG_ICG0_WDTPERI_1: u32 = 524288;
pub const ICG_ICG0_WDTCKS_POS: u32 = 20;
pub const ICG_ICG0_WDTCKS: u32 = 15728640;
pub const ICG_ICG0_WDTWDPT_POS: u32 = 24;
pub const ICG_ICG0_WDTWDPT: u32 = 251658240;
pub const ICG_ICG0_WDTSLPOFF_POS: u32 = 28;
pub const ICG_ICG0_WDTSLPOFF: u32 = 268435456;
pub const ICG_ICG1_HRCFREQSEL_POS: u32 = 0;
pub const ICG_ICG1_HRCFREQSEL: u32 = 1;
pub const ICG_ICG1_HRCSTOP_POS: u32 = 8;
pub const ICG_ICG1_HRCSTOP: u32 = 256;
pub const ICG_ICG1_BOR_LEV_POS: u32 = 16;
pub const ICG_ICG1_BOR_LEV: u32 = 196608;
pub const ICG_ICG1_BOR_LEV_0: u32 = 65536;
pub const ICG_ICG1_BOR_LEV_1: u32 = 131072;
pub const ICG_ICG1_BORDIS_POS: u32 = 18;
pub const ICG_ICG1_BORDIS: u32 = 262144;
pub const ICG_ICG1_SMPCLK_POS: u32 = 26;
pub const ICG_ICG1_SMPCLK: u32 = 201326592;
pub const ICG_ICG1_SMPCLK_0: u32 = 67108864;
pub const ICG_ICG1_SMPCLK_1: u32 = 134217728;
pub const ICG_ICG1_NMITRG_POS: u32 = 28;
pub const ICG_ICG1_NMITRG: u32 = 268435456;
pub const ICG_ICG1_NMIEN_POS: u32 = 29;
pub const ICG_ICG1_NMIEN: u32 = 536870912;
pub const ICG_ICG1_NFEN_POS: u32 = 30;
pub const ICG_ICG1_NFEN: u32 = 1073741824;
pub const ICG_ICG1_NMIICGEN_POS: u32 = 31;
pub const ICG_ICG1_NMIICGEN: u32 = 2147483648;
pub const ICG_ICG2: u32 = 4294967295;
pub const ICG_ICG3: u32 = 4294967295;
pub const ICG_ICG4: u32 = 4294967295;
pub const ICG_ICG5: u32 = 4294967295;
pub const ICG_ICG6: u32 = 4294967295;
pub const ICG_ICG7: u32 = 4294967295;
pub const INTC_NMICR_NMITRG_POS: u32 = 0;
pub const INTC_NMICR_NMITRG: u32 = 1;
pub const INTC_NMICR_NSMPCLK_POS: u32 = 4;
pub const INTC_NMICR_NSMPCLK: u32 = 48;
pub const INTC_NMICR_NSMPCLK_0: u32 = 16;
pub const INTC_NMICR_NSMPCLK_1: u32 = 32;
pub const INTC_NMICR_NFEN_POS: u32 = 7;
pub const INTC_NMICR_NFEN: u32 = 128;
pub const INTC_NMIENR_NMIENR_POS: u32 = 0;
pub const INTC_NMIENR_NMIENR: u32 = 1;
pub const INTC_NMIENR_SWDTENR_POS: u32 = 1;
pub const INTC_NMIENR_SWDTENR: u32 = 2;
pub const INTC_NMIENR_PVD1ENR_POS: u32 = 2;
pub const INTC_NMIENR_PVD1ENR: u32 = 4;
pub const INTC_NMIENR_PVD2ENR_POS: u32 = 3;
pub const INTC_NMIENR_PVD2ENR: u32 = 8;
pub const INTC_NMIENR_XTALSTPENR_POS: u32 = 5;
pub const INTC_NMIENR_XTALSTPENR: u32 = 32;
pub const INTC_NMIENR_REPENR_POS: u32 = 8;
pub const INTC_NMIENR_REPENR: u32 = 256;
pub const INTC_NMIENR_RECCENR_POS: u32 = 9;
pub const INTC_NMIENR_RECCENR: u32 = 512;
pub const INTC_NMIENR_BUSMENR_POS: u32 = 10;
pub const INTC_NMIENR_BUSMENR: u32 = 1024;
pub const INTC_NMIENR_WDTENR_POS: u32 = 11;
pub const INTC_NMIENR_WDTENR: u32 = 2048;
pub const INTC_NMIFR_NMIFR_POS: u32 = 0;
pub const INTC_NMIFR_NMIFR: u32 = 1;
pub const INTC_NMIFR_SWDTFR_POS: u32 = 1;
pub const INTC_NMIFR_SWDTFR: u32 = 2;
pub const INTC_NMIFR_PVD1FR_POS: u32 = 2;
pub const INTC_NMIFR_PVD1FR: u32 = 4;
pub const INTC_NMIFR_PVD2FR_POS: u32 = 3;
pub const INTC_NMIFR_PVD2FR: u32 = 8;
pub const INTC_NMIFR_XTALSTPFR_POS: u32 = 5;
pub const INTC_NMIFR_XTALSTPFR: u32 = 32;
pub const INTC_NMIFR_REPFR_POS: u32 = 8;
pub const INTC_NMIFR_REPFR: u32 = 256;
pub const INTC_NMIFR_RECCFR_POS: u32 = 9;
pub const INTC_NMIFR_RECCFR: u32 = 512;
pub const INTC_NMIFR_BUSMFR_POS: u32 = 10;
pub const INTC_NMIFR_BUSMFR: u32 = 1024;
pub const INTC_NMIFR_WDTFR_POS: u32 = 11;
pub const INTC_NMIFR_WDTFR: u32 = 2048;
pub const INTC_NMICFR_NMICFR_POS: u32 = 0;
pub const INTC_NMICFR_NMICFR: u32 = 1;
pub const INTC_NMICFR_SWDTCFR_POS: u32 = 1;
pub const INTC_NMICFR_SWDTCFR: u32 = 2;
pub const INTC_NMICFR_PVD1CFR_POS: u32 = 2;
pub const INTC_NMICFR_PVD1CFR: u32 = 4;
pub const INTC_NMICFR_PVD2CFR_POS: u32 = 3;
pub const INTC_NMICFR_PVD2CFR: u32 = 8;
pub const INTC_NMICFR_XTALSTPCFR_POS: u32 = 5;
pub const INTC_NMICFR_XTALSTPCFR: u32 = 32;
pub const INTC_NMICFR_REPCFR_POS: u32 = 8;
pub const INTC_NMICFR_REPCFR: u32 = 256;
pub const INTC_NMICFR_RECCCFR_POS: u32 = 9;
pub const INTC_NMICFR_RECCCFR: u32 = 512;
pub const INTC_NMICFR_BUSMCFR_POS: u32 = 10;
pub const INTC_NMICFR_BUSMCFR: u32 = 1024;
pub const INTC_NMICFR_WDTCFR_POS: u32 = 11;
pub const INTC_NMICFR_WDTCFR: u32 = 2048;
pub const INTC_EIRQCR_EIRQTRG_POS: u32 = 0;
pub const INTC_EIRQCR_EIRQTRG: u32 = 3;
pub const INTC_EIRQCR_EIRQTRG_0: u32 = 1;
pub const INTC_EIRQCR_EIRQTRG_1: u32 = 2;
pub const INTC_EIRQCR_EISMPCLK_POS: u32 = 4;
pub const INTC_EIRQCR_EISMPCLK: u32 = 48;
pub const INTC_EIRQCR_EISMPCLK_0: u32 = 16;
pub const INTC_EIRQCR_EISMPCLK_1: u32 = 32;
pub const INTC_EIRQCR_EFEN_POS: u32 = 7;
pub const INTC_EIRQCR_EFEN: u32 = 128;
pub const INTC_WUPEN_EIRQWUEN_POS: u32 = 0;
pub const INTC_WUPEN_EIRQWUEN: u32 = 65535;
pub const INTC_WUPEN_EIRQWUEN_0: u32 = 1;
pub const INTC_WUPEN_EIRQWUEN_1: u32 = 2;
pub const INTC_WUPEN_EIRQWUEN_2: u32 = 4;
pub const INTC_WUPEN_EIRQWUEN_3: u32 = 8;
pub const INTC_WUPEN_EIRQWUEN_4: u32 = 16;
pub const INTC_WUPEN_EIRQWUEN_5: u32 = 32;
pub const INTC_WUPEN_EIRQWUEN_6: u32 = 64;
pub const INTC_WUPEN_EIRQWUEN_7: u32 = 128;
pub const INTC_WUPEN_EIRQWUEN_8: u32 = 256;
pub const INTC_WUPEN_EIRQWUEN_9: u32 = 512;
pub const INTC_WUPEN_EIRQWUEN_10: u32 = 1024;
pub const INTC_WUPEN_EIRQWUEN_11: u32 = 2048;
pub const INTC_WUPEN_EIRQWUEN_12: u32 = 4096;
pub const INTC_WUPEN_EIRQWUEN_13: u32 = 8192;
pub const INTC_WUPEN_EIRQWUEN_14: u32 = 16384;
pub const INTC_WUPEN_EIRQWUEN_15: u32 = 32768;
pub const INTC_WUPEN_SWDTWUEN_POS: u32 = 16;
pub const INTC_WUPEN_SWDTWUEN: u32 = 65536;
pub const INTC_WUPEN_PVD1WUEN_POS: u32 = 17;
pub const INTC_WUPEN_PVD1WUEN: u32 = 131072;
pub const INTC_WUPEN_PVD2WUEN_POS: u32 = 18;
pub const INTC_WUPEN_PVD2WUEN: u32 = 262144;
pub const INTC_WUPEN_CMPI0WUEN_POS: u32 = 19;
pub const INTC_WUPEN_CMPI0WUEN: u32 = 524288;
pub const INTC_WUPEN_WKTMWUEN_POS: u32 = 20;
pub const INTC_WUPEN_WKTMWUEN: u32 = 1048576;
pub const INTC_WUPEN_RTCALMWUEN_POS: u32 = 21;
pub const INTC_WUPEN_RTCALMWUEN: u32 = 2097152;
pub const INTC_WUPEN_RTCPRDWUEN_POS: u32 = 22;
pub const INTC_WUPEN_RTCPRDWUEN: u32 = 4194304;
pub const INTC_WUPEN_TMR0WUEN_POS: u32 = 23;
pub const INTC_WUPEN_TMR0WUEN: u32 = 8388608;
pub const INTC_WUPEN_RXWUEN_POS: u32 = 25;
pub const INTC_WUPEN_RXWUEN: u32 = 33554432;
pub const INTC_EIFR_EIFR0_POS: u32 = 0;
pub const INTC_EIFR_EIFR0: u32 = 1;
pub const INTC_EIFR_EIFR1_POS: u32 = 1;
pub const INTC_EIFR_EIFR1: u32 = 2;
pub const INTC_EIFR_EIFR2_POS: u32 = 2;
pub const INTC_EIFR_EIFR2: u32 = 4;
pub const INTC_EIFR_EIFR3_POS: u32 = 3;
pub const INTC_EIFR_EIFR3: u32 = 8;
pub const INTC_EIFR_EIFR4_POS: u32 = 4;
pub const INTC_EIFR_EIFR4: u32 = 16;
pub const INTC_EIFR_EIFR5_POS: u32 = 5;
pub const INTC_EIFR_EIFR5: u32 = 32;
pub const INTC_EIFR_EIFR6_POS: u32 = 6;
pub const INTC_EIFR_EIFR6: u32 = 64;
pub const INTC_EIFR_EIFR7_POS: u32 = 7;
pub const INTC_EIFR_EIFR7: u32 = 128;
pub const INTC_EIFR_EIFR8_POS: u32 = 8;
pub const INTC_EIFR_EIFR8: u32 = 256;
pub const INTC_EIFR_EIFR9_POS: u32 = 9;
pub const INTC_EIFR_EIFR9: u32 = 512;
pub const INTC_EIFR_EIFR10_POS: u32 = 10;
pub const INTC_EIFR_EIFR10: u32 = 1024;
pub const INTC_EIFR_EIFR11_POS: u32 = 11;
pub const INTC_EIFR_EIFR11: u32 = 2048;
pub const INTC_EIFR_EIFR12_POS: u32 = 12;
pub const INTC_EIFR_EIFR12: u32 = 4096;
pub const INTC_EIFR_EIFR13_POS: u32 = 13;
pub const INTC_EIFR_EIFR13: u32 = 8192;
pub const INTC_EIFR_EIFR14_POS: u32 = 14;
pub const INTC_EIFR_EIFR14: u32 = 16384;
pub const INTC_EIFR_EIFR15_POS: u32 = 15;
pub const INTC_EIFR_EIFR15: u32 = 32768;
pub const INTC_EIFCR_EIFCR0_POS: u32 = 0;
pub const INTC_EIFCR_EIFCR0: u32 = 1;
pub const INTC_EIFCR_EIFCR1_POS: u32 = 1;
pub const INTC_EIFCR_EIFCR1: u32 = 2;
pub const INTC_EIFCR_EIFCR2_POS: u32 = 2;
pub const INTC_EIFCR_EIFCR2: u32 = 4;
pub const INTC_EIFCR_EIFCR3_POS: u32 = 3;
pub const INTC_EIFCR_EIFCR3: u32 = 8;
pub const INTC_EIFCR_EIFCR4_POS: u32 = 4;
pub const INTC_EIFCR_EIFCR4: u32 = 16;
pub const INTC_EIFCR_EIFCR5_POS: u32 = 5;
pub const INTC_EIFCR_EIFCR5: u32 = 32;
pub const INTC_EIFCR_EIFCR6_POS: u32 = 6;
pub const INTC_EIFCR_EIFCR6: u32 = 64;
pub const INTC_EIFCR_EIFCR7_POS: u32 = 7;
pub const INTC_EIFCR_EIFCR7: u32 = 128;
pub const INTC_EIFCR_EIFCR8_POS: u32 = 8;
pub const INTC_EIFCR_EIFCR8: u32 = 256;
pub const INTC_EIFCR_EIFCR9_POS: u32 = 9;
pub const INTC_EIFCR_EIFCR9: u32 = 512;
pub const INTC_EIFCR_EIFCR10_POS: u32 = 10;
pub const INTC_EIFCR_EIFCR10: u32 = 1024;
pub const INTC_EIFCR_EIFCR11_POS: u32 = 11;
pub const INTC_EIFCR_EIFCR11: u32 = 2048;
pub const INTC_EIFCR_EIFCR12_POS: u32 = 12;
pub const INTC_EIFCR_EIFCR12: u32 = 4096;
pub const INTC_EIFCR_EIFCR13_POS: u32 = 13;
pub const INTC_EIFCR_EIFCR13: u32 = 8192;
pub const INTC_EIFCR_EIFCR14_POS: u32 = 14;
pub const INTC_EIFCR_EIFCR14: u32 = 16384;
pub const INTC_EIFCR_EIFCR15_POS: u32 = 15;
pub const INTC_EIFCR_EIFCR15: u32 = 32768;
pub const INTC_SEL_INTSEL: u32 = 511;
pub const INTC_SEL_INTSEL_0: u32 = 1;
pub const INTC_SEL_INTSEL_1: u32 = 2;
pub const INTC_SEL_INTSEL_2: u32 = 4;
pub const INTC_SEL_INTSEL_3: u32 = 8;
pub const INTC_SEL_INTSEL_4: u32 = 16;
pub const INTC_SEL_INTSEL_5: u32 = 32;
pub const INTC_SEL_INTSEL_6: u32 = 64;
pub const INTC_SEL_INTSEL_7: u32 = 128;
pub const INTC_SEL_INTSEL_8: u32 = 256;
pub const INTC_VSSEL_VSEL0_POS: u32 = 0;
pub const INTC_VSSEL_VSEL0: u32 = 1;
pub const INTC_VSSEL_VSEL1_POS: u32 = 1;
pub const INTC_VSSEL_VSEL1: u32 = 2;
pub const INTC_VSSEL_VSEL2_POS: u32 = 2;
pub const INTC_VSSEL_VSEL2: u32 = 4;
pub const INTC_VSSEL_VSEL3_POS: u32 = 3;
pub const INTC_VSSEL_VSEL3: u32 = 8;
pub const INTC_VSSEL_VSEL4_POS: u32 = 4;
pub const INTC_VSSEL_VSEL4: u32 = 16;
pub const INTC_VSSEL_VSEL5_POS: u32 = 5;
pub const INTC_VSSEL_VSEL5: u32 = 32;
pub const INTC_VSSEL_VSEL6_POS: u32 = 6;
pub const INTC_VSSEL_VSEL6: u32 = 64;
pub const INTC_VSSEL_VSEL7_POS: u32 = 7;
pub const INTC_VSSEL_VSEL7: u32 = 128;
pub const INTC_VSSEL_VSEL8_POS: u32 = 8;
pub const INTC_VSSEL_VSEL8: u32 = 256;
pub const INTC_VSSEL_VSEL9_POS: u32 = 9;
pub const INTC_VSSEL_VSEL9: u32 = 512;
pub const INTC_VSSEL_VSEL10_POS: u32 = 10;
pub const INTC_VSSEL_VSEL10: u32 = 1024;
pub const INTC_VSSEL_VSEL11_POS: u32 = 11;
pub const INTC_VSSEL_VSEL11: u32 = 2048;
pub const INTC_VSSEL_VSEL12_POS: u32 = 12;
pub const INTC_VSSEL_VSEL12: u32 = 4096;
pub const INTC_VSSEL_VSEL13_POS: u32 = 13;
pub const INTC_VSSEL_VSEL13: u32 = 8192;
pub const INTC_VSSEL_VSEL14_POS: u32 = 14;
pub const INTC_VSSEL_VSEL14: u32 = 16384;
pub const INTC_VSSEL_VSEL15_POS: u32 = 15;
pub const INTC_VSSEL_VSEL15: u32 = 32768;
pub const INTC_VSSEL_VSEL16_POS: u32 = 16;
pub const INTC_VSSEL_VSEL16: u32 = 65536;
pub const INTC_VSSEL_VSEL17_POS: u32 = 17;
pub const INTC_VSSEL_VSEL17: u32 = 131072;
pub const INTC_VSSEL_VSEL18_POS: u32 = 18;
pub const INTC_VSSEL_VSEL18: u32 = 262144;
pub const INTC_VSSEL_VSEL19_POS: u32 = 19;
pub const INTC_VSSEL_VSEL19: u32 = 524288;
pub const INTC_VSSEL_VSEL20_POS: u32 = 20;
pub const INTC_VSSEL_VSEL20: u32 = 1048576;
pub const INTC_VSSEL_VSEL21_POS: u32 = 21;
pub const INTC_VSSEL_VSEL21: u32 = 2097152;
pub const INTC_VSSEL_VSEL22_POS: u32 = 22;
pub const INTC_VSSEL_VSEL22: u32 = 4194304;
pub const INTC_VSSEL_VSEL23_POS: u32 = 23;
pub const INTC_VSSEL_VSEL23: u32 = 8388608;
pub const INTC_VSSEL_VSEL24_POS: u32 = 24;
pub const INTC_VSSEL_VSEL24: u32 = 16777216;
pub const INTC_VSSEL_VSEL25_POS: u32 = 25;
pub const INTC_VSSEL_VSEL25: u32 = 33554432;
pub const INTC_VSSEL_VSEL26_POS: u32 = 26;
pub const INTC_VSSEL_VSEL26: u32 = 67108864;
pub const INTC_VSSEL_VSEL27_POS: u32 = 27;
pub const INTC_VSSEL_VSEL27: u32 = 134217728;
pub const INTC_VSSEL_VSEL28_POS: u32 = 28;
pub const INTC_VSSEL_VSEL28: u32 = 268435456;
pub const INTC_VSSEL_VSEL29_POS: u32 = 29;
pub const INTC_VSSEL_VSEL29: u32 = 536870912;
pub const INTC_VSSEL_VSEL30_POS: u32 = 30;
pub const INTC_VSSEL_VSEL30: u32 = 1073741824;
pub const INTC_VSSEL_VSEL31_POS: u32 = 31;
pub const INTC_VSSEL_VSEL31: u32 = 2147483648;
pub const INTC_SWIER_SWIE0_POS: u32 = 0;
pub const INTC_SWIER_SWIE0: u32 = 1;
pub const INTC_SWIER_SWIE1_POS: u32 = 1;
pub const INTC_SWIER_SWIE1: u32 = 2;
pub const INTC_SWIER_SWIE2_POS: u32 = 2;
pub const INTC_SWIER_SWIE2: u32 = 4;
pub const INTC_SWIER_SWIE3_POS: u32 = 3;
pub const INTC_SWIER_SWIE3: u32 = 8;
pub const INTC_SWIER_SWIE4_POS: u32 = 4;
pub const INTC_SWIER_SWIE4: u32 = 16;
pub const INTC_SWIER_SWIE5_POS: u32 = 5;
pub const INTC_SWIER_SWIE5: u32 = 32;
pub const INTC_SWIER_SWIE6_POS: u32 = 6;
pub const INTC_SWIER_SWIE6: u32 = 64;
pub const INTC_SWIER_SWIE7_POS: u32 = 7;
pub const INTC_SWIER_SWIE7: u32 = 128;
pub const INTC_SWIER_SWIE8_POS: u32 = 8;
pub const INTC_SWIER_SWIE8: u32 = 256;
pub const INTC_SWIER_SWIE9_POS: u32 = 9;
pub const INTC_SWIER_SWIE9: u32 = 512;
pub const INTC_SWIER_SWIE10_POS: u32 = 10;
pub const INTC_SWIER_SWIE10: u32 = 1024;
pub const INTC_SWIER_SWIE11_POS: u32 = 11;
pub const INTC_SWIER_SWIE11: u32 = 2048;
pub const INTC_SWIER_SWIE12_POS: u32 = 12;
pub const INTC_SWIER_SWIE12: u32 = 4096;
pub const INTC_SWIER_SWIE13_POS: u32 = 13;
pub const INTC_SWIER_SWIE13: u32 = 8192;
pub const INTC_SWIER_SWIE14_POS: u32 = 14;
pub const INTC_SWIER_SWIE14: u32 = 16384;
pub const INTC_SWIER_SWIE15_POS: u32 = 15;
pub const INTC_SWIER_SWIE15: u32 = 32768;
pub const INTC_SWIER_SWIE16_POS: u32 = 16;
pub const INTC_SWIER_SWIE16: u32 = 65536;
pub const INTC_SWIER_SWIE17_POS: u32 = 17;
pub const INTC_SWIER_SWIE17: u32 = 131072;
pub const INTC_SWIER_SWIE18_POS: u32 = 18;
pub const INTC_SWIER_SWIE18: u32 = 262144;
pub const INTC_SWIER_SWIE19_POS: u32 = 19;
pub const INTC_SWIER_SWIE19: u32 = 524288;
pub const INTC_SWIER_SWIE20_POS: u32 = 20;
pub const INTC_SWIER_SWIE20: u32 = 1048576;
pub const INTC_SWIER_SWIE21_POS: u32 = 21;
pub const INTC_SWIER_SWIE21: u32 = 2097152;
pub const INTC_SWIER_SWIE22_POS: u32 = 22;
pub const INTC_SWIER_SWIE22: u32 = 4194304;
pub const INTC_SWIER_SWIE23_POS: u32 = 23;
pub const INTC_SWIER_SWIE23: u32 = 8388608;
pub const INTC_SWIER_SWIE24_POS: u32 = 24;
pub const INTC_SWIER_SWIE24: u32 = 16777216;
pub const INTC_SWIER_SWIE25_POS: u32 = 25;
pub const INTC_SWIER_SWIE25: u32 = 33554432;
pub const INTC_SWIER_SWIE26_POS: u32 = 26;
pub const INTC_SWIER_SWIE26: u32 = 67108864;
pub const INTC_SWIER_SWIE27_POS: u32 = 27;
pub const INTC_SWIER_SWIE27: u32 = 134217728;
pub const INTC_SWIER_SWIE28_POS: u32 = 28;
pub const INTC_SWIER_SWIE28: u32 = 268435456;
pub const INTC_SWIER_SWIE29_POS: u32 = 29;
pub const INTC_SWIER_SWIE29: u32 = 536870912;
pub const INTC_SWIER_SWIE30_POS: u32 = 30;
pub const INTC_SWIER_SWIE30: u32 = 1073741824;
pub const INTC_SWIER_SWIE31_POS: u32 = 31;
pub const INTC_SWIER_SWIE31: u32 = 2147483648;
pub const INTC_EVTER_EVTE0_POS: u32 = 0;
pub const INTC_EVTER_EVTE0: u32 = 1;
pub const INTC_EVTER_EVTE1_POS: u32 = 1;
pub const INTC_EVTER_EVTE1: u32 = 2;
pub const INTC_EVTER_EVTE2_POS: u32 = 2;
pub const INTC_EVTER_EVTE2: u32 = 4;
pub const INTC_EVTER_EVTE3_POS: u32 = 3;
pub const INTC_EVTER_EVTE3: u32 = 8;
pub const INTC_EVTER_EVTE4_POS: u32 = 4;
pub const INTC_EVTER_EVTE4: u32 = 16;
pub const INTC_EVTER_EVTE5_POS: u32 = 5;
pub const INTC_EVTER_EVTE5: u32 = 32;
pub const INTC_EVTER_EVTE6_POS: u32 = 6;
pub const INTC_EVTER_EVTE6: u32 = 64;
pub const INTC_EVTER_EVTE7_POS: u32 = 7;
pub const INTC_EVTER_EVTE7: u32 = 128;
pub const INTC_EVTER_EVTE8_POS: u32 = 8;
pub const INTC_EVTER_EVTE8: u32 = 256;
pub const INTC_EVTER_EVTE9_POS: u32 = 9;
pub const INTC_EVTER_EVTE9: u32 = 512;
pub const INTC_EVTER_EVTE10_POS: u32 = 10;
pub const INTC_EVTER_EVTE10: u32 = 1024;
pub const INTC_EVTER_EVTE11_POS: u32 = 11;
pub const INTC_EVTER_EVTE11: u32 = 2048;
pub const INTC_EVTER_EVTE12_POS: u32 = 12;
pub const INTC_EVTER_EVTE12: u32 = 4096;
pub const INTC_EVTER_EVTE13_POS: u32 = 13;
pub const INTC_EVTER_EVTE13: u32 = 8192;
pub const INTC_EVTER_EVTE14_POS: u32 = 14;
pub const INTC_EVTER_EVTE14: u32 = 16384;
pub const INTC_EVTER_EVTE15_POS: u32 = 15;
pub const INTC_EVTER_EVTE15: u32 = 32768;
pub const INTC_EVTER_EVTE16_POS: u32 = 16;
pub const INTC_EVTER_EVTE16: u32 = 65536;
pub const INTC_EVTER_EVTE17_POS: u32 = 17;
pub const INTC_EVTER_EVTE17: u32 = 131072;
pub const INTC_EVTER_EVTE18_POS: u32 = 18;
pub const INTC_EVTER_EVTE18: u32 = 262144;
pub const INTC_EVTER_EVTE19_POS: u32 = 19;
pub const INTC_EVTER_EVTE19: u32 = 524288;
pub const INTC_EVTER_EVTE20_POS: u32 = 20;
pub const INTC_EVTER_EVTE20: u32 = 1048576;
pub const INTC_EVTER_EVTE21_POS: u32 = 21;
pub const INTC_EVTER_EVTE21: u32 = 2097152;
pub const INTC_EVTER_EVTE22_POS: u32 = 22;
pub const INTC_EVTER_EVTE22: u32 = 4194304;
pub const INTC_EVTER_EVTE23_POS: u32 = 23;
pub const INTC_EVTER_EVTE23: u32 = 8388608;
pub const INTC_EVTER_EVTE24_POS: u32 = 24;
pub const INTC_EVTER_EVTE24: u32 = 16777216;
pub const INTC_EVTER_EVTE25_POS: u32 = 25;
pub const INTC_EVTER_EVTE25: u32 = 33554432;
pub const INTC_EVTER_EVTE26_POS: u32 = 26;
pub const INTC_EVTER_EVTE26: u32 = 67108864;
pub const INTC_EVTER_EVTE27_POS: u32 = 27;
pub const INTC_EVTER_EVTE27: u32 = 134217728;
pub const INTC_EVTER_EVTE28_POS: u32 = 28;
pub const INTC_EVTER_EVTE28: u32 = 268435456;
pub const INTC_EVTER_EVTE29_POS: u32 = 29;
pub const INTC_EVTER_EVTE29: u32 = 536870912;
pub const INTC_EVTER_EVTE30_POS: u32 = 30;
pub const INTC_EVTER_EVTE30: u32 = 1073741824;
pub const INTC_EVTER_EVTE31_POS: u32 = 31;
pub const INTC_EVTER_EVTE31: u32 = 2147483648;
pub const INTC_IER_IER0_POS: u32 = 0;
pub const INTC_IER_IER0: u32 = 1;
pub const INTC_IER_IER1_POS: u32 = 1;
pub const INTC_IER_IER1: u32 = 2;
pub const INTC_IER_IER2_POS: u32 = 2;
pub const INTC_IER_IER2: u32 = 4;
pub const INTC_IER_IER3_POS: u32 = 3;
pub const INTC_IER_IER3: u32 = 8;
pub const INTC_IER_IER4_POS: u32 = 4;
pub const INTC_IER_IER4: u32 = 16;
pub const INTC_IER_IER5_POS: u32 = 5;
pub const INTC_IER_IER5: u32 = 32;
pub const INTC_IER_IER6_POS: u32 = 6;
pub const INTC_IER_IER6: u32 = 64;
pub const INTC_IER_IER7_POS: u32 = 7;
pub const INTC_IER_IER7: u32 = 128;
pub const INTC_IER_IER8_POS: u32 = 8;
pub const INTC_IER_IER8: u32 = 256;
pub const INTC_IER_IER9_POS: u32 = 9;
pub const INTC_IER_IER9: u32 = 512;
pub const INTC_IER_IER10_POS: u32 = 10;
pub const INTC_IER_IER10: u32 = 1024;
pub const INTC_IER_IER11_POS: u32 = 11;
pub const INTC_IER_IER11: u32 = 2048;
pub const INTC_IER_IER12_POS: u32 = 12;
pub const INTC_IER_IER12: u32 = 4096;
pub const INTC_IER_IER13_POS: u32 = 13;
pub const INTC_IER_IER13: u32 = 8192;
pub const INTC_IER_IER14_POS: u32 = 14;
pub const INTC_IER_IER14: u32 = 16384;
pub const INTC_IER_IER15_POS: u32 = 15;
pub const INTC_IER_IER15: u32 = 32768;
pub const INTC_IER_IER16_POS: u32 = 16;
pub const INTC_IER_IER16: u32 = 65536;
pub const INTC_IER_IER17_POS: u32 = 17;
pub const INTC_IER_IER17: u32 = 131072;
pub const INTC_IER_IER18_POS: u32 = 18;
pub const INTC_IER_IER18: u32 = 262144;
pub const INTC_IER_IER19_POS: u32 = 19;
pub const INTC_IER_IER19: u32 = 524288;
pub const INTC_IER_IER20_POS: u32 = 20;
pub const INTC_IER_IER20: u32 = 1048576;
pub const INTC_IER_IER21_POS: u32 = 21;
pub const INTC_IER_IER21: u32 = 2097152;
pub const INTC_IER_IER22_POS: u32 = 22;
pub const INTC_IER_IER22: u32 = 4194304;
pub const INTC_IER_IER23_POS: u32 = 23;
pub const INTC_IER_IER23: u32 = 8388608;
pub const INTC_IER_IER24_POS: u32 = 24;
pub const INTC_IER_IER24: u32 = 16777216;
pub const INTC_IER_IER25_POS: u32 = 25;
pub const INTC_IER_IER25: u32 = 33554432;
pub const INTC_IER_IER26_POS: u32 = 26;
pub const INTC_IER_IER26: u32 = 67108864;
pub const INTC_IER_IER27_POS: u32 = 27;
pub const INTC_IER_IER27: u32 = 134217728;
pub const INTC_IER_IER28_POS: u32 = 28;
pub const INTC_IER_IER28: u32 = 268435456;
pub const INTC_IER_IER29_POS: u32 = 29;
pub const INTC_IER_IER29: u32 = 536870912;
pub const INTC_IER_IER30_POS: u32 = 30;
pub const INTC_IER_IER30: u32 = 1073741824;
pub const INTC_IER_IER31_POS: u32 = 31;
pub const INTC_IER_IER31: u32 = 2147483648;
pub const KEYSCAN_SCR_KEYINSEL_POS: u32 = 0;
pub const KEYSCAN_SCR_KEYINSEL: u32 = 65535;
pub const KEYSCAN_SCR_KEYOUTSEL_POS: u32 = 16;
pub const KEYSCAN_SCR_KEYOUTSEL: u32 = 458752;
pub const KEYSCAN_SCR_CKSEL_POS: u32 = 20;
pub const KEYSCAN_SCR_CKSEL: u32 = 3145728;
pub const KEYSCAN_SCR_CKSEL_0: u32 = 1048576;
pub const KEYSCAN_SCR_CKSEL_1: u32 = 2097152;
pub const KEYSCAN_SCR_T_LLEVEL_POS: u32 = 24;
pub const KEYSCAN_SCR_T_LLEVEL: u32 = 520093696;
pub const KEYSCAN_SCR_T_HIZ_POS: u32 = 29;
pub const KEYSCAN_SCR_T_HIZ: u32 = 3758096384;
pub const KEYSCAN_SER_SEN: u32 = 1;
pub const KEYSCAN_SSR_INDEX: u32 = 7;
pub const MPU_RGD_MPURGSIZE_POS: u32 = 0;
pub const MPU_RGD_MPURGSIZE: u32 = 31;
pub const MPU_RGD_MPURGADDR_POS: u32 = 5;
pub const MPU_RGD_MPURGADDR: u32 = 4294967264;
pub const MPU_RGCR_S2RGRP_POS: u32 = 0;
pub const MPU_RGCR_S2RGRP: u32 = 1;
pub const MPU_RGCR_S2RGWP_POS: u32 = 1;
pub const MPU_RGCR_S2RGWP: u32 = 2;
pub const MPU_RGCR_S2RGE_POS: u32 = 7;
pub const MPU_RGCR_S2RGE: u32 = 128;
pub const MPU_RGCR_S1RGRP_POS: u32 = 8;
pub const MPU_RGCR_S1RGRP: u32 = 256;
pub const MPU_RGCR_S1RGWP_POS: u32 = 9;
pub const MPU_RGCR_S1RGWP: u32 = 512;
pub const MPU_RGCR_S1RGE_POS: u32 = 15;
pub const MPU_RGCR_S1RGE: u32 = 32768;
pub const MPU_RGCR_FRGRP_POS: u32 = 16;
pub const MPU_RGCR_FRGRP: u32 = 65536;
pub const MPU_RGCR_FRGWP_POS: u32 = 17;
pub const MPU_RGCR_FRGWP: u32 = 131072;
pub const MPU_RGCR_FRGE_POS: u32 = 23;
pub const MPU_RGCR_FRGE: u32 = 8388608;
pub const MPU_CR_SMPU2BRP_POS: u32 = 0;
pub const MPU_CR_SMPU2BRP: u32 = 1;
pub const MPU_CR_SMPU2BWP_POS: u32 = 1;
pub const MPU_CR_SMPU2BWP: u32 = 2;
pub const MPU_CR_SMPU2ACT_POS: u32 = 2;
pub const MPU_CR_SMPU2ACT: u32 = 12;
pub const MPU_CR_SMPU2ACT_0: u32 = 4;
pub const MPU_CR_SMPU2ACT_1: u32 = 8;
pub const MPU_CR_SMPU2E_POS: u32 = 7;
pub const MPU_CR_SMPU2E: u32 = 128;
pub const MPU_CR_SMPU1BRP_POS: u32 = 8;
pub const MPU_CR_SMPU1BRP: u32 = 256;
pub const MPU_CR_SMPU1BWP_POS: u32 = 9;
pub const MPU_CR_SMPU1BWP: u32 = 512;
pub const MPU_CR_SMPU1ACT_POS: u32 = 10;
pub const MPU_CR_SMPU1ACT: u32 = 3072;
pub const MPU_CR_SMPU1ACT_0: u32 = 1024;
pub const MPU_CR_SMPU1ACT_1: u32 = 2048;
pub const MPU_CR_SMPU1E_POS: u32 = 15;
pub const MPU_CR_SMPU1E: u32 = 32768;
pub const MPU_CR_FMPUBRP_POS: u32 = 16;
pub const MPU_CR_FMPUBRP: u32 = 65536;
pub const MPU_CR_FMPUBWP_POS: u32 = 17;
pub const MPU_CR_FMPUBWP: u32 = 131072;
pub const MPU_CR_FMPUACT_POS: u32 = 18;
pub const MPU_CR_FMPUACT: u32 = 786432;
pub const MPU_CR_FMPUACT_0: u32 = 262144;
pub const MPU_CR_FMPUACT_1: u32 = 524288;
pub const MPU_CR_FMPUE_POS: u32 = 23;
pub const MPU_CR_FMPUE: u32 = 8388608;
pub const MPU_SR_SMPU2EAF_POS: u32 = 0;
pub const MPU_SR_SMPU2EAF: u32 = 1;
pub const MPU_SR_SMPU1EAF_POS: u32 = 8;
pub const MPU_SR_SMPU1EAF: u32 = 256;
pub const MPU_SR_FMPUEAF_POS: u32 = 16;
pub const MPU_SR_FMPUEAF: u32 = 65536;
pub const MPU_ECLR_SMPU2ECLR_POS: u32 = 0;
pub const MPU_ECLR_SMPU2ECLR: u32 = 1;
pub const MPU_ECLR_SMPU1ECLR_POS: u32 = 8;
pub const MPU_ECLR_SMPU1ECLR: u32 = 256;
pub const MPU_ECLR_FMPUECLR_POS: u32 = 16;
pub const MPU_ECLR_FMPUECLR: u32 = 65536;
pub const MPU_WP_MPUWE_POS: u32 = 0;
pub const MPU_WP_MPUWE: u32 = 1;
pub const MPU_WP_WKEY_POS: u32 = 1;
pub const MPU_WP_WKEY: u32 = 65534;
pub const MPU_IPPR_AESRDP_POS: u32 = 0;
pub const MPU_IPPR_AESRDP: u32 = 1;
pub const MPU_IPPR_AESWRP_POS: u32 = 1;
pub const MPU_IPPR_AESWRP: u32 = 2;
pub const MPU_IPPR_HASHRDP_POS: u32 = 2;
pub const MPU_IPPR_HASHRDP: u32 = 4;
pub const MPU_IPPR_HASHWRP_POS: u32 = 3;
pub const MPU_IPPR_HASHWRP: u32 = 8;
pub const MPU_IPPR_TRNGRDP_POS: u32 = 4;
pub const MPU_IPPR_TRNGRDP: u32 = 16;
pub const MPU_IPPR_TRNGWRP_POS: u32 = 5;
pub const MPU_IPPR_TRNGWRP: u32 = 32;
pub const MPU_IPPR_CRCRDP_POS: u32 = 6;
pub const MPU_IPPR_CRCRDP: u32 = 64;
pub const MPU_IPPR_CRCWRP_POS: u32 = 7;
pub const MPU_IPPR_CRCWRP: u32 = 128;
pub const MPU_IPPR_EFMRDP_POS: u32 = 8;
pub const MPU_IPPR_EFMRDP: u32 = 256;
pub const MPU_IPPR_EFMWRP_POS: u32 = 9;
pub const MPU_IPPR_EFMWRP: u32 = 512;
pub const MPU_IPPR_WDTRDP_POS: u32 = 12;
pub const MPU_IPPR_WDTRDP: u32 = 4096;
pub const MPU_IPPR_WDTWRP_POS: u32 = 13;
pub const MPU_IPPR_WDTWRP: u32 = 8192;
pub const MPU_IPPR_SWDTRDP_POS: u32 = 14;
pub const MPU_IPPR_SWDTRDP: u32 = 16384;
pub const MPU_IPPR_SWDTWRP_POS: u32 = 15;
pub const MPU_IPPR_SWDTWRP: u32 = 32768;
pub const MPU_IPPR_BKSRAMRDP_POS: u32 = 16;
pub const MPU_IPPR_BKSRAMRDP: u32 = 65536;
pub const MPU_IPPR_BKSRAMWRP_POS: u32 = 17;
pub const MPU_IPPR_BKSRAMWRP: u32 = 131072;
pub const MPU_IPPR_RTCRDP_POS: u32 = 18;
pub const MPU_IPPR_RTCRDP: u32 = 262144;
pub const MPU_IPPR_RTCWRP_POS: u32 = 19;
pub const MPU_IPPR_RTCWRP: u32 = 524288;
pub const MPU_IPPR_DMPURDP_POS: u32 = 20;
pub const MPU_IPPR_DMPURDP: u32 = 1048576;
pub const MPU_IPPR_DMPUWRP_POS: u32 = 21;
pub const MPU_IPPR_DMPUWRP: u32 = 2097152;
pub const MPU_IPPR_SRAMCRDP_POS: u32 = 22;
pub const MPU_IPPR_SRAMCRDP: u32 = 4194304;
pub const MPU_IPPR_SRAMCWRP_POS: u32 = 23;
pub const MPU_IPPR_SRAMCWRP: u32 = 8388608;
pub const MPU_IPPR_INTCRDP_POS: u32 = 24;
pub const MPU_IPPR_INTCRDP: u32 = 16777216;
pub const MPU_IPPR_INTCWRP_POS: u32 = 25;
pub const MPU_IPPR_INTCWRP: u32 = 33554432;
pub const MPU_IPPR_SYSCRDP_POS: u32 = 26;
pub const MPU_IPPR_SYSCRDP: u32 = 67108864;
pub const MPU_IPPR_SYSCWRP_POS: u32 = 27;
pub const MPU_IPPR_SYSCWRP: u32 = 134217728;
pub const MPU_IPPR_MSTPRDP_POS: u32 = 28;
pub const MPU_IPPR_MSTPRDP: u32 = 268435456;
pub const MPU_IPPR_MSTPWRP_POS: u32 = 29;
pub const MPU_IPPR_MSTPWRP: u32 = 536870912;
pub const MPU_IPPR_BUSERRE_POS: u32 = 31;
pub const MPU_IPPR_BUSERRE: u32 = 2147483648;
pub const OTS_CTL_OTSST_POS: u32 = 0;
pub const OTS_CTL_OTSST: u32 = 1;
pub const OTS_CTL_OTSCK_POS: u32 = 1;
pub const OTS_CTL_OTSCK: u32 = 2;
pub const OTS_CTL_OTSIE_POS: u32 = 2;
pub const OTS_CTL_OTSIE: u32 = 4;
pub const OTS_CTL_TSSTP_POS: u32 = 3;
pub const OTS_CTL_TSSTP: u32 = 8;
pub const OTS_DR1: u32 = 65535;
pub const OTS_DR2: u32 = 65535;
pub const OTS_ECR: u32 = 65535;
pub const PERIC_USBFS_SYCTLREG_DFB_POS: u32 = 0;
pub const PERIC_USBFS_SYCTLREG_DFB: u32 = 1;
pub const PERIC_USBFS_SYCTLREG_SOFEN_POS: u32 = 1;
pub const PERIC_USBFS_SYCTLREG_SOFEN: u32 = 2;
pub const PERIC_SDIOC_SYCTLREG_SELMMC1_POS: u32 = 1;
pub const PERIC_SDIOC_SYCTLREG_SELMMC1: u32 = 2;
pub const PERIC_SDIOC_SYCTLREG_SELMMC2_POS: u32 = 3;
pub const PERIC_SDIOC_SYCTLREG_SELMMC2: u32 = 8;
pub const PWC_FCG0_SRAMH_POS: u32 = 0;
pub const PWC_FCG0_SRAMH: u32 = 1;
pub const PWC_FCG0_SRAM12_POS: u32 = 4;
pub const PWC_FCG0_SRAM12: u32 = 16;
pub const PWC_FCG0_SRAM3_POS: u32 = 8;
pub const PWC_FCG0_SRAM3: u32 = 256;
pub const PWC_FCG0_SRAMRET_POS: u32 = 10;
pub const PWC_FCG0_SRAMRET: u32 = 1024;
pub const PWC_FCG0_DMA1_POS: u32 = 14;
pub const PWC_FCG0_DMA1: u32 = 16384;
pub const PWC_FCG0_DMA2_POS: u32 = 15;
pub const PWC_FCG0_DMA2: u32 = 32768;
pub const PWC_FCG0_FCM_POS: u32 = 16;
pub const PWC_FCG0_FCM: u32 = 65536;
pub const PWC_FCG0_AOS_POS: u32 = 17;
pub const PWC_FCG0_AOS: u32 = 131072;
pub const PWC_FCG0_AES_POS: u32 = 20;
pub const PWC_FCG0_AES: u32 = 1048576;
pub const PWC_FCG0_HASH_POS: u32 = 21;
pub const PWC_FCG0_HASH: u32 = 2097152;
pub const PWC_FCG0_TRNG_POS: u32 = 22;
pub const PWC_FCG0_TRNG: u32 = 4194304;
pub const PWC_FCG0_CRC_POS: u32 = 23;
pub const PWC_FCG0_CRC: u32 = 8388608;
pub const PWC_FCG0_DCU1_POS: u32 = 24;
pub const PWC_FCG0_DCU1: u32 = 16777216;
pub const PWC_FCG0_DCU2_POS: u32 = 25;
pub const PWC_FCG0_DCU2: u32 = 33554432;
pub const PWC_FCG0_DCU3_POS: u32 = 26;
pub const PWC_FCG0_DCU3: u32 = 67108864;
pub const PWC_FCG0_DCU4_POS: u32 = 27;
pub const PWC_FCG0_DCU4: u32 = 134217728;
pub const PWC_FCG0_KEY_POS: u32 = 31;
pub const PWC_FCG0_KEY: u32 = 2147483648;
pub const PWC_FCG1_CAN_POS: u32 = 0;
pub const PWC_FCG1_CAN: u32 = 1;
pub const PWC_FCG1_QSPI_POS: u32 = 3;
pub const PWC_FCG1_QSPI: u32 = 8;
pub const PWC_FCG1_I2C1_POS: u32 = 4;
pub const PWC_FCG1_I2C1: u32 = 16;
pub const PWC_FCG1_I2C2_POS: u32 = 5;
pub const PWC_FCG1_I2C2: u32 = 32;
pub const PWC_FCG1_I2C3_POS: u32 = 6;
pub const PWC_FCG1_I2C3: u32 = 64;
pub const PWC_FCG1_USBFS_POS: u32 = 8;
pub const PWC_FCG1_USBFS: u32 = 256;
pub const PWC_FCG1_SDIOC1_POS: u32 = 10;
pub const PWC_FCG1_SDIOC1: u32 = 1024;
pub const PWC_FCG1_SDIOC2_POS: u32 = 11;
pub const PWC_FCG1_SDIOC2: u32 = 2048;
pub const PWC_FCG1_I2S1_POS: u32 = 12;
pub const PWC_FCG1_I2S1: u32 = 4096;
pub const PWC_FCG1_I2S2_POS: u32 = 13;
pub const PWC_FCG1_I2S2: u32 = 8192;
pub const PWC_FCG1_I2S3_POS: u32 = 14;
pub const PWC_FCG1_I2S3: u32 = 16384;
pub const PWC_FCG1_I2S4_POS: u32 = 15;
pub const PWC_FCG1_I2S4: u32 = 32768;
pub const PWC_FCG1_SPI1_POS: u32 = 16;
pub const PWC_FCG1_SPI1: u32 = 65536;
pub const PWC_FCG1_SPI2_POS: u32 = 17;
pub const PWC_FCG1_SPI2: u32 = 131072;
pub const PWC_FCG1_SPI3_POS: u32 = 18;
pub const PWC_FCG1_SPI3: u32 = 262144;
pub const PWC_FCG1_SPI4_POS: u32 = 19;
pub const PWC_FCG1_SPI4: u32 = 524288;
pub const PWC_FCG1_USART1_POS: u32 = 24;
pub const PWC_FCG1_USART1: u32 = 16777216;
pub const PWC_FCG1_USART2_POS: u32 = 25;
pub const PWC_FCG1_USART2: u32 = 33554432;
pub const PWC_FCG1_USART3_POS: u32 = 26;
pub const PWC_FCG1_USART3: u32 = 67108864;
pub const PWC_FCG1_USART4_POS: u32 = 27;
pub const PWC_FCG1_USART4: u32 = 134217728;
pub const PWC_FCG2_TIMER0_1_POS: u32 = 0;
pub const PWC_FCG2_TIMER0_1: u32 = 1;
pub const PWC_FCG2_TIMER0_2_POS: u32 = 1;
pub const PWC_FCG2_TIMER0_2: u32 = 2;
pub const PWC_FCG2_TIMERA_1_POS: u32 = 2;
pub const PWC_FCG2_TIMERA_1: u32 = 4;
pub const PWC_FCG2_TIMERA_2_POS: u32 = 3;
pub const PWC_FCG2_TIMERA_2: u32 = 8;
pub const PWC_FCG2_TIMERA_3_POS: u32 = 4;
pub const PWC_FCG2_TIMERA_3: u32 = 16;
pub const PWC_FCG2_TIMERA_4_POS: u32 = 5;
pub const PWC_FCG2_TIMERA_4: u32 = 32;
pub const PWC_FCG2_TIMERA_5_POS: u32 = 6;
pub const PWC_FCG2_TIMERA_5: u32 = 64;
pub const PWC_FCG2_TIMERA_6_POS: u32 = 7;
pub const PWC_FCG2_TIMERA_6: u32 = 128;
pub const PWC_FCG2_TIMER4_1_POS: u32 = 8;
pub const PWC_FCG2_TIMER4_1: u32 = 256;
pub const PWC_FCG2_TIMER4_2_POS: u32 = 9;
pub const PWC_FCG2_TIMER4_2: u32 = 512;
pub const PWC_FCG2_TIMER4_3_POS: u32 = 10;
pub const PWC_FCG2_TIMER4_3: u32 = 1024;
pub const PWC_FCG2_EMB_POS: u32 = 15;
pub const PWC_FCG2_EMB: u32 = 32768;
pub const PWC_FCG2_TIMER6_1_POS: u32 = 16;
pub const PWC_FCG2_TIMER6_1: u32 = 65536;
pub const PWC_FCG2_TIMER6_2_POS: u32 = 17;
pub const PWC_FCG2_TIMER6_2: u32 = 131072;
pub const PWC_FCG2_TIMER6_3_POS: u32 = 18;
pub const PWC_FCG2_TIMER6_3: u32 = 262144;
pub const PWC_FCG3_ADC1_POS: u32 = 0;
pub const PWC_FCG3_ADC1: u32 = 1;
pub const PWC_FCG3_ADC2_POS: u32 = 1;
pub const PWC_FCG3_ADC2: u32 = 2;
pub const PWC_FCG3_CMP_POS: u32 = 8;
pub const PWC_FCG3_CMP: u32 = 256;
pub const PWC_FCG3_OTS_POS: u32 = 12;
pub const PWC_FCG3_OTS: u32 = 4096;
pub const PWC_FCG0PC_PRT0_POS: u32 = 0;
pub const PWC_FCG0PC_PRT0: u32 = 1;
pub const PWC_FCG0PC_FCG0PCWE_POS: u32 = 16;
pub const PWC_FCG0PC_FCG0PCWE: u32 = 4294901760;
pub const PWC_WKTCR_WKTMCMP_POS: u32 = 0;
pub const PWC_WKTCR_WKTMCMP: u32 = 4095;
pub const PWC_WKTCR_WKOVF_POS: u32 = 12;
pub const PWC_WKTCR_WKOVF: u32 = 4096;
pub const PWC_WKTCR_WKCKS_POS: u32 = 13;
pub const PWC_WKTCR_WKCKS: u32 = 24576;
pub const PWC_WKTCR_WKCKS_0: u32 = 8192;
pub const PWC_WKTCR_WKCKS_1: u32 = 16384;
pub const PWC_WKTCR_WKTCE_POS: u32 = 15;
pub const PWC_WKTCR_WKTCE: u32 = 32768;
pub const PWC_STPMCR_FLNWT_POS: u32 = 0;
pub const PWC_STPMCR_FLNWT: u32 = 1;
pub const PWC_STPMCR_CKSMRC_POS: u32 = 1;
pub const PWC_STPMCR_CKSMRC: u32 = 2;
pub const PWC_STPMCR_STOP_POS: u32 = 15;
pub const PWC_STPMCR_STOP: u32 = 32768;
pub const PWC_RAMPC0_RAMPDC0_POS: u32 = 0;
pub const PWC_RAMPC0_RAMPDC0: u32 = 1;
pub const PWC_RAMPC0_RAMPDC1_POS: u32 = 1;
pub const PWC_RAMPC0_RAMPDC1: u32 = 2;
pub const PWC_RAMPC0_RAMPDC2_POS: u32 = 2;
pub const PWC_RAMPC0_RAMPDC2: u32 = 4;
pub const PWC_RAMPC0_RAMPDC3_POS: u32 = 3;
pub const PWC_RAMPC0_RAMPDC3: u32 = 8;
pub const PWC_RAMPC0_RAMPDC4_POS: u32 = 4;
pub const PWC_RAMPC0_RAMPDC4: u32 = 16;
pub const PWC_RAMPC0_RAMPDC5_POS: u32 = 5;
pub const PWC_RAMPC0_RAMPDC5: u32 = 32;
pub const PWC_RAMPC0_RAMPDC6_POS: u32 = 6;
pub const PWC_RAMPC0_RAMPDC6: u32 = 64;
pub const PWC_RAMPC0_RAMPDC7_POS: u32 = 7;
pub const PWC_RAMPC0_RAMPDC7: u32 = 128;
pub const PWC_RAMPC0_RAMPDC8_POS: u32 = 8;
pub const PWC_RAMPC0_RAMPDC8: u32 = 256;
pub const PWC_RAMOPM: u32 = 65535;
pub const PWC_PVDICR_PVD1NMIS_POS: u32 = 0;
pub const PWC_PVDICR_PVD1NMIS: u32 = 1;
pub const PWC_PVDICR_PVD2NMIS_POS: u32 = 4;
pub const PWC_PVDICR_PVD2NMIS: u32 = 16;
pub const PWC_PVDDSR_PVD1MON_POS: u32 = 0;
pub const PWC_PVDDSR_PVD1MON: u32 = 1;
pub const PWC_PVDDSR_PVD1DETFLG_POS: u32 = 1;
pub const PWC_PVDDSR_PVD1DETFLG: u32 = 2;
pub const PWC_PVDDSR_PVD2MON_POS: u32 = 4;
pub const PWC_PVDDSR_PVD2MON: u32 = 16;
pub const PWC_PVDDSR_PVD2DETFLG_POS: u32 = 5;
pub const PWC_PVDDSR_PVD2DETFLG: u32 = 32;
pub const PWC_FPRC_FPRCB0_POS: u32 = 0;
pub const PWC_FPRC_FPRCB0: u32 = 1;
pub const PWC_FPRC_FPRCB1_POS: u32 = 1;
pub const PWC_FPRC_FPRCB1: u32 = 2;
pub const PWC_FPRC_FPRCB2_POS: u32 = 2;
pub const PWC_FPRC_FPRCB2: u32 = 4;
pub const PWC_FPRC_FPRCB3_POS: u32 = 3;
pub const PWC_FPRC_FPRCB3: u32 = 8;
pub const PWC_FPRC_FPRCWE_POS: u32 = 8;
pub const PWC_FPRC_FPRCWE: u32 = 65280;
pub const PWC_PWRC0_PDMDS_POS: u32 = 0;
pub const PWC_PWRC0_PDMDS: u32 = 3;
pub const PWC_PWRC0_PDMDS_0: u32 = 1;
pub const PWC_PWRC0_PDMDS_1: u32 = 2;
pub const PWC_PWRC0_VVDRSD_POS: u32 = 2;
pub const PWC_PWRC0_VVDRSD: u32 = 4;
pub const PWC_PWRC0_RETRAMSD_POS: u32 = 3;
pub const PWC_PWRC0_RETRAMSD: u32 = 8;
pub const PWC_PWRC0_IORTN_POS: u32 = 4;
pub const PWC_PWRC0_IORTN: u32 = 48;
pub const PWC_PWRC0_IORTN_0: u32 = 16;
pub const PWC_PWRC0_IORTN_1: u32 = 32;
pub const PWC_PWRC0_PWDN_POS: u32 = 7;
pub const PWC_PWRC0_PWDN: u32 = 128;
pub const PWC_PWRC1_VPLLSD_POS: u32 = 0;
pub const PWC_PWRC1_VPLLSD: u32 = 1;
pub const PWC_PWRC1_VHRCSD_POS: u32 = 1;
pub const PWC_PWRC1_VHRCSD: u32 = 2;
pub const PWC_PWRC1_STPDAS_POS: u32 = 6;
pub const PWC_PWRC1_STPDAS: u32 = 192;
pub const PWC_PWRC1_STPDAS_0: u32 = 64;
pub const PWC_PWRC1_STPDAS_1: u32 = 128;
pub const PWC_PWRC2_DDAS_POS: u32 = 0;
pub const PWC_PWRC2_DDAS: u32 = 15;
pub const PWC_PWRC2_DDAS_0: u32 = 1;
pub const PWC_PWRC2_DDAS_1: u32 = 2;
pub const PWC_PWRC2_DDAS_2: u32 = 4;
pub const PWC_PWRC2_DDAS_3: u32 = 8;
pub const PWC_PWRC2_DVS_POS: u32 = 4;
pub const PWC_PWRC2_DVS: u32 = 48;
pub const PWC_PWRC2_DVS_0: u32 = 16;
pub const PWC_PWRC2_DVS_1: u32 = 32;
pub const PWC_PWRC3_PDTS_POS: u32 = 2;
pub const PWC_PWRC3_PDTS: u32 = 4;
pub const PWC_PDWKE0_WKE00_POS: u32 = 0;
pub const PWC_PDWKE0_WKE00: u32 = 1;
pub const PWC_PDWKE0_WKE01_POS: u32 = 1;
pub const PWC_PDWKE0_WKE01: u32 = 2;
pub const PWC_PDWKE0_WKE02_POS: u32 = 2;
pub const PWC_PDWKE0_WKE02: u32 = 4;
pub const PWC_PDWKE0_WKE03_POS: u32 = 3;
pub const PWC_PDWKE0_WKE03: u32 = 8;
pub const PWC_PDWKE0_WKE10_POS: u32 = 4;
pub const PWC_PDWKE0_WKE10: u32 = 16;
pub const PWC_PDWKE0_WKE11_POS: u32 = 5;
pub const PWC_PDWKE0_WKE11: u32 = 32;
pub const PWC_PDWKE0_WKE12_POS: u32 = 6;
pub const PWC_PDWKE0_WKE12: u32 = 64;
pub const PWC_PDWKE0_WKE13_POS: u32 = 7;
pub const PWC_PDWKE0_WKE13: u32 = 128;
pub const PWC_PDWKE1_WKE20_POS: u32 = 0;
pub const PWC_PDWKE1_WKE20: u32 = 1;
pub const PWC_PDWKE1_WKE21_POS: u32 = 1;
pub const PWC_PDWKE1_WKE21: u32 = 2;
pub const PWC_PDWKE1_WKE22_POS: u32 = 2;
pub const PWC_PDWKE1_WKE22: u32 = 4;
pub const PWC_PDWKE1_WKE23_POS: u32 = 3;
pub const PWC_PDWKE1_WKE23: u32 = 8;
pub const PWC_PDWKE1_WKE30_POS: u32 = 4;
pub const PWC_PDWKE1_WKE30: u32 = 16;
pub const PWC_PDWKE1_WKE31_POS: u32 = 5;
pub const PWC_PDWKE1_WKE31: u32 = 32;
pub const PWC_PDWKE1_WKE32_POS: u32 = 6;
pub const PWC_PDWKE1_WKE32: u32 = 64;
pub const PWC_PDWKE1_WKE33_POS: u32 = 7;
pub const PWC_PDWKE1_WKE33: u32 = 128;
pub const PWC_PDWKE2_VD1WKE_POS: u32 = 0;
pub const PWC_PDWKE2_VD1WKE: u32 = 1;
pub const PWC_PDWKE2_VD2WKE_POS: u32 = 1;
pub const PWC_PDWKE2_VD2WKE: u32 = 2;
pub const PWC_PDWKE2_NMIWKE_POS: u32 = 2;
pub const PWC_PDWKE2_NMIWKE: u32 = 4;
pub const PWC_PDWKE2_RTCPRDWKE_POS: u32 = 4;
pub const PWC_PDWKE2_RTCPRDWKE: u32 = 16;
pub const PWC_PDWKE2_RTCALMWKE_POS: u32 = 5;
pub const PWC_PDWKE2_RTCALMWKE: u32 = 32;
pub const PWC_PDWKE2_WKTMWKE_POS: u32 = 7;
pub const PWC_PDWKE2_WKTMWKE: u32 = 128;
pub const PWC_PDWKES_WK0EGS_POS: u32 = 0;
pub const PWC_PDWKES_WK0EGS: u32 = 1;
pub const PWC_PDWKES_WK1EGS_POS: u32 = 1;
pub const PWC_PDWKES_WK1EGS: u32 = 2;
pub const PWC_PDWKES_WK2EGS_POS: u32 = 2;
pub const PWC_PDWKES_WK2EGS: u32 = 4;
pub const PWC_PDWKES_WK3EGS_POS: u32 = 3;
pub const PWC_PDWKES_WK3EGS: u32 = 8;
pub const PWC_PDWKES_VD1EGS_POS: u32 = 4;
pub const PWC_PDWKES_VD1EGS: u32 = 16;
pub const PWC_PDWKES_VD2EGS_POS: u32 = 5;
pub const PWC_PDWKES_VD2EGS: u32 = 32;
pub const PWC_PDWKES_NMIEGS_POS: u32 = 6;
pub const PWC_PDWKES_NMIEGS: u32 = 64;
pub const PWC_PDWKF0_PTWK0F_POS: u32 = 0;
pub const PWC_PDWKF0_PTWK0F: u32 = 1;
pub const PWC_PDWKF0_PTWK1F_POS: u32 = 1;
pub const PWC_PDWKF0_PTWK1F: u32 = 2;
pub const PWC_PDWKF0_PTWK2F_POS: u32 = 2;
pub const PWC_PDWKF0_PTWK2F: u32 = 4;
pub const PWC_PDWKF0_PTWK3F_POS: u32 = 3;
pub const PWC_PDWKF0_PTWK3F: u32 = 8;
pub const PWC_PDWKF0_VD1WKF_POS: u32 = 4;
pub const PWC_PDWKF0_VD1WKF: u32 = 16;
pub const PWC_PDWKF0_VD2WKF_POS: u32 = 5;
pub const PWC_PDWKF0_VD2WKF: u32 = 32;
pub const PWC_PDWKF0_NMIWKF_POS: u32 = 6;
pub const PWC_PDWKF0_NMIWKF: u32 = 64;
pub const PWC_PDWKF1_RTCPRDWKF_POS: u32 = 4;
pub const PWC_PDWKF1_RTCPRDWKF: u32 = 16;
pub const PWC_PDWKF1_RTCALMWKF_POS: u32 = 5;
pub const PWC_PDWKF1_RTCALMWKF: u32 = 32;
pub const PWC_PDWKF1_WKTMWKF_POS: u32 = 7;
pub const PWC_PDWKF1_WKTMWKF: u32 = 128;
pub const PWC_PWCMR_ADBUFE_POS: u32 = 7;
pub const PWC_PWCMR_ADBUFE: u32 = 128;
pub const PWC_MDSWCR: u32 = 255;
pub const PWC_PVDCR0_EXVCCINEN_POS: u32 = 0;
pub const PWC_PVDCR0_EXVCCINEN: u32 = 1;
pub const PWC_PVDCR0_PVD1EN_POS: u32 = 5;
pub const PWC_PVDCR0_PVD1EN: u32 = 32;
pub const PWC_PVDCR0_PVD2EN_POS: u32 = 6;
pub const PWC_PVDCR0_PVD2EN: u32 = 64;
pub const PWC_PVDCR1_PVD1IRE_POS: u32 = 0;
pub const PWC_PVDCR1_PVD1IRE: u32 = 1;
pub const PWC_PVDCR1_PVD1IRS_POS: u32 = 1;
pub const PWC_PVDCR1_PVD1IRS: u32 = 2;
pub const PWC_PVDCR1_PVD1CMPOE_POS: u32 = 2;
pub const PWC_PVDCR1_PVD1CMPOE: u32 = 4;
pub const PWC_PVDCR1_PVD2IRE_POS: u32 = 4;
pub const PWC_PVDCR1_PVD2IRE: u32 = 16;
pub const PWC_PVDCR1_PVD2IRS_POS: u32 = 5;
pub const PWC_PVDCR1_PVD2IRS: u32 = 32;
pub const PWC_PVDCR1_PVD2CMPOE_POS: u32 = 6;
pub const PWC_PVDCR1_PVD2CMPOE: u32 = 64;
pub const PWC_PVDFCR_PVD1NFDIS_POS: u32 = 0;
pub const PWC_PVDFCR_PVD1NFDIS: u32 = 1;
pub const PWC_PVDFCR_PVD1NFCKS_POS: u32 = 1;
pub const PWC_PVDFCR_PVD1NFCKS: u32 = 6;
pub const PWC_PVDFCR_PVD1NFCKS_0: u32 = 2;
pub const PWC_PVDFCR_PVD1NFCKS_1: u32 = 4;
pub const PWC_PVDFCR_PVD2NFDIS_POS: u32 = 4;
pub const PWC_PVDFCR_PVD2NFDIS: u32 = 16;
pub const PWC_PVDFCR_PVD2NFCKS_POS: u32 = 5;
pub const PWC_PVDFCR_PVD2NFCKS: u32 = 96;
pub const PWC_PVDFCR_PVD2NFCKS_0: u32 = 32;
pub const PWC_PVDFCR_PVD2NFCKS_1: u32 = 64;
pub const PWC_PVDLCR_PVD1LVL_POS: u32 = 0;
pub const PWC_PVDLCR_PVD1LVL: u32 = 7;
pub const PWC_PVDLCR_PVD1LVL_0: u32 = 1;
pub const PWC_PVDLCR_PVD1LVL_1: u32 = 2;
pub const PWC_PVDLCR_PVD1LVL_2: u32 = 4;
pub const PWC_PVDLCR_PVD2LVL_POS: u32 = 4;
pub const PWC_PVDLCR_PVD2LVL: u32 = 112;
pub const PWC_PVDLCR_PVD2LVL_0: u32 = 16;
pub const PWC_PVDLCR_PVD2LVL_1: u32 = 32;
pub const PWC_PVDLCR_PVD2LVL_2: u32 = 64;
pub const PWC_XTAL32CS_CSDIS_POS: u32 = 7;
pub const PWC_XTAL32CS_CSDIS: u32 = 128;
pub const QSPI_CR_MDSEL_POS: u32 = 0;
pub const QSPI_CR_MDSEL: u32 = 7;
pub const QSPI_CR_PFE_POS: u32 = 3;
pub const QSPI_CR_PFE: u32 = 8;
pub const QSPI_CR_PFSAE_POS: u32 = 4;
pub const QSPI_CR_PFSAE: u32 = 16;
pub const QSPI_CR_DCOME_POS: u32 = 5;
pub const QSPI_CR_DCOME: u32 = 32;
pub const QSPI_CR_XIPE_POS: u32 = 6;
pub const QSPI_CR_XIPE: u32 = 64;
pub const QSPI_CR_SPIMD3_POS: u32 = 7;
pub const QSPI_CR_SPIMD3: u32 = 128;
pub const QSPI_CR_IPRSL_POS: u32 = 8;
pub const QSPI_CR_IPRSL: u32 = 768;
pub const QSPI_CR_IPRSL_0: u32 = 256;
pub const QSPI_CR_IPRSL_1: u32 = 512;
pub const QSPI_CR_APRSL_POS: u32 = 10;
pub const QSPI_CR_APRSL: u32 = 3072;
pub const QSPI_CR_APRSL_0: u32 = 1024;
pub const QSPI_CR_APRSL_1: u32 = 2048;
pub const QSPI_CR_DPRSL_POS: u32 = 12;
pub const QSPI_CR_DPRSL: u32 = 12288;
pub const QSPI_CR_DPRSL_0: u32 = 4096;
pub const QSPI_CR_DPRSL_1: u32 = 8192;
pub const QSPI_CR_DIV_POS: u32 = 16;
pub const QSPI_CR_DIV: u32 = 4128768;
pub const QSPI_CSCR_SSHW_POS: u32 = 0;
pub const QSPI_CSCR_SSHW: u32 = 15;
pub const QSPI_CSCR_SSNW_POS: u32 = 4;
pub const QSPI_CSCR_SSNW: u32 = 48;
pub const QSPI_CSCR_SSNW_0: u32 = 16;
pub const QSPI_CSCR_SSNW_1: u32 = 32;
pub const QSPI_FCR_AWSL_POS: u32 = 0;
pub const QSPI_FCR_AWSL: u32 = 3;
pub const QSPI_FCR_AWSL_0: u32 = 1;
pub const QSPI_FCR_AWSL_1: u32 = 2;
pub const QSPI_FCR_FOUR_BIC_POS: u32 = 2;
pub const QSPI_FCR_FOUR_BIC: u32 = 4;
pub const QSPI_FCR_SSNHD_POS: u32 = 4;
pub const QSPI_FCR_SSNHD: u32 = 16;
pub const QSPI_FCR_SSNLD_POS: u32 = 5;
pub const QSPI_FCR_SSNLD: u32 = 32;
pub const QSPI_FCR_WPOL_POS: u32 = 6;
pub const QSPI_FCR_WPOL: u32 = 64;
pub const QSPI_FCR_DMCYCN_POS: u32 = 8;
pub const QSPI_FCR_DMCYCN: u32 = 3840;
pub const QSPI_FCR_DUTY_POS: u32 = 15;
pub const QSPI_FCR_DUTY: u32 = 32768;
pub const QSPI_SR_BUSY_POS: u32 = 0;
pub const QSPI_SR_BUSY: u32 = 1;
pub const QSPI_SR_XIPF_POS: u32 = 6;
pub const QSPI_SR_XIPF: u32 = 64;
pub const QSPI_SR_RAER_POS: u32 = 7;
pub const QSPI_SR_RAER: u32 = 128;
pub const QSPI_SR_PFNUM_POS: u32 = 8;
pub const QSPI_SR_PFNUM: u32 = 7936;
pub const QSPI_SR_PFFUL_POS: u32 = 14;
pub const QSPI_SR_PFFUL: u32 = 16384;
pub const QSPI_SR_PFAN_POS: u32 = 15;
pub const QSPI_SR_PFAN: u32 = 32768;
pub const QSPI_DCOM_DCOM: u32 = 255;
pub const QSPI_CCMD_RIC: u32 = 255;
pub const QSPI_XCMD_XIPMC: u32 = 255;
pub const QSPI_CLR_RAERCLR_POS: u32 = 7;
pub const QSPI_CLR_RAERCLR: u32 = 128;
pub const QSPI_EXAR_EXADR_POS: u32 = 26;
pub const QSPI_EXAR_EXADR: u32 = 4227858432;
pub const RMU_RSTF0_PORF_POS: u32 = 0;
pub const RMU_RSTF0_PORF: u32 = 1;
pub const RMU_RSTF0_PINRF_POS: u32 = 1;
pub const RMU_RSTF0_PINRF: u32 = 2;
pub const RMU_RSTF0_BORF_POS: u32 = 2;
pub const RMU_RSTF0_BORF: u32 = 4;
pub const RMU_RSTF0_PVD1RF_POS: u32 = 3;
pub const RMU_RSTF0_PVD1RF: u32 = 8;
pub const RMU_RSTF0_PVD2RF_POS: u32 = 4;
pub const RMU_RSTF0_PVD2RF: u32 = 16;
pub const RMU_RSTF0_WDRF_POS: u32 = 5;
pub const RMU_RSTF0_WDRF: u32 = 32;
pub const RMU_RSTF0_SWDRF_POS: u32 = 6;
pub const RMU_RSTF0_SWDRF: u32 = 64;
pub const RMU_RSTF0_PDRF_POS: u32 = 7;
pub const RMU_RSTF0_PDRF: u32 = 128;
pub const RMU_RSTF0_SWRF_POS: u32 = 8;
pub const RMU_RSTF0_SWRF: u32 = 256;
pub const RMU_RSTF0_MPUERF_POS: u32 = 9;
pub const RMU_RSTF0_MPUERF: u32 = 512;
pub const RMU_RSTF0_RAPERF_POS: u32 = 10;
pub const RMU_RSTF0_RAPERF: u32 = 1024;
pub const RMU_RSTF0_RAECRF_POS: u32 = 11;
pub const RMU_RSTF0_RAECRF: u32 = 2048;
pub const RMU_RSTF0_CKFERF_POS: u32 = 12;
pub const RMU_RSTF0_CKFERF: u32 = 4096;
pub const RMU_RSTF0_XTALERF_POS: u32 = 13;
pub const RMU_RSTF0_XTALERF: u32 = 8192;
pub const RMU_RSTF0_MULTIRF_POS: u32 = 14;
pub const RMU_RSTF0_MULTIRF: u32 = 16384;
pub const RMU_RSTF0_CLRF_POS: u32 = 15;
pub const RMU_RSTF0_CLRF: u32 = 32768;
pub const RTC_CR0_RESET: u32 = 1;
pub const RTC_CR1_PRDS_POS: u32 = 0;
pub const RTC_CR1_PRDS: u32 = 7;
pub const RTC_CR1_AMPM_POS: u32 = 3;
pub const RTC_CR1_AMPM: u32 = 8;
pub const RTC_CR1_ALMFCLR_POS: u32 = 4;
pub const RTC_CR1_ALMFCLR: u32 = 16;
pub const RTC_CR1_ONEHZOE_POS: u32 = 5;
pub const RTC_CR1_ONEHZOE: u32 = 32;
pub const RTC_CR1_ONEHZSEL_POS: u32 = 6;
pub const RTC_CR1_ONEHZSEL: u32 = 64;
pub const RTC_CR1_START_POS: u32 = 7;
pub const RTC_CR1_START: u32 = 128;
pub const RTC_CR2_RWREQ_POS: u32 = 0;
pub const RTC_CR2_RWREQ: u32 = 1;
pub const RTC_CR2_RWEN_POS: u32 = 1;
pub const RTC_CR2_RWEN: u32 = 2;
pub const RTC_CR2_ALMF_POS: u32 = 3;
pub const RTC_CR2_ALMF: u32 = 8;
pub const RTC_CR2_PRDIE_POS: u32 = 5;
pub const RTC_CR2_PRDIE: u32 = 32;
pub const RTC_CR2_ALMIE_POS: u32 = 6;
pub const RTC_CR2_ALMIE: u32 = 64;
pub const RTC_CR2_ALME_POS: u32 = 7;
pub const RTC_CR2_ALME: u32 = 128;
pub const RTC_CR3_LRCEN_POS: u32 = 4;
pub const RTC_CR3_LRCEN: u32 = 16;
pub const RTC_CR3_RCKSEL_POS: u32 = 7;
pub const RTC_CR3_RCKSEL: u32 = 128;
pub const RTC_SEC_SECU_POS: u32 = 0;
pub const RTC_SEC_SECU: u32 = 15;
pub const RTC_SEC_SECD_POS: u32 = 4;
pub const RTC_SEC_SECD: u32 = 112;
pub const RTC_MIN_MINU_POS: u32 = 0;
pub const RTC_MIN_MINU: u32 = 15;
pub const RTC_MIN_MIND_POS: u32 = 4;
pub const RTC_MIN_MIND: u32 = 112;
pub const RTC_HOUR_HOURU_POS: u32 = 0;
pub const RTC_HOUR_HOURU: u32 = 15;
pub const RTC_HOUR_HOURU_0: u32 = 1;
pub const RTC_HOUR_HOURU_1: u32 = 2;
pub const RTC_HOUR_HOURU_2: u32 = 4;
pub const RTC_HOUR_HOURU_3: u32 = 8;
pub const RTC_HOUR_HOURD_POS: u32 = 4;
pub const RTC_HOUR_HOURD: u32 = 48;
pub const RTC_HOUR_HOURD_0: u32 = 16;
pub const RTC_HOUR_HOURD_1: u32 = 32;
pub const RTC_WEEK_WEEK: u32 = 7;
pub const RTC_DAY_DAYU_POS: u32 = 0;
pub const RTC_DAY_DAYU: u32 = 15;
pub const RTC_DAY_DAYD_POS: u32 = 4;
pub const RTC_DAY_DAYD: u32 = 48;
pub const RTC_MON_MON: u32 = 31;
pub const RTC_YEAR_YEARU_POS: u32 = 0;
pub const RTC_YEAR_YEARU: u32 = 15;
pub const RTC_YEAR_YEARD_POS: u32 = 4;
pub const RTC_YEAR_YEARD: u32 = 240;
pub const RTC_ALMMIN_ALMMINU_POS: u32 = 0;
pub const RTC_ALMMIN_ALMMINU: u32 = 15;
pub const RTC_ALMMIN_ALMMIND_POS: u32 = 4;
pub const RTC_ALMMIN_ALMMIND: u32 = 112;
pub const RTC_ALMHOUR_ALMHOURU_POS: u32 = 0;
pub const RTC_ALMHOUR_ALMHOURU: u32 = 15;
pub const RTC_ALMHOUR_ALMHOURD_POS: u32 = 4;
pub const RTC_ALMHOUR_ALMHOURD: u32 = 48;
pub const RTC_ALMHOUR_ALMHOURD_0: u32 = 16;
pub const RTC_ALMHOUR_ALMHOURD_1: u32 = 32;
pub const RTC_ALMWEEK_ALMWEEK: u32 = 127;
pub const RTC_ALMWEEK_ALMWEEK_0: u32 = 1;
pub const RTC_ALMWEEK_ALMWEEK_1: u32 = 2;
pub const RTC_ALMWEEK_ALMWEEK_2: u32 = 4;
pub const RTC_ALMWEEK_ALMWEEK_3: u32 = 8;
pub const RTC_ALMWEEK_ALMWEEK_4: u32 = 16;
pub const RTC_ALMWEEK_ALMWEEK_5: u32 = 32;
pub const RTC_ALMWEEK_ALMWEEK_6: u32 = 64;
pub const RTC_ERRCRH_COMP8_POS: u32 = 0;
pub const RTC_ERRCRH_COMP8: u32 = 1;
pub const RTC_ERRCRH_COMPEN_POS: u32 = 7;
pub const RTC_ERRCRH_COMPEN: u32 = 128;
pub const RTC_ERRCRL_COMP: u32 = 255;
pub const SDIOC_BLKSIZE_TBS: u32 = 4095;
pub const SDIOC_BLKCNT: u32 = 65535;
pub const SDIOC_ARG0: u32 = 65535;
pub const SDIOC_ARG1: u32 = 65535;
pub const SDIOC_TRANSMODE_BCE_POS: u32 = 1;
pub const SDIOC_TRANSMODE_BCE: u32 = 2;
pub const SDIOC_TRANSMODE_ATCEN_POS: u32 = 2;
pub const SDIOC_TRANSMODE_ATCEN: u32 = 12;
pub const SDIOC_TRANSMODE_ATCEN_0: u32 = 4;
pub const SDIOC_TRANSMODE_ATCEN_1: u32 = 8;
pub const SDIOC_TRANSMODE_DDIR_POS: u32 = 4;
pub const SDIOC_TRANSMODE_DDIR: u32 = 16;
pub const SDIOC_TRANSMODE_MULB_POS: u32 = 5;
pub const SDIOC_TRANSMODE_MULB: u32 = 32;
pub const SDIOC_CMD_RESTYP_POS: u32 = 0;
pub const SDIOC_CMD_RESTYP: u32 = 3;
pub const SDIOC_CMD_RESTYP_0: u32 = 1;
pub const SDIOC_CMD_RESTYP_1: u32 = 2;
pub const SDIOC_CMD_CCE_POS: u32 = 3;
pub const SDIOC_CMD_CCE: u32 = 8;
pub const SDIOC_CMD_ICE_POS: u32 = 4;
pub const SDIOC_CMD_ICE: u32 = 16;
pub const SDIOC_CMD_DAT_POS: u32 = 5;
pub const SDIOC_CMD_DAT: u32 = 32;
pub const SDIOC_CMD_TYP_POS: u32 = 6;
pub const SDIOC_CMD_TYP: u32 = 192;
pub const SDIOC_CMD_TYP_0: u32 = 64;
pub const SDIOC_CMD_TYP_1: u32 = 128;
pub const SDIOC_CMD_IDX_POS: u32 = 8;
pub const SDIOC_CMD_IDX: u32 = 16128;
pub const SDIOC_RESP0: u32 = 65535;
pub const SDIOC_RESP1: u32 = 65535;
pub const SDIOC_RESP2: u32 = 65535;
pub const SDIOC_RESP3: u32 = 65535;
pub const SDIOC_RESP4: u32 = 65535;
pub const SDIOC_RESP5: u32 = 65535;
pub const SDIOC_RESP6: u32 = 65535;
pub const SDIOC_RESP7: u32 = 65535;
pub const SDIOC_BUF0: u32 = 65535;
pub const SDIOC_BUF1: u32 = 65535;
pub const SDIOC_PSTAT_CIC_POS: u32 = 0;
pub const SDIOC_PSTAT_CIC: u32 = 1;
pub const SDIOC_PSTAT_CID_POS: u32 = 1;
pub const SDIOC_PSTAT_CID: u32 = 2;
pub const SDIOC_PSTAT_DA_POS: u32 = 2;
pub const SDIOC_PSTAT_DA: u32 = 4;
pub const SDIOC_PSTAT_WTA_POS: u32 = 8;
pub const SDIOC_PSTAT_WTA: u32 = 256;
pub const SDIOC_PSTAT_RTA_POS: u32 = 9;
pub const SDIOC_PSTAT_RTA: u32 = 512;
pub const SDIOC_PSTAT_BWE_POS: u32 = 10;
pub const SDIOC_PSTAT_BWE: u32 = 1024;
pub const SDIOC_PSTAT_BRE_POS: u32 = 11;
pub const SDIOC_PSTAT_BRE: u32 = 2048;
pub const SDIOC_PSTAT_CIN_POS: u32 = 16;
pub const SDIOC_PSTAT_CIN: u32 = 65536;
pub const SDIOC_PSTAT_CSS_POS: u32 = 17;
pub const SDIOC_PSTAT_CSS: u32 = 131072;
pub const SDIOC_PSTAT_CDL_POS: u32 = 18;
pub const SDIOC_PSTAT_CDL: u32 = 262144;
pub const SDIOC_PSTAT_WPL_POS: u32 = 19;
pub const SDIOC_PSTAT_WPL: u32 = 524288;
pub const SDIOC_PSTAT_DATL_POS: u32 = 20;
pub const SDIOC_PSTAT_DATL: u32 = 15728640;
pub const SDIOC_PSTAT_DATL_0: u32 = 1048576;
pub const SDIOC_PSTAT_DATL_1: u32 = 2097152;
pub const SDIOC_PSTAT_DATL_2: u32 = 4194304;
pub const SDIOC_PSTAT_DATL_3: u32 = 8388608;
pub const SDIOC_PSTAT_CMDL_POS: u32 = 24;
pub const SDIOC_PSTAT_CMDL: u32 = 16777216;
pub const SDIOC_HOSTCON_DW_POS: u32 = 1;
pub const SDIOC_HOSTCON_DW: u32 = 2;
pub const SDIOC_HOSTCON_HSEN_POS: u32 = 2;
pub const SDIOC_HOSTCON_HSEN: u32 = 4;
pub const SDIOC_HOSTCON_EXDW_POS: u32 = 5;
pub const SDIOC_HOSTCON_EXDW: u32 = 32;
pub const SDIOC_HOSTCON_CDTL_POS: u32 = 6;
pub const SDIOC_HOSTCON_CDTL: u32 = 64;
pub const SDIOC_HOSTCON_CDSS_POS: u32 = 7;
pub const SDIOC_HOSTCON_CDSS: u32 = 128;
pub const SDIOC_PWRCON_PWON: u32 = 1;
pub const SDIOC_BLKGPCON_SABGR_POS: u32 = 0;
pub const SDIOC_BLKGPCON_SABGR: u32 = 1;
pub const SDIOC_BLKGPCON_CR_POS: u32 = 1;
pub const SDIOC_BLKGPCON_CR: u32 = 2;
pub const SDIOC_BLKGPCON_RWC_POS: u32 = 2;
pub const SDIOC_BLKGPCON_RWC: u32 = 4;
pub const SDIOC_BLKGPCON_IABG_POS: u32 = 3;
pub const SDIOC_BLKGPCON_IABG: u32 = 8;
pub const SDIOC_CLKCON_ICE_POS: u32 = 0;
pub const SDIOC_CLKCON_ICE: u32 = 1;
pub const SDIOC_CLKCON_CE_POS: u32 = 2;
pub const SDIOC_CLKCON_CE: u32 = 4;
pub const SDIOC_CLKCON_FS_POS: u32 = 8;
pub const SDIOC_CLKCON_FS: u32 = 65280;
pub const SDIOC_CLKCON_FS_0: u32 = 256;
pub const SDIOC_CLKCON_FS_1: u32 = 512;
pub const SDIOC_CLKCON_FS_2: u32 = 1024;
pub const SDIOC_CLKCON_FS_3: u32 = 2048;
pub const SDIOC_CLKCON_FS_4: u32 = 4096;
pub const SDIOC_CLKCON_FS_5: u32 = 8192;
pub const SDIOC_CLKCON_FS_6: u32 = 16384;
pub const SDIOC_CLKCON_FS_7: u32 = 32768;
pub const SDIOC_TOUTCON_DTO: u32 = 15;
pub const SDIOC_SFTRST_RSTA_POS: u32 = 0;
pub const SDIOC_SFTRST_RSTA: u32 = 1;
pub const SDIOC_SFTRST_RSTC_POS: u32 = 1;
pub const SDIOC_SFTRST_RSTC: u32 = 2;
pub const SDIOC_SFTRST_RSTD_POS: u32 = 2;
pub const SDIOC_SFTRST_RSTD: u32 = 4;
pub const SDIOC_NORINTST_CC_POS: u32 = 0;
pub const SDIOC_NORINTST_CC: u32 = 1;
pub const SDIOC_NORINTST_TC_POS: u32 = 1;
pub const SDIOC_NORINTST_TC: u32 = 2;
pub const SDIOC_NORINTST_BGE_POS: u32 = 2;
pub const SDIOC_NORINTST_BGE: u32 = 4;
pub const SDIOC_NORINTST_BWR_POS: u32 = 4;
pub const SDIOC_NORINTST_BWR: u32 = 16;
pub const SDIOC_NORINTST_BRR_POS: u32 = 5;
pub const SDIOC_NORINTST_BRR: u32 = 32;
pub const SDIOC_NORINTST_CIST_POS: u32 = 6;
pub const SDIOC_NORINTST_CIST: u32 = 64;
pub const SDIOC_NORINTST_CRM_POS: u32 = 7;
pub const SDIOC_NORINTST_CRM: u32 = 128;
pub const SDIOC_NORINTST_CINT_POS: u32 = 8;
pub const SDIOC_NORINTST_CINT: u32 = 256;
pub const SDIOC_NORINTST_EI_POS: u32 = 15;
pub const SDIOC_NORINTST_EI: u32 = 32768;
pub const SDIOC_ERRINTST_CTOE_POS: u32 = 0;
pub const SDIOC_ERRINTST_CTOE: u32 = 1;
pub const SDIOC_ERRINTST_CCE_POS: u32 = 1;
pub const SDIOC_ERRINTST_CCE: u32 = 2;
pub const SDIOC_ERRINTST_CEBE_POS: u32 = 2;
pub const SDIOC_ERRINTST_CEBE: u32 = 4;
pub const SDIOC_ERRINTST_CIE_POS: u32 = 3;
pub const SDIOC_ERRINTST_CIE: u32 = 8;
pub const SDIOC_ERRINTST_DTOE_POS: u32 = 4;
pub const SDIOC_ERRINTST_DTOE: u32 = 16;
pub const SDIOC_ERRINTST_DCE_POS: u32 = 5;
pub const SDIOC_ERRINTST_DCE: u32 = 32;
pub const SDIOC_ERRINTST_DEBE_POS: u32 = 6;
pub const SDIOC_ERRINTST_DEBE: u32 = 64;
pub const SDIOC_ERRINTST_ACE_POS: u32 = 8;
pub const SDIOC_ERRINTST_ACE: u32 = 256;
pub const SDIOC_NORINTSTEN_CCEN_POS: u32 = 0;
pub const SDIOC_NORINTSTEN_CCEN: u32 = 1;
pub const SDIOC_NORINTSTEN_TCEN_POS: u32 = 1;
pub const SDIOC_NORINTSTEN_TCEN: u32 = 2;
pub const SDIOC_NORINTSTEN_BGEEN_POS: u32 = 2;
pub const SDIOC_NORINTSTEN_BGEEN: u32 = 4;
pub const SDIOC_NORINTSTEN_BWREN_POS: u32 = 4;
pub const SDIOC_NORINTSTEN_BWREN: u32 = 16;
pub const SDIOC_NORINTSTEN_BRREN_POS: u32 = 5;
pub const SDIOC_NORINTSTEN_BRREN: u32 = 32;
pub const SDIOC_NORINTSTEN_CISTEN_POS: u32 = 6;
pub const SDIOC_NORINTSTEN_CISTEN: u32 = 64;
pub const SDIOC_NORINTSTEN_CRMEN_POS: u32 = 7;
pub const SDIOC_NORINTSTEN_CRMEN: u32 = 128;
pub const SDIOC_NORINTSTEN_CINTEN_POS: u32 = 8;
pub const SDIOC_NORINTSTEN_CINTEN: u32 = 256;
pub const SDIOC_ERRINTSTEN_CTOEEN_POS: u32 = 0;
pub const SDIOC_ERRINTSTEN_CTOEEN: u32 = 1;
pub const SDIOC_ERRINTSTEN_CCEEN_POS: u32 = 1;
pub const SDIOC_ERRINTSTEN_CCEEN: u32 = 2;
pub const SDIOC_ERRINTSTEN_CEBEEN_POS: u32 = 2;
pub const SDIOC_ERRINTSTEN_CEBEEN: u32 = 4;
pub const SDIOC_ERRINTSTEN_CIEEN_POS: u32 = 3;
pub const SDIOC_ERRINTSTEN_CIEEN: u32 = 8;
pub const SDIOC_ERRINTSTEN_DTOEEN_POS: u32 = 4;
pub const SDIOC_ERRINTSTEN_DTOEEN: u32 = 16;
pub const SDIOC_ERRINTSTEN_DCEEN_POS: u32 = 5;
pub const SDIOC_ERRINTSTEN_DCEEN: u32 = 32;
pub const SDIOC_ERRINTSTEN_DEBEEN_POS: u32 = 6;
pub const SDIOC_ERRINTSTEN_DEBEEN: u32 = 64;
pub const SDIOC_ERRINTSTEN_ACEEN_POS: u32 = 8;
pub const SDIOC_ERRINTSTEN_ACEEN: u32 = 256;
pub const SDIOC_NORINTSGEN_CCSEN_POS: u32 = 0;
pub const SDIOC_NORINTSGEN_CCSEN: u32 = 1;
pub const SDIOC_NORINTSGEN_TCSEN_POS: u32 = 1;
pub const SDIOC_NORINTSGEN_TCSEN: u32 = 2;
pub const SDIOC_NORINTSGEN_BGESEN_POS: u32 = 2;
pub const SDIOC_NORINTSGEN_BGESEN: u32 = 4;
pub const SDIOC_NORINTSGEN_BWRSEN_POS: u32 = 4;
pub const SDIOC_NORINTSGEN_BWRSEN: u32 = 16;
pub const SDIOC_NORINTSGEN_BRRSEN_POS: u32 = 5;
pub const SDIOC_NORINTSGEN_BRRSEN: u32 = 32;
pub const SDIOC_NORINTSGEN_CISTSEN_POS: u32 = 6;
pub const SDIOC_NORINTSGEN_CISTSEN: u32 = 64;
pub const SDIOC_NORINTSGEN_CRMSEN_POS: u32 = 7;
pub const SDIOC_NORINTSGEN_CRMSEN: u32 = 128;
pub const SDIOC_NORINTSGEN_CINTSEN_POS: u32 = 8;
pub const SDIOC_NORINTSGEN_CINTSEN: u32 = 256;
pub const SDIOC_ERRINTSGEN_CTOESEN_POS: u32 = 0;
pub const SDIOC_ERRINTSGEN_CTOESEN: u32 = 1;
pub const SDIOC_ERRINTSGEN_CCESEN_POS: u32 = 1;
pub const SDIOC_ERRINTSGEN_CCESEN: u32 = 2;
pub const SDIOC_ERRINTSGEN_CEBESEN_POS: u32 = 2;
pub const SDIOC_ERRINTSGEN_CEBESEN: u32 = 4;
pub const SDIOC_ERRINTSGEN_CIESEN_POS: u32 = 3;
pub const SDIOC_ERRINTSGEN_CIESEN: u32 = 8;
pub const SDIOC_ERRINTSGEN_DTOESEN_POS: u32 = 4;
pub const SDIOC_ERRINTSGEN_DTOESEN: u32 = 16;
pub const SDIOC_ERRINTSGEN_DCESEN_POS: u32 = 5;
pub const SDIOC_ERRINTSGEN_DCESEN: u32 = 32;
pub const SDIOC_ERRINTSGEN_DEBESEN_POS: u32 = 6;
pub const SDIOC_ERRINTSGEN_DEBESEN: u32 = 64;
pub const SDIOC_ERRINTSGEN_ACESEN_POS: u32 = 8;
pub const SDIOC_ERRINTSGEN_ACESEN: u32 = 256;
pub const SDIOC_ATCERRST_NE_POS: u32 = 0;
pub const SDIOC_ATCERRST_NE: u32 = 1;
pub const SDIOC_ATCERRST_TOE_POS: u32 = 1;
pub const SDIOC_ATCERRST_TOE: u32 = 2;
pub const SDIOC_ATCERRST_CE_POS: u32 = 2;
pub const SDIOC_ATCERRST_CE: u32 = 4;
pub const SDIOC_ATCERRST_EBE_POS: u32 = 3;
pub const SDIOC_ATCERRST_EBE: u32 = 8;
pub const SDIOC_ATCERRST_IE_POS: u32 = 4;
pub const SDIOC_ATCERRST_IE: u32 = 16;
pub const SDIOC_ATCERRST_CMDE_POS: u32 = 7;
pub const SDIOC_ATCERRST_CMDE: u32 = 128;
pub const SDIOC_FEA_FNE_POS: u32 = 0;
pub const SDIOC_FEA_FNE: u32 = 1;
pub const SDIOC_FEA_FTOE_POS: u32 = 1;
pub const SDIOC_FEA_FTOE: u32 = 2;
pub const SDIOC_FEA_FCE_POS: u32 = 2;
pub const SDIOC_FEA_FCE: u32 = 4;
pub const SDIOC_FEA_FEBE_POS: u32 = 3;
pub const SDIOC_FEA_FEBE: u32 = 8;
pub const SDIOC_FEA_FIE_POS: u32 = 4;
pub const SDIOC_FEA_FIE: u32 = 16;
pub const SDIOC_FEA_FCMDE_POS: u32 = 7;
pub const SDIOC_FEA_FCMDE: u32 = 128;
pub const SDIOC_FEE_FCTOE_POS: u32 = 0;
pub const SDIOC_FEE_FCTOE: u32 = 1;
pub const SDIOC_FEE_FCCE_POS: u32 = 1;
pub const SDIOC_FEE_FCCE: u32 = 2;
pub const SDIOC_FEE_FCEBE_POS: u32 = 2;
pub const SDIOC_FEE_FCEBE: u32 = 4;
pub const SDIOC_FEE_FCIE_POS: u32 = 3;
pub const SDIOC_FEE_FCIE: u32 = 8;
pub const SDIOC_FEE_FDTOE_POS: u32 = 4;
pub const SDIOC_FEE_FDTOE: u32 = 16;
pub const SDIOC_FEE_FDCE_POS: u32 = 5;
pub const SDIOC_FEE_FDCE: u32 = 32;
pub const SDIOC_FEE_FDEBE_POS: u32 = 6;
pub const SDIOC_FEE_FDEBE: u32 = 64;
pub const SDIOC_FEE_FACE_POS: u32 = 8;
pub const SDIOC_FEE_FACE: u32 = 256;
pub const SPI_DR: u32 = 4294967295;
pub const SPI_CR1_SPIMDS_POS: u32 = 0;
pub const SPI_CR1_SPIMDS: u32 = 1;
pub const SPI_CR1_TXMDS_POS: u32 = 1;
pub const SPI_CR1_TXMDS: u32 = 2;
pub const SPI_CR1_MSTR_POS: u32 = 3;
pub const SPI_CR1_MSTR: u32 = 8;
pub const SPI_CR1_SPLPBK_POS: u32 = 4;
pub const SPI_CR1_SPLPBK: u32 = 16;
pub const SPI_CR1_SPLPBK2_POS: u32 = 5;
pub const SPI_CR1_SPLPBK2: u32 = 32;
pub const SPI_CR1_SPE_POS: u32 = 6;
pub const SPI_CR1_SPE: u32 = 64;
pub const SPI_CR1_CSUSPE_POS: u32 = 7;
pub const SPI_CR1_CSUSPE: u32 = 128;
pub const SPI_CR1_EIE_POS: u32 = 8;
pub const SPI_CR1_EIE: u32 = 256;
pub const SPI_CR1_TXIE_POS: u32 = 9;
pub const SPI_CR1_TXIE: u32 = 512;
pub const SPI_CR1_RXIE_POS: u32 = 10;
pub const SPI_CR1_RXIE: u32 = 1024;
pub const SPI_CR1_IDIE_POS: u32 = 11;
pub const SPI_CR1_IDIE: u32 = 2048;
pub const SPI_CR1_MODFE_POS: u32 = 12;
pub const SPI_CR1_MODFE: u32 = 4096;
pub const SPI_CR1_PATE_POS: u32 = 13;
pub const SPI_CR1_PATE: u32 = 8192;
pub const SPI_CR1_PAOE_POS: u32 = 14;
pub const SPI_CR1_PAOE: u32 = 16384;
pub const SPI_CR1_PAE_POS: u32 = 15;
pub const SPI_CR1_PAE: u32 = 32768;
pub const SPI_CFG1_FTHLV_POS: u32 = 0;
pub const SPI_CFG1_FTHLV: u32 = 3;
pub const SPI_CFG1_FTHLV_0: u32 = 1;
pub const SPI_CFG1_FTHLV_1: u32 = 2;
pub const SPI_CFG1_SPRDTD_POS: u32 = 6;
pub const SPI_CFG1_SPRDTD: u32 = 64;
pub const SPI_CFG1_SS0PV_POS: u32 = 8;
pub const SPI_CFG1_SS0PV: u32 = 256;
pub const SPI_CFG1_SS1PV_POS: u32 = 9;
pub const SPI_CFG1_SS1PV: u32 = 512;
pub const SPI_CFG1_SS2PV_POS: u32 = 10;
pub const SPI_CFG1_SS2PV: u32 = 1024;
pub const SPI_CFG1_SS3PV_POS: u32 = 11;
pub const SPI_CFG1_SS3PV: u32 = 2048;
pub const SPI_CFG1_MSSI_POS: u32 = 20;
pub const SPI_CFG1_MSSI: u32 = 7340032;
pub const SPI_CFG1_MSSDL_POS: u32 = 24;
pub const SPI_CFG1_MSSDL: u32 = 117440512;
pub const SPI_CFG1_MIDI_POS: u32 = 28;
pub const SPI_CFG1_MIDI: u32 = 1879048192;
pub const SPI_SR_OVRERF_POS: u32 = 0;
pub const SPI_SR_OVRERF: u32 = 1;
pub const SPI_SR_IDLNF_POS: u32 = 1;
pub const SPI_SR_IDLNF: u32 = 2;
pub const SPI_SR_MODFERF_POS: u32 = 2;
pub const SPI_SR_MODFERF: u32 = 4;
pub const SPI_SR_PERF_POS: u32 = 3;
pub const SPI_SR_PERF: u32 = 8;
pub const SPI_SR_UDRERF_POS: u32 = 4;
pub const SPI_SR_UDRERF: u32 = 16;
pub const SPI_SR_TDEF_POS: u32 = 5;
pub const SPI_SR_TDEF: u32 = 32;
pub const SPI_SR_RDFF_POS: u32 = 7;
pub const SPI_SR_RDFF: u32 = 128;
pub const SPI_CFG2_CPHA_POS: u32 = 0;
pub const SPI_CFG2_CPHA: u32 = 1;
pub const SPI_CFG2_CPOL_POS: u32 = 1;
pub const SPI_CFG2_CPOL: u32 = 2;
pub const SPI_CFG2_MBR_POS: u32 = 2;
pub const SPI_CFG2_MBR: u32 = 28;
pub const SPI_CFG2_SSA_POS: u32 = 5;
pub const SPI_CFG2_SSA: u32 = 224;
pub const SPI_CFG2_SSA_0: u32 = 32;
pub const SPI_CFG2_SSA_1: u32 = 64;
pub const SPI_CFG2_SSA_2: u32 = 128;
pub const SPI_CFG2_DSIZE_POS: u32 = 8;
pub const SPI_CFG2_DSIZE: u32 = 3840;
pub const SPI_CFG2_LSBF_POS: u32 = 12;
pub const SPI_CFG2_LSBF: u32 = 4096;
pub const SPI_CFG2_MIDIE_POS: u32 = 13;
pub const SPI_CFG2_MIDIE: u32 = 8192;
pub const SPI_CFG2_MSSDLE_POS: u32 = 14;
pub const SPI_CFG2_MSSDLE: u32 = 16384;
pub const SPI_CFG2_MSSIE_POS: u32 = 15;
pub const SPI_CFG2_MSSIE: u32 = 32768;
pub const SRAMC_WTCR_SRAM12_RWT_POS: u32 = 0;
pub const SRAMC_WTCR_SRAM12_RWT: u32 = 7;
pub const SRAMC_WTCR_SRAM12_WWT_POS: u32 = 4;
pub const SRAMC_WTCR_SRAM12_WWT: u32 = 112;
pub const SRAMC_WTCR_SRAM3_RWT_POS: u32 = 8;
pub const SRAMC_WTCR_SRAM3_RWT: u32 = 1792;
pub const SRAMC_WTCR_SRAM3_WWT_POS: u32 = 12;
pub const SRAMC_WTCR_SRAM3_WWT: u32 = 28672;
pub const SRAMC_WTCR_SRAMH_RWT_POS: u32 = 16;
pub const SRAMC_WTCR_SRAMH_RWT: u32 = 458752;
pub const SRAMC_WTCR_SRAMH_WWT_POS: u32 = 20;
pub const SRAMC_WTCR_SRAMH_WWT: u32 = 7340032;
pub const SRAMC_WTCR_SRAMR_RWT_POS: u32 = 24;
pub const SRAMC_WTCR_SRAMR_RWT: u32 = 117440512;
pub const SRAMC_WTCR_SRAMR_WWT_POS: u32 = 28;
pub const SRAMC_WTCR_SRAMR_WWT: u32 = 1879048192;
pub const SRAMC_WTPR_WTPRC_POS: u32 = 0;
pub const SRAMC_WTPR_WTPRC: u32 = 1;
pub const SRAMC_WTPR_WTPRKW_POS: u32 = 1;
pub const SRAMC_WTPR_WTPRKW: u32 = 254;
pub const SRAMC_CKCR_PYOAD_POS: u32 = 0;
pub const SRAMC_CKCR_PYOAD: u32 = 1;
pub const SRAMC_CKCR_ECCOAD_POS: u32 = 16;
pub const SRAMC_CKCR_ECCOAD: u32 = 65536;
pub const SRAMC_CKCR_ECCMOD_POS: u32 = 24;
pub const SRAMC_CKCR_ECCMOD: u32 = 50331648;
pub const SRAMC_CKCR_ECCMOD_0: u32 = 16777216;
pub const SRAMC_CKCR_ECCMOD_1: u32 = 33554432;
pub const SRAMC_CKPR_CKPRC_POS: u32 = 0;
pub const SRAMC_CKPR_CKPRC: u32 = 1;
pub const SRAMC_CKPR_CKPRKW_POS: u32 = 1;
pub const SRAMC_CKPR_CKPRKW: u32 = 254;
pub const SRAMC_CKSR_SRAM3_1ERR_POS: u32 = 0;
pub const SRAMC_CKSR_SRAM3_1ERR: u32 = 1;
pub const SRAMC_CKSR_SRAM3_2ERR_POS: u32 = 1;
pub const SRAMC_CKSR_SRAM3_2ERR: u32 = 2;
pub const SRAMC_CKSR_SRAM12_PYERR_POS: u32 = 2;
pub const SRAMC_CKSR_SRAM12_PYERR: u32 = 4;
pub const SRAMC_CKSR_SRAMH_PYERR_POS: u32 = 3;
pub const SRAMC_CKSR_SRAMH_PYERR: u32 = 8;
pub const SRAMC_CKSR_SRAMR_PYERR_POS: u32 = 4;
pub const SRAMC_CKSR_SRAMR_PYERR: u32 = 16;
pub const SWDT_SR_CNT_POS: u32 = 0;
pub const SWDT_SR_CNT: u32 = 65535;
pub const SWDT_SR_UDF_POS: u32 = 16;
pub const SWDT_SR_UDF: u32 = 65536;
pub const SWDT_SR_REF_POS: u32 = 17;
pub const SWDT_SR_REF: u32 = 131072;
pub const SWDT_RR_RF: u32 = 65535;
pub const TMR0_CNTAR_CNTA: u32 = 65535;
pub const TMR0_CNTBR_CNTB: u32 = 65535;
pub const TMR0_CMPAR_CMPA: u32 = 65535;
pub const TMR0_CMPBR_CMPB: u32 = 65535;
pub const TMR0_BCONR_CSTA_POS: u32 = 0;
pub const TMR0_BCONR_CSTA: u32 = 1;
pub const TMR0_BCONR_CAPMDA_POS: u32 = 1;
pub const TMR0_BCONR_CAPMDA: u32 = 2;
pub const TMR0_BCONR_INTENA_POS: u32 = 2;
pub const TMR0_BCONR_INTENA: u32 = 4;
pub const TMR0_BCONR_CKDIVA_POS: u32 = 4;
pub const TMR0_BCONR_CKDIVA: u32 = 240;
pub const TMR0_BCONR_SYNSA_POS: u32 = 8;
pub const TMR0_BCONR_SYNSA: u32 = 256;
pub const TMR0_BCONR_SYNCLKA_POS: u32 = 9;
pub const TMR0_BCONR_SYNCLKA: u32 = 512;
pub const TMR0_BCONR_ASYNCLKA_POS: u32 = 10;
pub const TMR0_BCONR_ASYNCLKA: u32 = 1024;
pub const TMR0_BCONR_HSTAA_POS: u32 = 12;
pub const TMR0_BCONR_HSTAA: u32 = 4096;
pub const TMR0_BCONR_HSTPA_POS: u32 = 13;
pub const TMR0_BCONR_HSTPA: u32 = 8192;
pub const TMR0_BCONR_HCLEA_POS: u32 = 14;
pub const TMR0_BCONR_HCLEA: u32 = 16384;
pub const TMR0_BCONR_HICPA_POS: u32 = 15;
pub const TMR0_BCONR_HICPA: u32 = 32768;
pub const TMR0_BCONR_CSTB_POS: u32 = 16;
pub const TMR0_BCONR_CSTB: u32 = 65536;
pub const TMR0_BCONR_CAPMDB_POS: u32 = 17;
pub const TMR0_BCONR_CAPMDB: u32 = 131072;
pub const TMR0_BCONR_INTENB_POS: u32 = 18;
pub const TMR0_BCONR_INTENB: u32 = 262144;
pub const TMR0_BCONR_CKDIVB_POS: u32 = 20;
pub const TMR0_BCONR_CKDIVB: u32 = 15728640;
pub const TMR0_BCONR_SYNSB_POS: u32 = 24;
pub const TMR0_BCONR_SYNSB: u32 = 16777216;
pub const TMR0_BCONR_SYNCLKB_POS: u32 = 25;
pub const TMR0_BCONR_SYNCLKB: u32 = 33554432;
pub const TMR0_BCONR_ASYNCLKB_POS: u32 = 26;
pub const TMR0_BCONR_ASYNCLKB: u32 = 67108864;
pub const TMR0_BCONR_HSTAB_POS: u32 = 28;
pub const TMR0_BCONR_HSTAB: u32 = 268435456;
pub const TMR0_BCONR_HSTPB_POS: u32 = 29;
pub const TMR0_BCONR_HSTPB: u32 = 536870912;
pub const TMR0_BCONR_HCLEB_POS: u32 = 30;
pub const TMR0_BCONR_HCLEB: u32 = 1073741824;
pub const TMR0_BCONR_HICPB_POS: u32 = 31;
pub const TMR0_BCONR_HICPB: u32 = 2147483648;
pub const TMR0_STFLR_CMFA_POS: u32 = 0;
pub const TMR0_STFLR_CMFA: u32 = 1;
pub const TMR0_STFLR_CMFB_POS: u32 = 16;
pub const TMR0_STFLR_CMFB: u32 = 65536;
pub const TMR4_OCCRUH: u32 = 65535;
pub const TMR4_OCCRUL: u32 = 65535;
pub const TMR4_OCCRVH: u32 = 65535;
pub const TMR4_OCCRVL: u32 = 65535;
pub const TMR4_OCCRWH: u32 = 65535;
pub const TMR4_OCCRWL: u32 = 65535;
pub const TMR4_OCSR_OCEH_POS: u32 = 0;
pub const TMR4_OCSR_OCEH: u32 = 1;
pub const TMR4_OCSR_OCEL_POS: u32 = 1;
pub const TMR4_OCSR_OCEL: u32 = 2;
pub const TMR4_OCSR_OCPH_POS: u32 = 2;
pub const TMR4_OCSR_OCPH: u32 = 4;
pub const TMR4_OCSR_OCPL_POS: u32 = 3;
pub const TMR4_OCSR_OCPL: u32 = 8;
pub const TMR4_OCSR_OCIEH_POS: u32 = 4;
pub const TMR4_OCSR_OCIEH: u32 = 16;
pub const TMR4_OCSR_OCIEL_POS: u32 = 5;
pub const TMR4_OCSR_OCIEL: u32 = 32;
pub const TMR4_OCSR_OCFH_POS: u32 = 6;
pub const TMR4_OCSR_OCFH: u32 = 64;
pub const TMR4_OCSR_OCFL_POS: u32 = 7;
pub const TMR4_OCSR_OCFL: u32 = 128;
pub const TMR4_OCER_CHBUFEN_POS: u32 = 0;
pub const TMR4_OCER_CHBUFEN: u32 = 3;
pub const TMR4_OCER_CHBUFEN_0: u32 = 1;
pub const TMR4_OCER_CHBUFEN_1: u32 = 2;
pub const TMR4_OCER_CLBUFEN_POS: u32 = 2;
pub const TMR4_OCER_CLBUFEN: u32 = 12;
pub const TMR4_OCER_CLBUFEN_0: u32 = 4;
pub const TMR4_OCER_CLBUFEN_1: u32 = 8;
pub const TMR4_OCER_MHBUFEN_POS: u32 = 4;
pub const TMR4_OCER_MHBUFEN: u32 = 48;
pub const TMR4_OCER_MHBUFEN_0: u32 = 16;
pub const TMR4_OCER_MHBUFEN_1: u32 = 32;
pub const TMR4_OCER_MLBUFEN_POS: u32 = 6;
pub const TMR4_OCER_MLBUFEN: u32 = 192;
pub const TMR4_OCER_MLBUFEN_0: u32 = 64;
pub const TMR4_OCER_MLBUFEN_1: u32 = 128;
pub const TMR4_OCER_LMCH_POS: u32 = 8;
pub const TMR4_OCER_LMCH: u32 = 256;
pub const TMR4_OCER_LMCL_POS: u32 = 9;
pub const TMR4_OCER_LMCL: u32 = 512;
pub const TMR4_OCER_LMMH_POS: u32 = 10;
pub const TMR4_OCER_LMMH: u32 = 1024;
pub const TMR4_OCER_LMML_POS: u32 = 11;
pub const TMR4_OCER_LMML: u32 = 2048;
pub const TMR4_OCER_MCECH_POS: u32 = 12;
pub const TMR4_OCER_MCECH: u32 = 4096;
pub const TMR4_OCER_MCECL_POS: u32 = 13;
pub const TMR4_OCER_MCECL: u32 = 8192;
pub const TMR4_OCMRH_OCFDCH_POS: u32 = 0;
pub const TMR4_OCMRH_OCFDCH: u32 = 1;
pub const TMR4_OCMRH_OCFPKH_POS: u32 = 1;
pub const TMR4_OCMRH_OCFPKH: u32 = 2;
pub const TMR4_OCMRH_OCFUCH_POS: u32 = 2;
pub const TMR4_OCMRH_OCFUCH: u32 = 4;
pub const TMR4_OCMRH_OCFZRH_POS: u32 = 3;
pub const TMR4_OCMRH_OCFZRH: u32 = 8;
pub const TMR4_OCMRH_OPDCH_POS: u32 = 4;
pub const TMR4_OCMRH_OPDCH: u32 = 48;
pub const TMR4_OCMRH_OPDCH_0: u32 = 16;
pub const TMR4_OCMRH_OPDCH_1: u32 = 32;
pub const TMR4_OCMRH_OPPKH_POS: u32 = 6;
pub const TMR4_OCMRH_OPPKH: u32 = 192;
pub const TMR4_OCMRH_OPPKH_0: u32 = 64;
pub const TMR4_OCMRH_OPPKH_1: u32 = 128;
pub const TMR4_OCMRH_OPUCH_POS: u32 = 8;
pub const TMR4_OCMRH_OPUCH: u32 = 768;
pub const TMR4_OCMRH_OPUCH_0: u32 = 256;
pub const TMR4_OCMRH_OPUCH_1: u32 = 512;
pub const TMR4_OCMRH_OPZRH_POS: u32 = 10;
pub const TMR4_OCMRH_OPZRH: u32 = 3072;
pub const TMR4_OCMRH_OPZRH_0: u32 = 1024;
pub const TMR4_OCMRH_OPZRH_1: u32 = 2048;
pub const TMR4_OCMRH_OPNPKH_POS: u32 = 12;
pub const TMR4_OCMRH_OPNPKH: u32 = 12288;
pub const TMR4_OCMRH_OPNPKH_0: u32 = 4096;
pub const TMR4_OCMRH_OPNPKH_1: u32 = 8192;
pub const TMR4_OCMRH_OPNZRH_POS: u32 = 14;
pub const TMR4_OCMRH_OPNZRH: u32 = 49152;
pub const TMR4_OCMRH_OPNZRH_0: u32 = 16384;
pub const TMR4_OCMRH_OPNZRH_1: u32 = 32768;
pub const TMR4_OCMRL_OCFDCL_POS: u32 = 0;
pub const TMR4_OCMRL_OCFDCL: u32 = 1;
pub const TMR4_OCMRL_OCFPKL_POS: u32 = 1;
pub const TMR4_OCMRL_OCFPKL: u32 = 2;
pub const TMR4_OCMRL_OCFUCL_POS: u32 = 2;
pub const TMR4_OCMRL_OCFUCL: u32 = 4;
pub const TMR4_OCMRL_OCFZRL_POS: u32 = 3;
pub const TMR4_OCMRL_OCFZRL: u32 = 8;
pub const TMR4_OCMRL_OPDCL_POS: u32 = 4;
pub const TMR4_OCMRL_OPDCL: u32 = 48;
pub const TMR4_OCMRL_OPDCL_0: u32 = 16;
pub const TMR4_OCMRL_OPDCL_1: u32 = 32;
pub const TMR4_OCMRL_OPPKL_POS: u32 = 6;
pub const TMR4_OCMRL_OPPKL: u32 = 192;
pub const TMR4_OCMRL_OPPKL_0: u32 = 64;
pub const TMR4_OCMRL_OPPKL_1: u32 = 128;
pub const TMR4_OCMRL_OPUCL_POS: u32 = 8;
pub const TMR4_OCMRL_OPUCL: u32 = 768;
pub const TMR4_OCMRL_OPUCL_0: u32 = 256;
pub const TMR4_OCMRL_OPUCL_1: u32 = 512;
pub const TMR4_OCMRL_OPZRL_POS: u32 = 10;
pub const TMR4_OCMRL_OPZRL: u32 = 3072;
pub const TMR4_OCMRL_OPZRL_0: u32 = 1024;
pub const TMR4_OCMRL_OPZRL_1: u32 = 2048;
pub const TMR4_OCMRL_OPNPKL_POS: u32 = 12;
pub const TMR4_OCMRL_OPNPKL: u32 = 12288;
pub const TMR4_OCMRL_OPNPKL_0: u32 = 4096;
pub const TMR4_OCMRL_OPNPKL_1: u32 = 8192;
pub const TMR4_OCMRL_OPNZRL_POS: u32 = 14;
pub const TMR4_OCMRL_OPNZRL: u32 = 49152;
pub const TMR4_OCMRL_OPNZRL_0: u32 = 16384;
pub const TMR4_OCMRL_OPNZRL_1: u32 = 32768;
pub const TMR4_OCMRL_EOPNDCL_POS: u32 = 16;
pub const TMR4_OCMRL_EOPNDCL: u32 = 196608;
pub const TMR4_OCMRL_EOPNDCL_0: u32 = 65536;
pub const TMR4_OCMRL_EOPNDCL_1: u32 = 131072;
pub const TMR4_OCMRL_EOPNUCL_POS: u32 = 18;
pub const TMR4_OCMRL_EOPNUCL: u32 = 786432;
pub const TMR4_OCMRL_EOPNUCL_0: u32 = 262144;
pub const TMR4_OCMRL_EOPNUCL_1: u32 = 524288;
pub const TMR4_OCMRL_EOPDCL_POS: u32 = 20;
pub const TMR4_OCMRL_EOPDCL: u32 = 3145728;
pub const TMR4_OCMRL_EOPDCL_0: u32 = 1048576;
pub const TMR4_OCMRL_EOPDCL_1: u32 = 2097152;
pub const TMR4_OCMRL_EOPPKL_POS: u32 = 22;
pub const TMR4_OCMRL_EOPPKL: u32 = 12582912;
pub const TMR4_OCMRL_EOPPKL_0: u32 = 4194304;
pub const TMR4_OCMRL_EOPPKL_1: u32 = 8388608;
pub const TMR4_OCMRL_EOPUCL_POS: u32 = 24;
pub const TMR4_OCMRL_EOPUCL: u32 = 50331648;
pub const TMR4_OCMRL_EOPUCL_0: u32 = 16777216;
pub const TMR4_OCMRL_EOPUCL_1: u32 = 33554432;
pub const TMR4_OCMRL_EOPZRL_POS: u32 = 26;
pub const TMR4_OCMRL_EOPZRL: u32 = 201326592;
pub const TMR4_OCMRL_EOPZRL_0: u32 = 67108864;
pub const TMR4_OCMRL_EOPZRL_1: u32 = 134217728;
pub const TMR4_OCMRL_EOPNPKL_POS: u32 = 28;
pub const TMR4_OCMRL_EOPNPKL: u32 = 805306368;
pub const TMR4_OCMRL_EOPNPKL_0: u32 = 268435456;
pub const TMR4_OCMRL_EOPNPKL_1: u32 = 536870912;
pub const TMR4_OCMRL_EOPNZRL_POS: u32 = 30;
pub const TMR4_OCMRL_EOPNZRL: u32 = 3221225472;
pub const TMR4_OCMRL_EOPNZRL_0: u32 = 1073741824;
pub const TMR4_OCMRL_EOPNZRL_1: u32 = 2147483648;
pub const TMR4_CPSR: u32 = 65535;
pub const TMR4_CNTR: u32 = 65535;
pub const TMR4_CCSR_CKDIV_POS: u32 = 0;
pub const TMR4_CCSR_CKDIV: u32 = 15;
pub const TMR4_CCSR_CLEAR_POS: u32 = 4;
pub const TMR4_CCSR_CLEAR: u32 = 16;
pub const TMR4_CCSR_MODE_POS: u32 = 5;
pub const TMR4_CCSR_MODE: u32 = 32;
pub const TMR4_CCSR_STOP_POS: u32 = 6;
pub const TMR4_CCSR_STOP: u32 = 64;
pub const TMR4_CCSR_BUFEN_POS: u32 = 7;
pub const TMR4_CCSR_BUFEN: u32 = 128;
pub const TMR4_CCSR_IRQPEN_POS: u32 = 8;
pub const TMR4_CCSR_IRQPEN: u32 = 256;
pub const TMR4_CCSR_IRQPF_POS: u32 = 9;
pub const TMR4_CCSR_IRQPF: u32 = 512;
pub const TMR4_CCSR_IRQZEN_POS: u32 = 13;
pub const TMR4_CCSR_IRQZEN: u32 = 8192;
pub const TMR4_CCSR_IRQZF_POS: u32 = 14;
pub const TMR4_CCSR_IRQZF: u32 = 16384;
pub const TMR4_CCSR_ECKEN_POS: u32 = 15;
pub const TMR4_CCSR_ECKEN: u32 = 32768;
pub const TMR4_CVPR_ZIM_POS: u32 = 0;
pub const TMR4_CVPR_ZIM: u32 = 15;
pub const TMR4_CVPR_PIM_POS: u32 = 4;
pub const TMR4_CVPR_PIM: u32 = 240;
pub const TMR4_CVPR_ZIC_POS: u32 = 8;
pub const TMR4_CVPR_ZIC: u32 = 3840;
pub const TMR4_CVPR_PIC_POS: u32 = 12;
pub const TMR4_CVPR_PIC: u32 = 61440;
pub const TMR4_PFSRU: u32 = 65535;
pub const TMR4_PDARU: u32 = 65535;
pub const TMR4_PDBRU: u32 = 65535;
pub const TMR4_PFSRV: u32 = 65535;
pub const TMR4_PDARV: u32 = 65535;
pub const TMR4_PDBRV: u32 = 65535;
pub const TMR4_PFSRW: u32 = 65535;
pub const TMR4_PDARW: u32 = 65535;
pub const TMR4_PDBRW: u32 = 65535;
pub const TMR4_POCR_DIVCK_POS: u32 = 0;
pub const TMR4_POCR_DIVCK: u32 = 7;
pub const TMR4_POCR_PWMMD_POS: u32 = 4;
pub const TMR4_POCR_PWMMD: u32 = 48;
pub const TMR4_POCR_PWMMD_0: u32 = 16;
pub const TMR4_POCR_PWMMD_1: u32 = 32;
pub const TMR4_POCR_LVLS_POS: u32 = 6;
pub const TMR4_POCR_LVLS: u32 = 192;
pub const TMR4_POCR_LVLS_0: u32 = 64;
pub const TMR4_POCR_LVLS_1: u32 = 128;
pub const TMR4_RCSR_RTIDU_POS: u32 = 0;
pub const TMR4_RCSR_RTIDU: u32 = 1;
pub const TMR4_RCSR_RTIDV_POS: u32 = 1;
pub const TMR4_RCSR_RTIDV: u32 = 2;
pub const TMR4_RCSR_RTIDW_POS: u32 = 2;
pub const TMR4_RCSR_RTIDW: u32 = 4;
pub const TMR4_RCSR_RTIFU_POS: u32 = 4;
pub const TMR4_RCSR_RTIFU: u32 = 16;
pub const TMR4_RCSR_RTICU_POS: u32 = 5;
pub const TMR4_RCSR_RTICU: u32 = 32;
pub const TMR4_RCSR_RTEU_POS: u32 = 6;
pub const TMR4_RCSR_RTEU: u32 = 64;
pub const TMR4_RCSR_RTSU_POS: u32 = 7;
pub const TMR4_RCSR_RTSU: u32 = 128;
pub const TMR4_RCSR_RTIFV_POS: u32 = 8;
pub const TMR4_RCSR_RTIFV: u32 = 256;
pub const TMR4_RCSR_RTICV_POS: u32 = 9;
pub const TMR4_RCSR_RTICV: u32 = 512;
pub const TMR4_RCSR_RTEV_POS: u32 = 10;
pub const TMR4_RCSR_RTEV: u32 = 1024;
pub const TMR4_RCSR_RTSV_POS: u32 = 11;
pub const TMR4_RCSR_RTSV: u32 = 2048;
pub const TMR4_RCSR_RTIFW_POS: u32 = 12;
pub const TMR4_RCSR_RTIFW: u32 = 4096;
pub const TMR4_RCSR_RTICW_POS: u32 = 13;
pub const TMR4_RCSR_RTICW: u32 = 8192;
pub const TMR4_RCSR_RTEW_POS: u32 = 14;
pub const TMR4_RCSR_RTEW: u32 = 16384;
pub const TMR4_RCSR_RTSW_POS: u32 = 15;
pub const TMR4_RCSR_RTSW: u32 = 32768;
pub const TMR4_SCCRUH: u32 = 65535;
pub const TMR4_SCCRUL: u32 = 65535;
pub const TMR4_SCCRVH: u32 = 65535;
pub const TMR4_SCCRVL: u32 = 65535;
pub const TMR4_SCCRWH: u32 = 65535;
pub const TMR4_SCCRWL: u32 = 65535;
pub const TMR4_SCSR_BUFEN_POS: u32 = 0;
pub const TMR4_SCSR_BUFEN: u32 = 3;
pub const TMR4_SCSR_BUFEN_0: u32 = 1;
pub const TMR4_SCSR_BUFEN_1: u32 = 2;
pub const TMR4_SCSR_EVTOS_POS: u32 = 2;
pub const TMR4_SCSR_EVTOS: u32 = 28;
pub const TMR4_SCSR_LMC_POS: u32 = 5;
pub const TMR4_SCSR_LMC: u32 = 32;
pub const TMR4_SCSR_EVTMS_POS: u32 = 8;
pub const TMR4_SCSR_EVTMS: u32 = 256;
pub const TMR4_SCSR_EVTDS_POS: u32 = 9;
pub const TMR4_SCSR_EVTDS: u32 = 512;
pub const TMR4_SCSR_DEN_POS: u32 = 12;
pub const TMR4_SCSR_DEN: u32 = 4096;
pub const TMR4_SCSR_PEN_POS: u32 = 13;
pub const TMR4_SCSR_PEN: u32 = 8192;
pub const TMR4_SCSR_UEN_POS: u32 = 14;
pub const TMR4_SCSR_UEN: u32 = 16384;
pub const TMR4_SCSR_ZEN_POS: u32 = 15;
pub const TMR4_SCSR_ZEN: u32 = 32768;
pub const TMR4_SCMR_AMC_POS: u32 = 0;
pub const TMR4_SCMR_AMC: u32 = 15;
pub const TMR4_SCMR_MZCE_POS: u32 = 6;
pub const TMR4_SCMR_MZCE: u32 = 64;
pub const TMR4_SCMR_MPCE_POS: u32 = 7;
pub const TMR4_SCMR_MPCE: u32 = 128;
pub const TMR4_ECSR_HOLD_POS: u32 = 7;
pub const TMR4_ECSR_HOLD: u32 = 128;
pub const TMR4_ECER_ECER_EMBVAL: u32 = 3;
pub const TMR6_CNTER_CNT: u32 = 65535;
pub const TMR6_PERAR_PERA: u32 = 65535;
pub const TMR6_PERBR_PERB: u32 = 65535;
pub const TMR6_PERCR_PERC: u32 = 65535;
pub const TMR6_GCMAR_GCMA: u32 = 65535;
pub const TMR6_GCMBR_GCMB: u32 = 65535;
pub const TMR6_GCMCR_GCMC: u32 = 65535;
pub const TMR6_GCMDR_GCMD: u32 = 65535;
pub const TMR6_GCMER_GCME: u32 = 65535;
pub const TMR6_GCMFR_GCMF: u32 = 65535;
pub const TMR6_SCMAR_SCMA: u32 = 65535;
pub const TMR6_SCMBR_SCMB: u32 = 65535;
pub const TMR6_SCMCR_SCMC: u32 = 65535;
pub const TMR6_SCMDR_SCMD: u32 = 65535;
pub const TMR6_SCMER_SCME: u32 = 65535;
pub const TMR6_SCMFR_SCMF: u32 = 65535;
pub const TMR6_DTUAR_DTUA: u32 = 65535;
pub const TMR6_DTDAR_DTDA: u32 = 65535;
pub const TMR6_DTUBR_DTUB: u32 = 65535;
pub const TMR6_DTDBR_DTDB: u32 = 65535;
pub const TMR6_GCONR_START_POS: u32 = 0;
pub const TMR6_GCONR_START: u32 = 1;
pub const TMR6_GCONR_MODE_POS: u32 = 1;
pub const TMR6_GCONR_MODE: u32 = 14;
pub const TMR6_GCONR_CKDIV_POS: u32 = 4;
pub const TMR6_GCONR_CKDIV: u32 = 112;
pub const TMR6_GCONR_DIR_POS: u32 = 8;
pub const TMR6_GCONR_DIR: u32 = 256;
pub const TMR6_GCONR_ZMSKREV_POS: u32 = 16;
pub const TMR6_GCONR_ZMSKREV: u32 = 65536;
pub const TMR6_GCONR_ZMSKPOS_POS: u32 = 17;
pub const TMR6_GCONR_ZMSKPOS: u32 = 131072;
pub const TMR6_GCONR_ZMSKVAL_POS: u32 = 18;
pub const TMR6_GCONR_ZMSKVAL: u32 = 786432;
pub const TMR6_GCONR_ZMSKVAL_0: u32 = 262144;
pub const TMR6_GCONR_ZMSKVAL_1: u32 = 524288;
pub const TMR6_ICONR_INTENA_POS: u32 = 0;
pub const TMR6_ICONR_INTENA: u32 = 1;
pub const TMR6_ICONR_INTENB_POS: u32 = 1;
pub const TMR6_ICONR_INTENB: u32 = 2;
pub const TMR6_ICONR_INTENC_POS: u32 = 2;
pub const TMR6_ICONR_INTENC: u32 = 4;
pub const TMR6_ICONR_INTEND_POS: u32 = 3;
pub const TMR6_ICONR_INTEND: u32 = 8;
pub const TMR6_ICONR_INTENE_POS: u32 = 4;
pub const TMR6_ICONR_INTENE: u32 = 16;
pub const TMR6_ICONR_INTENF_POS: u32 = 5;
pub const TMR6_ICONR_INTENF: u32 = 32;
pub const TMR6_ICONR_INTENOVF_POS: u32 = 6;
pub const TMR6_ICONR_INTENOVF: u32 = 64;
pub const TMR6_ICONR_INTENUDF_POS: u32 = 7;
pub const TMR6_ICONR_INTENUDF: u32 = 128;
pub const TMR6_ICONR_INTENDTE_POS: u32 = 8;
pub const TMR6_ICONR_INTENDTE: u32 = 256;
pub const TMR6_ICONR_INTENSAU_POS: u32 = 16;
pub const TMR6_ICONR_INTENSAU: u32 = 65536;
pub const TMR6_ICONR_INTENSAD_POS: u32 = 17;
pub const TMR6_ICONR_INTENSAD: u32 = 131072;
pub const TMR6_ICONR_INTENSBU_POS: u32 = 18;
pub const TMR6_ICONR_INTENSBU: u32 = 262144;
pub const TMR6_ICONR_INTENSBD_POS: u32 = 19;
pub const TMR6_ICONR_INTENSBD: u32 = 524288;
pub const TMR6_PCONR_CAPMDA_POS: u32 = 0;
pub const TMR6_PCONR_CAPMDA: u32 = 1;
pub const TMR6_PCONR_STACA_POS: u32 = 1;
pub const TMR6_PCONR_STACA: u32 = 2;
pub const TMR6_PCONR_STPCA_POS: u32 = 2;
pub const TMR6_PCONR_STPCA: u32 = 4;
pub const TMR6_PCONR_STASTPSA_POS: u32 = 3;
pub const TMR6_PCONR_STASTPSA: u32 = 8;
pub const TMR6_PCONR_CMPCA_POS: u32 = 4;
pub const TMR6_PCONR_CMPCA: u32 = 48;
pub const TMR6_PCONR_CMPCA_0: u32 = 16;
pub const TMR6_PCONR_CMPCA_1: u32 = 32;
pub const TMR6_PCONR_PERCA_POS: u32 = 6;
pub const TMR6_PCONR_PERCA: u32 = 192;
pub const TMR6_PCONR_PERCA_0: u32 = 64;
pub const TMR6_PCONR_PERCA_1: u32 = 128;
pub const TMR6_PCONR_OUTENA_POS: u32 = 8;
pub const TMR6_PCONR_OUTENA: u32 = 256;
pub const TMR6_PCONR_EMBVALA_POS: u32 = 11;
pub const TMR6_PCONR_EMBVALA: u32 = 6144;
pub const TMR6_PCONR_EMBVALA_0: u32 = 2048;
pub const TMR6_PCONR_EMBVALA_1: u32 = 4096;
pub const TMR6_PCONR_CAPMDB_POS: u32 = 16;
pub const TMR6_PCONR_CAPMDB: u32 = 65536;
pub const TMR6_PCONR_STACB_POS: u32 = 17;
pub const TMR6_PCONR_STACB: u32 = 131072;
pub const TMR6_PCONR_STPCB_POS: u32 = 18;
pub const TMR6_PCONR_STPCB: u32 = 262144;
pub const TMR6_PCONR_STASTPSB_POS: u32 = 19;
pub const TMR6_PCONR_STASTPSB: u32 = 524288;
pub const TMR6_PCONR_CMPCB_POS: u32 = 20;
pub const TMR6_PCONR_CMPCB: u32 = 3145728;
pub const TMR6_PCONR_CMPCB_0: u32 = 1048576;
pub const TMR6_PCONR_CMPCB_1: u32 = 2097152;
pub const TMR6_PCONR_PERCB_POS: u32 = 22;
pub const TMR6_PCONR_PERCB: u32 = 12582912;
pub const TMR6_PCONR_PERCB_0: u32 = 4194304;
pub const TMR6_PCONR_PERCB_1: u32 = 8388608;
pub const TMR6_PCONR_OUTENB_POS: u32 = 24;
pub const TMR6_PCONR_OUTENB: u32 = 16777216;
pub const TMR6_PCONR_EMBVALB_POS: u32 = 27;
pub const TMR6_PCONR_EMBVALB: u32 = 402653184;
pub const TMR6_PCONR_EMBVALB_0: u32 = 134217728;
pub const TMR6_PCONR_EMBVALB_1: u32 = 268435456;
pub const TMR6_BCONR_BENA_POS: u32 = 0;
pub const TMR6_BCONR_BENA: u32 = 1;
pub const TMR6_BCONR_BSEA_POS: u32 = 1;
pub const TMR6_BCONR_BSEA: u32 = 2;
pub const TMR6_BCONR_BENB_POS: u32 = 2;
pub const TMR6_BCONR_BENB: u32 = 4;
pub const TMR6_BCONR_BSEB_POS: u32 = 3;
pub const TMR6_BCONR_BSEB: u32 = 8;
pub const TMR6_BCONR_BENP_POS: u32 = 8;
pub const TMR6_BCONR_BENP: u32 = 256;
pub const TMR6_BCONR_BSEP_POS: u32 = 9;
pub const TMR6_BCONR_BSEP: u32 = 512;
pub const TMR6_BCONR_BENSPA_POS: u32 = 16;
pub const TMR6_BCONR_BENSPA: u32 = 65536;
pub const TMR6_BCONR_BSESPA_POS: u32 = 17;
pub const TMR6_BCONR_BSESPA: u32 = 131072;
pub const TMR6_BCONR_BTRUSPA_POS: u32 = 20;
pub const TMR6_BCONR_BTRUSPA: u32 = 1048576;
pub const TMR6_BCONR_BTRDSPA_POS: u32 = 21;
pub const TMR6_BCONR_BTRDSPA: u32 = 2097152;
pub const TMR6_BCONR_BENSPB_POS: u32 = 24;
pub const TMR6_BCONR_BENSPB: u32 = 16777216;
pub const TMR6_BCONR_BSESPB_POS: u32 = 25;
pub const TMR6_BCONR_BSESPB: u32 = 33554432;
pub const TMR6_BCONR_BTRUSPB_POS: u32 = 28;
pub const TMR6_BCONR_BTRUSPB: u32 = 268435456;
pub const TMR6_BCONR_BTRDSPB_POS: u32 = 29;
pub const TMR6_BCONR_BTRDSPB: u32 = 536870912;
pub const TMR6_DCONR_DTCEN_POS: u32 = 0;
pub const TMR6_DCONR_DTCEN: u32 = 1;
pub const TMR6_DCONR_DTBENU_POS: u32 = 4;
pub const TMR6_DCONR_DTBENU: u32 = 16;
pub const TMR6_DCONR_DTBEND_POS: u32 = 5;
pub const TMR6_DCONR_DTBEND: u32 = 32;
pub const TMR6_DCONR_SEPA_POS: u32 = 8;
pub const TMR6_DCONR_SEPA: u32 = 256;
pub const TMR6_FCONR_NOFIENGA_POS: u32 = 0;
pub const TMR6_FCONR_NOFIENGA: u32 = 1;
pub const TMR6_FCONR_NOFICKGA_POS: u32 = 1;
pub const TMR6_FCONR_NOFICKGA: u32 = 6;
pub const TMR6_FCONR_NOFICKGA_0: u32 = 2;
pub const TMR6_FCONR_NOFICKGA_1: u32 = 4;
pub const TMR6_FCONR_NOFIENGB_POS: u32 = 4;
pub const TMR6_FCONR_NOFIENGB: u32 = 16;
pub const TMR6_FCONR_NOFICKGB_POS: u32 = 5;
pub const TMR6_FCONR_NOFICKGB: u32 = 96;
pub const TMR6_FCONR_NOFICKGB_0: u32 = 32;
pub const TMR6_FCONR_NOFICKGB_1: u32 = 64;
pub const TMR6_FCONR_NOFIENTA_POS: u32 = 16;
pub const TMR6_FCONR_NOFIENTA: u32 = 65536;
pub const TMR6_FCONR_NOFICKTA_POS: u32 = 17;
pub const TMR6_FCONR_NOFICKTA: u32 = 393216;
pub const TMR6_FCONR_NOFICKTA_0: u32 = 131072;
pub const TMR6_FCONR_NOFICKTA_1: u32 = 262144;
pub const TMR6_FCONR_NOFIENTB_POS: u32 = 20;
pub const TMR6_FCONR_NOFIENTB: u32 = 1048576;
pub const TMR6_FCONR_NOFICKTB_POS: u32 = 21;
pub const TMR6_FCONR_NOFICKTB: u32 = 6291456;
pub const TMR6_FCONR_NOFICKTB_0: u32 = 2097152;
pub const TMR6_FCONR_NOFICKTB_1: u32 = 4194304;
pub const TMR6_VPERR_SPPERIA_POS: u32 = 8;
pub const TMR6_VPERR_SPPERIA: u32 = 256;
pub const TMR6_VPERR_SPPERIB_POS: u32 = 9;
pub const TMR6_VPERR_SPPERIB: u32 = 512;
pub const TMR6_VPERR_PCNTE_POS: u32 = 16;
pub const TMR6_VPERR_PCNTE: u32 = 196608;
pub const TMR6_VPERR_PCNTE_0: u32 = 65536;
pub const TMR6_VPERR_PCNTE_1: u32 = 131072;
pub const TMR6_VPERR_PCNTS_POS: u32 = 18;
pub const TMR6_VPERR_PCNTS: u32 = 1835008;
pub const TMR6_STFLR_CMAF_POS: u32 = 0;
pub const TMR6_STFLR_CMAF: u32 = 1;
pub const TMR6_STFLR_CMBF_POS: u32 = 1;
pub const TMR6_STFLR_CMBF: u32 = 2;
pub const TMR6_STFLR_CMCF_POS: u32 = 2;
pub const TMR6_STFLR_CMCF: u32 = 4;
pub const TMR6_STFLR_CMDF_POS: u32 = 3;
pub const TMR6_STFLR_CMDF: u32 = 8;
pub const TMR6_STFLR_CMEF_POS: u32 = 4;
pub const TMR6_STFLR_CMEF: u32 = 16;
pub const TMR6_STFLR_CMFF_POS: u32 = 5;
pub const TMR6_STFLR_CMFF: u32 = 32;
pub const TMR6_STFLR_OVFF_POS: u32 = 6;
pub const TMR6_STFLR_OVFF: u32 = 64;
pub const TMR6_STFLR_UDFF_POS: u32 = 7;
pub const TMR6_STFLR_UDFF: u32 = 128;
pub const TMR6_STFLR_DTEF_POS: u32 = 8;
pub const TMR6_STFLR_DTEF: u32 = 256;
pub const TMR6_STFLR_CMSAUF_POS: u32 = 9;
pub const TMR6_STFLR_CMSAUF: u32 = 512;
pub const TMR6_STFLR_CMSADF_POS: u32 = 10;
pub const TMR6_STFLR_CMSADF: u32 = 1024;
pub const TMR6_STFLR_CMSBUF_POS: u32 = 11;
pub const TMR6_STFLR_CMSBUF: u32 = 2048;
pub const TMR6_STFLR_CMSBDF_POS: u32 = 12;
pub const TMR6_STFLR_CMSBDF: u32 = 4096;
pub const TMR6_STFLR_VPERNUM_POS: u32 = 21;
pub const TMR6_STFLR_VPERNUM: u32 = 14680064;
pub const TMR6_STFLR_DIRF_POS: u32 = 31;
pub const TMR6_STFLR_DIRF: u32 = 2147483648;
pub const TMR6_HSTAR_HSTA0_POS: u32 = 0;
pub const TMR6_HSTAR_HSTA0: u32 = 1;
pub const TMR6_HSTAR_HSTA1_POS: u32 = 1;
pub const TMR6_HSTAR_HSTA1: u32 = 2;
pub const TMR6_HSTAR_HSTA4_POS: u32 = 4;
pub const TMR6_HSTAR_HSTA4: u32 = 16;
pub const TMR6_HSTAR_HSTA5_POS: u32 = 5;
pub const TMR6_HSTAR_HSTA5: u32 = 32;
pub const TMR6_HSTAR_HSTA6_POS: u32 = 6;
pub const TMR6_HSTAR_HSTA6: u32 = 64;
pub const TMR6_HSTAR_HSTA7_POS: u32 = 7;
pub const TMR6_HSTAR_HSTA7: u32 = 128;
pub const TMR6_HSTAR_HSTA8_POS: u32 = 8;
pub const TMR6_HSTAR_HSTA8: u32 = 256;
pub const TMR6_HSTAR_HSTA9_POS: u32 = 9;
pub const TMR6_HSTAR_HSTA9: u32 = 512;
pub const TMR6_HSTAR_HSTA10_POS: u32 = 10;
pub const TMR6_HSTAR_HSTA10: u32 = 1024;
pub const TMR6_HSTAR_HSTA11_POS: u32 = 11;
pub const TMR6_HSTAR_HSTA11: u32 = 2048;
pub const TMR6_HSTAR_STAS_POS: u32 = 31;
pub const TMR6_HSTAR_STAS: u32 = 2147483648;
pub const TMR6_HSTPR_HSTP0_POS: u32 = 0;
pub const TMR6_HSTPR_HSTP0: u32 = 1;
pub const TMR6_HSTPR_HSTP1_POS: u32 = 1;
pub const TMR6_HSTPR_HSTP1: u32 = 2;
pub const TMR6_HSTPR_HSTP4_POS: u32 = 4;
pub const TMR6_HSTPR_HSTP4: u32 = 16;
pub const TMR6_HSTPR_HSTP5_POS: u32 = 5;
pub const TMR6_HSTPR_HSTP5: u32 = 32;
pub const TMR6_HSTPR_HSTP6_POS: u32 = 6;
pub const TMR6_HSTPR_HSTP6: u32 = 64;
pub const TMR6_HSTPR_HSTP7_POS: u32 = 7;
pub const TMR6_HSTPR_HSTP7: u32 = 128;
pub const TMR6_HSTPR_HSTP8_POS: u32 = 8;
pub const TMR6_HSTPR_HSTP8: u32 = 256;
pub const TMR6_HSTPR_HSTP9_POS: u32 = 9;
pub const TMR6_HSTPR_HSTP9: u32 = 512;
pub const TMR6_HSTPR_HSTP10_POS: u32 = 10;
pub const TMR6_HSTPR_HSTP10: u32 = 1024;
pub const TMR6_HSTPR_HSTP11_POS: u32 = 11;
pub const TMR6_HSTPR_HSTP11: u32 = 2048;
pub const TMR6_HSTPR_STPS_POS: u32 = 31;
pub const TMR6_HSTPR_STPS: u32 = 2147483648;
pub const TMR6_HCLRR_HCLE0_POS: u32 = 0;
pub const TMR6_HCLRR_HCLE0: u32 = 1;
pub const TMR6_HCLRR_HCLE1_POS: u32 = 1;
pub const TMR6_HCLRR_HCLE1: u32 = 2;
pub const TMR6_HCLRR_HCLE4_POS: u32 = 4;
pub const TMR6_HCLRR_HCLE4: u32 = 16;
pub const TMR6_HCLRR_HCLE5_POS: u32 = 5;
pub const TMR6_HCLRR_HCLE5: u32 = 32;
pub const TMR6_HCLRR_HCLE6_POS: u32 = 6;
pub const TMR6_HCLRR_HCLE6: u32 = 64;
pub const TMR6_HCLRR_HCLE7_POS: u32 = 7;
pub const TMR6_HCLRR_HCLE7: u32 = 128;
pub const TMR6_HCLRR_HCLE8_POS: u32 = 8;
pub const TMR6_HCLRR_HCLE8: u32 = 256;
pub const TMR6_HCLRR_HCLE9_POS: u32 = 9;
pub const TMR6_HCLRR_HCLE9: u32 = 512;
pub const TMR6_HCLRR_HCLE10_POS: u32 = 10;
pub const TMR6_HCLRR_HCLE10: u32 = 1024;
pub const TMR6_HCLRR_HCLE11_POS: u32 = 11;
pub const TMR6_HCLRR_HCLE11: u32 = 2048;
pub const TMR6_HCLRR_CLES_POS: u32 = 31;
pub const TMR6_HCLRR_CLES: u32 = 2147483648;
pub const TMR6_HCPAR_HCPA0_POS: u32 = 0;
pub const TMR6_HCPAR_HCPA0: u32 = 1;
pub const TMR6_HCPAR_HCPA1_POS: u32 = 1;
pub const TMR6_HCPAR_HCPA1: u32 = 2;
pub const TMR6_HCPAR_HCPA4_POS: u32 = 4;
pub const TMR6_HCPAR_HCPA4: u32 = 16;
pub const TMR6_HCPAR_HCPA5_POS: u32 = 5;
pub const TMR6_HCPAR_HCPA5: u32 = 32;
pub const TMR6_HCPAR_HCPA6_POS: u32 = 6;
pub const TMR6_HCPAR_HCPA6: u32 = 64;
pub const TMR6_HCPAR_HCPA7_POS: u32 = 7;
pub const TMR6_HCPAR_HCPA7: u32 = 128;
pub const TMR6_HCPAR_HCPA8_POS: u32 = 8;
pub const TMR6_HCPAR_HCPA8: u32 = 256;
pub const TMR6_HCPAR_HCPA9_POS: u32 = 9;
pub const TMR6_HCPAR_HCPA9: u32 = 512;
pub const TMR6_HCPAR_HCPA10_POS: u32 = 10;
pub const TMR6_HCPAR_HCPA10: u32 = 1024;
pub const TMR6_HCPAR_HCPA11_POS: u32 = 11;
pub const TMR6_HCPAR_HCPA11: u32 = 2048;
pub const TMR6_HCPBR_HCPB0_POS: u32 = 0;
pub const TMR6_HCPBR_HCPB0: u32 = 1;
pub const TMR6_HCPBR_HCPB1_POS: u32 = 1;
pub const TMR6_HCPBR_HCPB1: u32 = 2;
pub const TMR6_HCPBR_HCPB4_POS: u32 = 4;
pub const TMR6_HCPBR_HCPB4: u32 = 16;
pub const TMR6_HCPBR_HCPB5_POS: u32 = 5;
pub const TMR6_HCPBR_HCPB5: u32 = 32;
pub const TMR6_HCPBR_HCPB6_POS: u32 = 6;
pub const TMR6_HCPBR_HCPB6: u32 = 64;
pub const TMR6_HCPBR_HCPB7_POS: u32 = 7;
pub const TMR6_HCPBR_HCPB7: u32 = 128;
pub const TMR6_HCPBR_HCPB8_POS: u32 = 8;
pub const TMR6_HCPBR_HCPB8: u32 = 256;
pub const TMR6_HCPBR_HCPB9_POS: u32 = 9;
pub const TMR6_HCPBR_HCPB9: u32 = 512;
pub const TMR6_HCPBR_HCPB10_POS: u32 = 10;
pub const TMR6_HCPBR_HCPB10: u32 = 1024;
pub const TMR6_HCPBR_HCPB11_POS: u32 = 11;
pub const TMR6_HCPBR_HCPB11: u32 = 2048;
pub const TMR6_HCUPR_HCUP0_POS: u32 = 0;
pub const TMR6_HCUPR_HCUP0: u32 = 1;
pub const TMR6_HCUPR_HCUP1_POS: u32 = 1;
pub const TMR6_HCUPR_HCUP1: u32 = 2;
pub const TMR6_HCUPR_HCUP2_POS: u32 = 2;
pub const TMR6_HCUPR_HCUP2: u32 = 4;
pub const TMR6_HCUPR_HCUP3_POS: u32 = 3;
pub const TMR6_HCUPR_HCUP3: u32 = 8;
pub const TMR6_HCUPR_HCUP4_POS: u32 = 4;
pub const TMR6_HCUPR_HCUP4: u32 = 16;
pub const TMR6_HCUPR_HCUP5_POS: u32 = 5;
pub const TMR6_HCUPR_HCUP5: u32 = 32;
pub const TMR6_HCUPR_HCUP6_POS: u32 = 6;
pub const TMR6_HCUPR_HCUP6: u32 = 64;
pub const TMR6_HCUPR_HCUP7_POS: u32 = 7;
pub const TMR6_HCUPR_HCUP7: u32 = 128;
pub const TMR6_HCUPR_HCUP8_POS: u32 = 8;
pub const TMR6_HCUPR_HCUP8: u32 = 256;
pub const TMR6_HCUPR_HCUP9_POS: u32 = 9;
pub const TMR6_HCUPR_HCUP9: u32 = 512;
pub const TMR6_HCUPR_HCUP10_POS: u32 = 10;
pub const TMR6_HCUPR_HCUP10: u32 = 1024;
pub const TMR6_HCUPR_HCUP11_POS: u32 = 11;
pub const TMR6_HCUPR_HCUP11: u32 = 2048;
pub const TMR6_HCUPR_HCUP16_POS: u32 = 16;
pub const TMR6_HCUPR_HCUP16: u32 = 65536;
pub const TMR6_HCUPR_HCUP17_POS: u32 = 17;
pub const TMR6_HCUPR_HCUP17: u32 = 131072;
pub const TMR6_HCDOR_HCDO0_POS: u32 = 0;
pub const TMR6_HCDOR_HCDO0: u32 = 1;
pub const TMR6_HCDOR_HCDO1_POS: u32 = 1;
pub const TMR6_HCDOR_HCDO1: u32 = 2;
pub const TMR6_HCDOR_HCDO2_POS: u32 = 2;
pub const TMR6_HCDOR_HCDO2: u32 = 4;
pub const TMR6_HCDOR_HCDO3_POS: u32 = 3;
pub const TMR6_HCDOR_HCDO3: u32 = 8;
pub const TMR6_HCDOR_HCDO4_POS: u32 = 4;
pub const TMR6_HCDOR_HCDO4: u32 = 16;
pub const TMR6_HCDOR_HCDO5_POS: u32 = 5;
pub const TMR6_HCDOR_HCDO5: u32 = 32;
pub const TMR6_HCDOR_HCDO6_POS: u32 = 6;
pub const TMR6_HCDOR_HCDO6: u32 = 64;
pub const TMR6_HCDOR_HCDO7_POS: u32 = 7;
pub const TMR6_HCDOR_HCDO7: u32 = 128;
pub const TMR6_HCDOR_HCDO8_POS: u32 = 8;
pub const TMR6_HCDOR_HCDO8: u32 = 256;
pub const TMR6_HCDOR_HCDO9_POS: u32 = 9;
pub const TMR6_HCDOR_HCDO9: u32 = 512;
pub const TMR6_HCDOR_HCDO10_POS: u32 = 10;
pub const TMR6_HCDOR_HCDO10: u32 = 1024;
pub const TMR6_HCDOR_HCDO11_POS: u32 = 11;
pub const TMR6_HCDOR_HCDO11: u32 = 2048;
pub const TMR6_HCDOR_HCDO16_POS: u32 = 16;
pub const TMR6_HCDOR_HCDO16: u32 = 65536;
pub const TMR6_HCDOR_HCDO17_POS: u32 = 17;
pub const TMR6_HCDOR_HCDO17: u32 = 131072;
pub const TMR6_COMMON_SSTAR_SSTA1_POS: u32 = 0;
pub const TMR6_COMMON_SSTAR_SSTA1: u32 = 1;
pub const TMR6_COMMON_SSTAR_SSTA2_POS: u32 = 1;
pub const TMR6_COMMON_SSTAR_SSTA2: u32 = 2;
pub const TMR6_COMMON_SSTAR_SSTA3_POS: u32 = 2;
pub const TMR6_COMMON_SSTAR_SSTA3: u32 = 4;
pub const TMR6_COMMON_SSTPR_SSTP1_POS: u32 = 0;
pub const TMR6_COMMON_SSTPR_SSTP1: u32 = 1;
pub const TMR6_COMMON_SSTPR_SSTP2_POS: u32 = 1;
pub const TMR6_COMMON_SSTPR_SSTP2: u32 = 2;
pub const TMR6_COMMON_SSTPR_SSTP3_POS: u32 = 2;
pub const TMR6_COMMON_SSTPR_SSTP3: u32 = 4;
pub const TMR6_COMMON_SCLRR_SCLE1_POS: u32 = 0;
pub const TMR6_COMMON_SCLRR_SCLE1: u32 = 1;
pub const TMR6_COMMON_SCLRR_SCLE2_POS: u32 = 1;
pub const TMR6_COMMON_SCLRR_SCLE2: u32 = 2;
pub const TMR6_COMMON_SCLRR_SCLE3_POS: u32 = 2;
pub const TMR6_COMMON_SCLRR_SCLE3: u32 = 4;
pub const TMRA_CNTER_CNT: u32 = 65535;
pub const TMRA_PERAR_PER: u32 = 65535;
pub const TMRA_CMPAR_CMP: u32 = 65535;
pub const TMRA_BCSTRL_START_POS: u32 = 0;
pub const TMRA_BCSTRL_START: u32 = 1;
pub const TMRA_BCSTRL_DIR_POS: u32 = 1;
pub const TMRA_BCSTRL_DIR: u32 = 2;
pub const TMRA_BCSTRL_MODE_POS: u32 = 2;
pub const TMRA_BCSTRL_MODE: u32 = 4;
pub const TMRA_BCSTRL_SYNST_POS: u32 = 3;
pub const TMRA_BCSTRL_SYNST: u32 = 8;
pub const TMRA_BCSTRL_CKDIV_POS: u32 = 4;
pub const TMRA_BCSTRL_CKDIV: u32 = 240;
pub const TMRA_BCSTRH_OVSTP_POS: u32 = 0;
pub const TMRA_BCSTRH_OVSTP: u32 = 1;
pub const TMRA_BCSTRH_ITENOVF_POS: u32 = 4;
pub const TMRA_BCSTRH_ITENOVF: u32 = 16;
pub const TMRA_BCSTRH_ITENUDF_POS: u32 = 5;
pub const TMRA_BCSTRH_ITENUDF: u32 = 32;
pub const TMRA_BCSTRH_OVFF_POS: u32 = 6;
pub const TMRA_BCSTRH_OVFF: u32 = 64;
pub const TMRA_BCSTRH_UDFF_POS: u32 = 7;
pub const TMRA_BCSTRH_UDFF: u32 = 128;
pub const TMRA_HCONR_HSTA0_POS: u32 = 0;
pub const TMRA_HCONR_HSTA0: u32 = 1;
pub const TMRA_HCONR_HSTA1_POS: u32 = 1;
pub const TMRA_HCONR_HSTA1: u32 = 2;
pub const TMRA_HCONR_HSTA2_POS: u32 = 2;
pub const TMRA_HCONR_HSTA2: u32 = 4;
pub const TMRA_HCONR_HSTP0_POS: u32 = 4;
pub const TMRA_HCONR_HSTP0: u32 = 16;
pub const TMRA_HCONR_HSTP1_POS: u32 = 5;
pub const TMRA_HCONR_HSTP1: u32 = 32;
pub const TMRA_HCONR_HSTP2_POS: u32 = 6;
pub const TMRA_HCONR_HSTP2: u32 = 64;
pub const TMRA_HCONR_HCLE0_POS: u32 = 8;
pub const TMRA_HCONR_HCLE0: u32 = 256;
pub const TMRA_HCONR_HCLE1_POS: u32 = 9;
pub const TMRA_HCONR_HCLE1: u32 = 512;
pub const TMRA_HCONR_HCLE2_POS: u32 = 10;
pub const TMRA_HCONR_HCLE2: u32 = 1024;
pub const TMRA_HCONR_HCLE3_POS: u32 = 12;
pub const TMRA_HCONR_HCLE3: u32 = 4096;
pub const TMRA_HCONR_HCLE4_POS: u32 = 13;
pub const TMRA_HCONR_HCLE4: u32 = 8192;
pub const TMRA_HCONR_HCLE5_POS: u32 = 14;
pub const TMRA_HCONR_HCLE5: u32 = 16384;
pub const TMRA_HCONR_HCLE6_POS: u32 = 15;
pub const TMRA_HCONR_HCLE6: u32 = 32768;
pub const TMRA_HCUPR_HCUP0_POS: u32 = 0;
pub const TMRA_HCUPR_HCUP0: u32 = 1;
pub const TMRA_HCUPR_HCUP1_POS: u32 = 1;
pub const TMRA_HCUPR_HCUP1: u32 = 2;
pub const TMRA_HCUPR_HCUP2_POS: u32 = 2;
pub const TMRA_HCUPR_HCUP2: u32 = 4;
pub const TMRA_HCUPR_HCUP3_POS: u32 = 3;
pub const TMRA_HCUPR_HCUP3: u32 = 8;
pub const TMRA_HCUPR_HCUP4_POS: u32 = 4;
pub const TMRA_HCUPR_HCUP4: u32 = 16;
pub const TMRA_HCUPR_HCUP5_POS: u32 = 5;
pub const TMRA_HCUPR_HCUP5: u32 = 32;
pub const TMRA_HCUPR_HCUP6_POS: u32 = 6;
pub const TMRA_HCUPR_HCUP6: u32 = 64;
pub const TMRA_HCUPR_HCUP7_POS: u32 = 7;
pub const TMRA_HCUPR_HCUP7: u32 = 128;
pub const TMRA_HCUPR_HCUP8_POS: u32 = 8;
pub const TMRA_HCUPR_HCUP8: u32 = 256;
pub const TMRA_HCUPR_HCUP9_POS: u32 = 9;
pub const TMRA_HCUPR_HCUP9: u32 = 512;
pub const TMRA_HCUPR_HCUP10_POS: u32 = 10;
pub const TMRA_HCUPR_HCUP10: u32 = 1024;
pub const TMRA_HCUPR_HCUP11_POS: u32 = 11;
pub const TMRA_HCUPR_HCUP11: u32 = 2048;
pub const TMRA_HCUPR_HCUP12_POS: u32 = 12;
pub const TMRA_HCUPR_HCUP12: u32 = 4096;
pub const TMRA_HCDOR_HCDO0_POS: u32 = 0;
pub const TMRA_HCDOR_HCDO0: u32 = 1;
pub const TMRA_HCDOR_HCDO1_POS: u32 = 1;
pub const TMRA_HCDOR_HCDO1: u32 = 2;
pub const TMRA_HCDOR_HCDO2_POS: u32 = 2;
pub const TMRA_HCDOR_HCDO2: u32 = 4;
pub const TMRA_HCDOR_HCDO3_POS: u32 = 3;
pub const TMRA_HCDOR_HCDO3: u32 = 8;
pub const TMRA_HCDOR_HCDO4_POS: u32 = 4;
pub const TMRA_HCDOR_HCDO4: u32 = 16;
pub const TMRA_HCDOR_HCDO5_POS: u32 = 5;
pub const TMRA_HCDOR_HCDO5: u32 = 32;
pub const TMRA_HCDOR_HCDO6_POS: u32 = 6;
pub const TMRA_HCDOR_HCDO6: u32 = 64;
pub const TMRA_HCDOR_HCDO7_POS: u32 = 7;
pub const TMRA_HCDOR_HCDO7: u32 = 128;
pub const TMRA_HCDOR_HCDO8_POS: u32 = 8;
pub const TMRA_HCDOR_HCDO8: u32 = 256;
pub const TMRA_HCDOR_HCDO9_POS: u32 = 9;
pub const TMRA_HCDOR_HCDO9: u32 = 512;
pub const TMRA_HCDOR_HCDO10_POS: u32 = 10;
pub const TMRA_HCDOR_HCDO10: u32 = 1024;
pub const TMRA_HCDOR_HCDO11_POS: u32 = 11;
pub const TMRA_HCDOR_HCDO11: u32 = 2048;
pub const TMRA_HCDOR_HCDO12_POS: u32 = 12;
pub const TMRA_HCDOR_HCDO12: u32 = 4096;
pub const TMRA_ICONR_ITEN1_POS: u32 = 0;
pub const TMRA_ICONR_ITEN1: u32 = 1;
pub const TMRA_ICONR_ITEN2_POS: u32 = 1;
pub const TMRA_ICONR_ITEN2: u32 = 2;
pub const TMRA_ICONR_ITEN3_POS: u32 = 2;
pub const TMRA_ICONR_ITEN3: u32 = 4;
pub const TMRA_ICONR_ITEN4_POS: u32 = 3;
pub const TMRA_ICONR_ITEN4: u32 = 8;
pub const TMRA_ICONR_ITEN5_POS: u32 = 4;
pub const TMRA_ICONR_ITEN5: u32 = 16;
pub const TMRA_ICONR_ITEN6_POS: u32 = 5;
pub const TMRA_ICONR_ITEN6: u32 = 32;
pub const TMRA_ICONR_ITEN7_POS: u32 = 6;
pub const TMRA_ICONR_ITEN7: u32 = 64;
pub const TMRA_ICONR_ITEN8_POS: u32 = 7;
pub const TMRA_ICONR_ITEN8: u32 = 128;
pub const TMRA_ECONR_ETEN1_POS: u32 = 0;
pub const TMRA_ECONR_ETEN1: u32 = 1;
pub const TMRA_ECONR_ETEN2_POS: u32 = 1;
pub const TMRA_ECONR_ETEN2: u32 = 2;
pub const TMRA_ECONR_ETEN3_POS: u32 = 2;
pub const TMRA_ECONR_ETEN3: u32 = 4;
pub const TMRA_ECONR_ETEN4_POS: u32 = 3;
pub const TMRA_ECONR_ETEN4: u32 = 8;
pub const TMRA_ECONR_ETEN5_POS: u32 = 4;
pub const TMRA_ECONR_ETEN5: u32 = 16;
pub const TMRA_ECONR_ETEN6_POS: u32 = 5;
pub const TMRA_ECONR_ETEN6: u32 = 32;
pub const TMRA_ECONR_ETEN7_POS: u32 = 6;
pub const TMRA_ECONR_ETEN7: u32 = 64;
pub const TMRA_ECONR_ETEN8_POS: u32 = 7;
pub const TMRA_ECONR_ETEN8: u32 = 128;
pub const TMRA_FCONR_NOFIENTG_POS: u32 = 0;
pub const TMRA_FCONR_NOFIENTG: u32 = 1;
pub const TMRA_FCONR_NOFICKTG_POS: u32 = 1;
pub const TMRA_FCONR_NOFICKTG: u32 = 6;
pub const TMRA_FCONR_NOFIENCA_POS: u32 = 8;
pub const TMRA_FCONR_NOFIENCA: u32 = 256;
pub const TMRA_FCONR_NOFICKCA_POS: u32 = 9;
pub const TMRA_FCONR_NOFICKCA: u32 = 1536;
pub const TMRA_FCONR_NOFIENCB_POS: u32 = 12;
pub const TMRA_FCONR_NOFIENCB: u32 = 4096;
pub const TMRA_FCONR_NOFICKCB_POS: u32 = 13;
pub const TMRA_FCONR_NOFICKCB: u32 = 24576;
pub const TMRA_STFLR_CMPF1_POS: u32 = 0;
pub const TMRA_STFLR_CMPF1: u32 = 1;
pub const TMRA_STFLR_CMPF2_POS: u32 = 1;
pub const TMRA_STFLR_CMPF2: u32 = 2;
pub const TMRA_STFLR_CMPF3_POS: u32 = 2;
pub const TMRA_STFLR_CMPF3: u32 = 4;
pub const TMRA_STFLR_CMPF4_POS: u32 = 3;
pub const TMRA_STFLR_CMPF4: u32 = 8;
pub const TMRA_STFLR_CMPF5_POS: u32 = 4;
pub const TMRA_STFLR_CMPF5: u32 = 16;
pub const TMRA_STFLR_CMPF6_POS: u32 = 5;
pub const TMRA_STFLR_CMPF6: u32 = 32;
pub const TMRA_STFLR_CMPF7_POS: u32 = 6;
pub const TMRA_STFLR_CMPF7: u32 = 64;
pub const TMRA_STFLR_CMPF8_POS: u32 = 7;
pub const TMRA_STFLR_CMPF8: u32 = 128;
pub const TMRA_BCONR_BEN_POS: u32 = 0;
pub const TMRA_BCONR_BEN: u32 = 1;
pub const TMRA_BCONR_BSE0_POS: u32 = 1;
pub const TMRA_BCONR_BSE0: u32 = 2;
pub const TMRA_BCONR_BSE1_POS: u32 = 2;
pub const TMRA_BCONR_BSE1: u32 = 4;
pub const TMRA_CCONR_CAPMD_POS: u32 = 0;
pub const TMRA_CCONR_CAPMD: u32 = 1;
pub const TMRA_CCONR_HICP0_POS: u32 = 4;
pub const TMRA_CCONR_HICP0: u32 = 16;
pub const TMRA_CCONR_HICP1_POS: u32 = 5;
pub const TMRA_CCONR_HICP1: u32 = 32;
pub const TMRA_CCONR_HICP2_POS: u32 = 6;
pub const TMRA_CCONR_HICP2: u32 = 64;
pub const TMRA_CCONR_HICP3_POS: u32 = 8;
pub const TMRA_CCONR_HICP3: u32 = 256;
pub const TMRA_CCONR_HICP4_POS: u32 = 9;
pub const TMRA_CCONR_HICP4: u32 = 512;
pub const TMRA_CCONR_NOFIENCP_POS: u32 = 12;
pub const TMRA_CCONR_NOFIENCP: u32 = 4096;
pub const TMRA_CCONR_NOFICKCP_POS: u32 = 13;
pub const TMRA_CCONR_NOFICKCP: u32 = 24576;
pub const TMRA_CCONR_NOFICKCP_0: u32 = 8192;
pub const TMRA_CCONR_NOFICKCP_1: u32 = 16384;
pub const TMRA_PCONR_STAC_POS: u32 = 0;
pub const TMRA_PCONR_STAC: u32 = 3;
pub const TMRA_PCONR_STAC_0: u32 = 1;
pub const TMRA_PCONR_STAC_1: u32 = 2;
pub const TMRA_PCONR_STPC_POS: u32 = 2;
pub const TMRA_PCONR_STPC: u32 = 12;
pub const TMRA_PCONR_STPC_0: u32 = 4;
pub const TMRA_PCONR_STPC_1: u32 = 8;
pub const TMRA_PCONR_CMPC_POS: u32 = 4;
pub const TMRA_PCONR_CMPC: u32 = 48;
pub const TMRA_PCONR_CMPC_0: u32 = 16;
pub const TMRA_PCONR_CMPC_1: u32 = 32;
pub const TMRA_PCONR_PERC_POS: u32 = 6;
pub const TMRA_PCONR_PERC: u32 = 192;
pub const TMRA_PCONR_PERC_0: u32 = 64;
pub const TMRA_PCONR_PERC_1: u32 = 128;
pub const TMRA_PCONR_FORC_POS: u32 = 8;
pub const TMRA_PCONR_FORC: u32 = 768;
pub const TMRA_PCONR_FORC_0: u32 = 256;
pub const TMRA_PCONR_FORC_1: u32 = 512;
pub const TMRA_PCONR_OUTEN_POS: u32 = 12;
pub const TMRA_PCONR_OUTEN: u32 = 4096;
pub const TRNG_CR_EN_POS: u32 = 0;
pub const TRNG_CR_EN: u32 = 1;
pub const TRNG_CR_RUN_POS: u32 = 1;
pub const TRNG_CR_RUN: u32 = 2;
pub const TRNG_MR_LOAD_POS: u32 = 0;
pub const TRNG_MR_LOAD: u32 = 1;
pub const TRNG_MR_CNT_POS: u32 = 2;
pub const TRNG_MR_CNT: u32 = 28;
pub const TRNG_DR0: u32 = 4294967295;
pub const TRNG_DR1: u32 = 4294967295;
pub const USART_SR_PE_POS: u32 = 0;
pub const USART_SR_PE: u32 = 1;
pub const USART_SR_FE_POS: u32 = 1;
pub const USART_SR_FE: u32 = 2;
pub const USART_SR_ORE_POS: u32 = 3;
pub const USART_SR_ORE: u32 = 8;
pub const USART_SR_RXNE_POS: u32 = 5;
pub const USART_SR_RXNE: u32 = 32;
pub const USART_SR_TC_POS: u32 = 6;
pub const USART_SR_TC: u32 = 64;
pub const USART_SR_TXE_POS: u32 = 7;
pub const USART_SR_TXE: u32 = 128;
pub const USART_SR_RTOF_POS: u32 = 8;
pub const USART_SR_RTOF: u32 = 256;
pub const USART_SR_MPB_POS: u32 = 16;
pub const USART_SR_MPB: u32 = 65536;
pub const USART_TDR_TDR_POS: u32 = 0;
pub const USART_TDR_TDR: u32 = 511;
pub const USART_TDR_MPID_POS: u32 = 9;
pub const USART_TDR_MPID: u32 = 512;
pub const USART_RDR_RDR: u32 = 511;
pub const USART_BRR_DIV_FRACTION_POS: u32 = 0;
pub const USART_BRR_DIV_FRACTION: u32 = 127;
pub const USART_BRR_DIV_INTEGER_POS: u32 = 8;
pub const USART_BRR_DIV_INTEGER: u32 = 65280;
pub const USART_CR1_RTOE_POS: u32 = 0;
pub const USART_CR1_RTOE: u32 = 1;
pub const USART_CR1_RTOIE_POS: u32 = 1;
pub const USART_CR1_RTOIE: u32 = 2;
pub const USART_CR1_RE_POS: u32 = 2;
pub const USART_CR1_RE: u32 = 4;
pub const USART_CR1_TE_POS: u32 = 3;
pub const USART_CR1_TE: u32 = 8;
pub const USART_CR1_SLME_POS: u32 = 4;
pub const USART_CR1_SLME: u32 = 16;
pub const USART_CR1_RIE_POS: u32 = 5;
pub const USART_CR1_RIE: u32 = 32;
pub const USART_CR1_TCIE_POS: u32 = 6;
pub const USART_CR1_TCIE: u32 = 64;
pub const USART_CR1_TXEIE_POS: u32 = 7;
pub const USART_CR1_TXEIE: u32 = 128;
pub const USART_CR1_PS_POS: u32 = 9;
pub const USART_CR1_PS: u32 = 512;
pub const USART_CR1_PCE_POS: u32 = 10;
pub const USART_CR1_PCE: u32 = 1024;
pub const USART_CR1_M_POS: u32 = 12;
pub const USART_CR1_M: u32 = 4096;
pub const USART_CR1_OVER8_POS: u32 = 15;
pub const USART_CR1_OVER8: u32 = 32768;
pub const USART_CR1_CPE_POS: u32 = 16;
pub const USART_CR1_CPE: u32 = 65536;
pub const USART_CR1_CFE_POS: u32 = 17;
pub const USART_CR1_CFE: u32 = 131072;
pub const USART_CR1_CORE_POS: u32 = 19;
pub const USART_CR1_CORE: u32 = 524288;
pub const USART_CR1_CRTOF_POS: u32 = 20;
pub const USART_CR1_CRTOF: u32 = 1048576;
pub const USART_CR1_MS_POS: u32 = 24;
pub const USART_CR1_MS: u32 = 16777216;
pub const USART_CR1_ML_POS: u32 = 28;
pub const USART_CR1_ML: u32 = 268435456;
pub const USART_CR1_FBME_POS: u32 = 29;
pub const USART_CR1_FBME: u32 = 536870912;
pub const USART_CR1_NFE_POS: u32 = 30;
pub const USART_CR1_NFE: u32 = 1073741824;
pub const USART_CR1_SBS_POS: u32 = 31;
pub const USART_CR1_SBS: u32 = 2147483648;
pub const USART_CR2_MPE_POS: u32 = 0;
pub const USART_CR2_MPE: u32 = 1;
pub const USART_CR2_CLKC_POS: u32 = 11;
pub const USART_CR2_CLKC: u32 = 6144;
pub const USART_CR2_CLKC_0: u32 = 2048;
pub const USART_CR2_CLKC_1: u32 = 4096;
pub const USART_CR2_STOP_POS: u32 = 13;
pub const USART_CR2_STOP: u32 = 8192;
pub const USART_CR3_SCEN_POS: u32 = 5;
pub const USART_CR3_SCEN: u32 = 32;
pub const USART_CR3_CTSE_POS: u32 = 9;
pub const USART_CR3_CTSE: u32 = 512;
pub const USART_CR3_BCN_POS: u32 = 21;
pub const USART_CR3_BCN: u32 = 14680064;
pub const USART_PR_PSC: u32 = 3;
pub const USART_PR_PSC_0: u32 = 1;
pub const USART_PR_PSC_1: u32 = 2;
pub const USBFS_GVBUSCFG_VBUSOVEN_POS: u32 = 6;
pub const USBFS_GVBUSCFG_VBUSOVEN: u32 = 64;
pub const USBFS_GVBUSCFG_VBUSVAL_POS: u32 = 7;
pub const USBFS_GVBUSCFG_VBUSVAL: u32 = 128;
pub const USBFS_GAHBCFG_GINTMSK_POS: u32 = 0;
pub const USBFS_GAHBCFG_GINTMSK: u32 = 1;
pub const USBFS_GAHBCFG_HBSTLEN_POS: u32 = 1;
pub const USBFS_GAHBCFG_HBSTLEN: u32 = 30;
pub const USBFS_GAHBCFG_DMAEN_POS: u32 = 5;
pub const USBFS_GAHBCFG_DMAEN: u32 = 32;
pub const USBFS_GAHBCFG_TXFELVL_POS: u32 = 7;
pub const USBFS_GAHBCFG_TXFELVL: u32 = 128;
pub const USBFS_GAHBCFG_PTXFELVL_POS: u32 = 8;
pub const USBFS_GAHBCFG_PTXFELVL: u32 = 256;
pub const USBFS_GUSBCFG_TOCAL_POS: u32 = 0;
pub const USBFS_GUSBCFG_TOCAL: u32 = 7;
pub const USBFS_GUSBCFG_PHYSEL_POS: u32 = 6;
pub const USBFS_GUSBCFG_PHYSEL: u32 = 64;
pub const USBFS_GUSBCFG_TRDT_POS: u32 = 10;
pub const USBFS_GUSBCFG_TRDT: u32 = 15360;
pub const USBFS_GUSBCFG_FHMOD_POS: u32 = 29;
pub const USBFS_GUSBCFG_FHMOD: u32 = 536870912;
pub const USBFS_GUSBCFG_FDMOD_POS: u32 = 30;
pub const USBFS_GUSBCFG_FDMOD: u32 = 1073741824;
pub const USBFS_GRSTCTL_CSRST_POS: u32 = 0;
pub const USBFS_GRSTCTL_CSRST: u32 = 1;
pub const USBFS_GRSTCTL_HSRST_POS: u32 = 1;
pub const USBFS_GRSTCTL_HSRST: u32 = 2;
pub const USBFS_GRSTCTL_FCRST_POS: u32 = 2;
pub const USBFS_GRSTCTL_FCRST: u32 = 4;
pub const USBFS_GRSTCTL_RXFFLSH_POS: u32 = 4;
pub const USBFS_GRSTCTL_RXFFLSH: u32 = 16;
pub const USBFS_GRSTCTL_TXFFLSH_POS: u32 = 5;
pub const USBFS_GRSTCTL_TXFFLSH: u32 = 32;
pub const USBFS_GRSTCTL_TXFNUM_POS: u32 = 6;
pub const USBFS_GRSTCTL_TXFNUM: u32 = 1984;
pub const USBFS_GRSTCTL_DMAREQ_POS: u32 = 30;
pub const USBFS_GRSTCTL_DMAREQ: u32 = 1073741824;
pub const USBFS_GRSTCTL_AHBIDL_POS: u32 = 31;
pub const USBFS_GRSTCTL_AHBIDL: u32 = 2147483648;
pub const USBFS_GINTSTS_CMOD_POS: u32 = 0;
pub const USBFS_GINTSTS_CMOD: u32 = 1;
pub const USBFS_GINTSTS_MMIS_POS: u32 = 1;
pub const USBFS_GINTSTS_MMIS: u32 = 2;
pub const USBFS_GINTSTS_SOF_POS: u32 = 3;
pub const USBFS_GINTSTS_SOF: u32 = 8;
pub const USBFS_GINTSTS_RXFNE_POS: u32 = 4;
pub const USBFS_GINTSTS_RXFNE: u32 = 16;
pub const USBFS_GINTSTS_NPTXFE_POS: u32 = 5;
pub const USBFS_GINTSTS_NPTXFE: u32 = 32;
pub const USBFS_GINTSTS_GINAKEFF_POS: u32 = 6;
pub const USBFS_GINTSTS_GINAKEFF: u32 = 64;
pub const USBFS_GINTSTS_GONAKEFF_POS: u32 = 7;
pub const USBFS_GINTSTS_GONAKEFF: u32 = 128;
pub const USBFS_GINTSTS_ESUSP_POS: u32 = 10;
pub const USBFS_GINTSTS_ESUSP: u32 = 1024;
pub const USBFS_GINTSTS_USBSUSP_POS: u32 = 11;
pub const USBFS_GINTSTS_USBSUSP: u32 = 2048;
pub const USBFS_GINTSTS_USBRST_POS: u32 = 12;
pub const USBFS_GINTSTS_USBRST: u32 = 4096;
pub const USBFS_GINTSTS_ENUMDNE_POS: u32 = 13;
pub const USBFS_GINTSTS_ENUMDNE: u32 = 8192;
pub const USBFS_GINTSTS_ISOODRP_POS: u32 = 14;
pub const USBFS_GINTSTS_ISOODRP: u32 = 16384;
pub const USBFS_GINTSTS_EOPF_POS: u32 = 15;
pub const USBFS_GINTSTS_EOPF: u32 = 32768;
pub const USBFS_GINTSTS_IEPINT_POS: u32 = 18;
pub const USBFS_GINTSTS_IEPINT: u32 = 262144;
pub const USBFS_GINTSTS_OEPINT_POS: u32 = 19;
pub const USBFS_GINTSTS_OEPINT: u32 = 524288;
pub const USBFS_GINTSTS_IISOIXFR_POS: u32 = 20;
pub const USBFS_GINTSTS_IISOIXFR: u32 = 1048576;
pub const USBFS_GINTSTS_IPXFR_INCOMPISOOUT_POS: u32 = 21;
pub const USBFS_GINTSTS_IPXFR_INCOMPISOOUT: u32 = 2097152;
pub const USBFS_GINTSTS_DATAFSUSP_POS: u32 = 22;
pub const USBFS_GINTSTS_DATAFSUSP: u32 = 4194304;
pub const USBFS_GINTSTS_HPRTINT_POS: u32 = 24;
pub const USBFS_GINTSTS_HPRTINT: u32 = 16777216;
pub const USBFS_GINTSTS_HCINT_POS: u32 = 25;
pub const USBFS_GINTSTS_HCINT: u32 = 33554432;
pub const USBFS_GINTSTS_PTXFE_POS: u32 = 26;
pub const USBFS_GINTSTS_PTXFE: u32 = 67108864;
pub const USBFS_GINTSTS_CIDSCHG_POS: u32 = 28;
pub const USBFS_GINTSTS_CIDSCHG: u32 = 268435456;
pub const USBFS_GINTSTS_DISCINT_POS: u32 = 29;
pub const USBFS_GINTSTS_DISCINT: u32 = 536870912;
pub const USBFS_GINTSTS_VBUSVINT_POS: u32 = 30;
pub const USBFS_GINTSTS_VBUSVINT: u32 = 1073741824;
pub const USBFS_GINTSTS_WKUINT_POS: u32 = 31;
pub const USBFS_GINTSTS_WKUINT: u32 = 2147483648;
pub const USBFS_GINTMSK_MMISM_POS: u32 = 1;
pub const USBFS_GINTMSK_MMISM: u32 = 2;
pub const USBFS_GINTMSK_SOFM_POS: u32 = 3;
pub const USBFS_GINTMSK_SOFM: u32 = 8;
pub const USBFS_GINTMSK_RXFNEM_POS: u32 = 4;
pub const USBFS_GINTMSK_RXFNEM: u32 = 16;
pub const USBFS_GINTMSK_NPTXFEM_POS: u32 = 5;
pub const USBFS_GINTMSK_NPTXFEM: u32 = 32;
pub const USBFS_GINTMSK_GINAKEFFM_POS: u32 = 6;
pub const USBFS_GINTMSK_GINAKEFFM: u32 = 64;
pub const USBFS_GINTMSK_GONAKEFFM_POS: u32 = 7;
pub const USBFS_GINTMSK_GONAKEFFM: u32 = 128;
pub const USBFS_GINTMSK_ESUSPM_POS: u32 = 10;
pub const USBFS_GINTMSK_ESUSPM: u32 = 1024;
pub const USBFS_GINTMSK_USBSUSPM_POS: u32 = 11;
pub const USBFS_GINTMSK_USBSUSPM: u32 = 2048;
pub const USBFS_GINTMSK_USBRSTM_POS: u32 = 12;
pub const USBFS_GINTMSK_USBRSTM: u32 = 4096;
pub const USBFS_GINTMSK_ENUMDNEM_POS: u32 = 13;
pub const USBFS_GINTMSK_ENUMDNEM: u32 = 8192;
pub const USBFS_GINTMSK_ISOODRPM_POS: u32 = 14;
pub const USBFS_GINTMSK_ISOODRPM: u32 = 16384;
pub const USBFS_GINTMSK_EOPFM_POS: u32 = 15;
pub const USBFS_GINTMSK_EOPFM: u32 = 32768;
pub const USBFS_GINTMSK_IEPIM_POS: u32 = 18;
pub const USBFS_GINTMSK_IEPIM: u32 = 262144;
pub const USBFS_GINTMSK_OEPIM_POS: u32 = 19;
pub const USBFS_GINTMSK_OEPIM: u32 = 524288;
pub const USBFS_GINTMSK_IISOIXFRM_POS: u32 = 20;
pub const USBFS_GINTMSK_IISOIXFRM: u32 = 1048576;
pub const USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS: u32 = 21;
pub const USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM: u32 = 2097152;
pub const USBFS_GINTMSK_DATAFSUSPM_POS: u32 = 22;
pub const USBFS_GINTMSK_DATAFSUSPM: u32 = 4194304;
pub const USBFS_GINTMSK_HPRTIM_POS: u32 = 24;
pub const USBFS_GINTMSK_HPRTIM: u32 = 16777216;
pub const USBFS_GINTMSK_HCIM_POS: u32 = 25;
pub const USBFS_GINTMSK_HCIM: u32 = 33554432;
pub const USBFS_GINTMSK_PTXFEM_POS: u32 = 26;
pub const USBFS_GINTMSK_PTXFEM: u32 = 67108864;
pub const USBFS_GINTMSK_CIDSCHGM_POS: u32 = 28;
pub const USBFS_GINTMSK_CIDSCHGM: u32 = 268435456;
pub const USBFS_GINTMSK_DISCIM_POS: u32 = 29;
pub const USBFS_GINTMSK_DISCIM: u32 = 536870912;
pub const USBFS_GINTMSK_VBUSVIM_POS: u32 = 30;
pub const USBFS_GINTMSK_VBUSVIM: u32 = 1073741824;
pub const USBFS_GINTMSK_WKUIM_POS: u32 = 31;
pub const USBFS_GINTMSK_WKUIM: u32 = 2147483648;
pub const USBFS_GRXSTSR_CHNUM_EPNUM_POS: u32 = 0;
pub const USBFS_GRXSTSR_CHNUM_EPNUM: u32 = 15;
pub const USBFS_GRXSTSR_BCNT_POS: u32 = 4;
pub const USBFS_GRXSTSR_BCNT: u32 = 32752;
pub const USBFS_GRXSTSR_DPID_POS: u32 = 15;
pub const USBFS_GRXSTSR_DPID: u32 = 98304;
pub const USBFS_GRXSTSR_PKTSTS_POS: u32 = 17;
pub const USBFS_GRXSTSR_PKTSTS: u32 = 1966080;
pub const USBFS_GRXSTSP_CHNUM_EPNUM_POS: u32 = 0;
pub const USBFS_GRXSTSP_CHNUM_EPNUM: u32 = 15;
pub const USBFS_GRXSTSP_BCNT_POS: u32 = 4;
pub const USBFS_GRXSTSP_BCNT: u32 = 32752;
pub const USBFS_GRXSTSP_DPID_POS: u32 = 15;
pub const USBFS_GRXSTSP_DPID: u32 = 98304;
pub const USBFS_GRXSTSP_PKTSTS_POS: u32 = 17;
pub const USBFS_GRXSTSP_PKTSTS: u32 = 1966080;
pub const USBFS_GRXFSIZ_RXFD: u32 = 2047;
pub const USBFS_HNPTXFSIZ_NPTXFSA_POS: u32 = 0;
pub const USBFS_HNPTXFSIZ_NPTXFSA: u32 = 65535;
pub const USBFS_HNPTXFSIZ_NPTXFD_POS: u32 = 16;
pub const USBFS_HNPTXFSIZ_NPTXFD: u32 = 4294901760;
pub const USBFS_HNPTXSTS_NPTXFSAV_POS: u32 = 0;
pub const USBFS_HNPTXSTS_NPTXFSAV: u32 = 65535;
pub const USBFS_HNPTXSTS_NPTQXSAV_POS: u32 = 16;
pub const USBFS_HNPTXSTS_NPTQXSAV: u32 = 16711680;
pub const USBFS_HNPTXSTS_NPTXQTOP_POS: u32 = 24;
pub const USBFS_HNPTXSTS_NPTXQTOP: u32 = 2130706432;
pub const USBFS_CID: u32 = 4294967295;
pub const USBFS_HPTXFSIZ_PTXSA_POS: u32 = 0;
pub const USBFS_HPTXFSIZ_PTXSA: u32 = 4095;
pub const USBFS_HPTXFSIZ_PTXFD_POS: u32 = 16;
pub const USBFS_HPTXFSIZ_PTXFD: u32 = 134152192;
pub const USBFS_DIEPTXF_INEPTXSA_POS: u32 = 0;
pub const USBFS_DIEPTXF_INEPTXSA: u32 = 4095;
pub const USBFS_DIEPTXF_INEPTXFD_POS: u32 = 16;
pub const USBFS_DIEPTXF_INEPTXFD: u32 = 67043328;
pub const USBFS_HCFG_FSLSPCS_POS: u32 = 0;
pub const USBFS_HCFG_FSLSPCS: u32 = 3;
pub const USBFS_HCFG_FSLSS_POS: u32 = 2;
pub const USBFS_HCFG_FSLSS: u32 = 4;
pub const USBFS_HFIR_FRIVL: u32 = 65535;
pub const USBFS_HFNUM_FRNUM_POS: u32 = 0;
pub const USBFS_HFNUM_FRNUM: u32 = 65535;
pub const USBFS_HFNUM_FTREM_POS: u32 = 16;
pub const USBFS_HFNUM_FTREM: u32 = 4294901760;
pub const USBFS_HPTXSTS_PTXFSAVL_POS: u32 = 0;
pub const USBFS_HPTXSTS_PTXFSAVL: u32 = 65535;
pub const USBFS_HPTXSTS_PTXQSAV_POS: u32 = 16;
pub const USBFS_HPTXSTS_PTXQSAV: u32 = 16711680;
pub const USBFS_HPTXSTS_PTXQTOP_POS: u32 = 24;
pub const USBFS_HPTXSTS_PTXQTOP: u32 = 4278190080;
pub const USBFS_HAINT_HAINT: u32 = 4095;
pub const USBFS_HAINTMSK_HAINTM: u32 = 4095;
pub const USBFS_HPRT_PCSTS_POS: u32 = 0;
pub const USBFS_HPRT_PCSTS: u32 = 1;
pub const USBFS_HPRT_PCDET_POS: u32 = 1;
pub const USBFS_HPRT_PCDET: u32 = 2;
pub const USBFS_HPRT_PENA_POS: u32 = 2;
pub const USBFS_HPRT_PENA: u32 = 4;
pub const USBFS_HPRT_PENCHNG_POS: u32 = 3;
pub const USBFS_HPRT_PENCHNG: u32 = 8;
pub const USBFS_HPRT_PRES_POS: u32 = 6;
pub const USBFS_HPRT_PRES: u32 = 64;
pub const USBFS_HPRT_PSUSP_POS: u32 = 7;
pub const USBFS_HPRT_PSUSP: u32 = 128;
pub const USBFS_HPRT_PRST_POS: u32 = 8;
pub const USBFS_HPRT_PRST: u32 = 256;
pub const USBFS_HPRT_PLSTS_POS: u32 = 10;
pub const USBFS_HPRT_PLSTS: u32 = 3072;
pub const USBFS_HPRT_PWPR_POS: u32 = 12;
pub const USBFS_HPRT_PWPR: u32 = 4096;
pub const USBFS_HPRT_PSPD_POS: u32 = 17;
pub const USBFS_HPRT_PSPD: u32 = 393216;
pub const USBFS_HCCHAR_MPSIZ_POS: u32 = 0;
pub const USBFS_HCCHAR_MPSIZ: u32 = 2047;
pub const USBFS_HCCHAR_EPNUM_POS: u32 = 11;
pub const USBFS_HCCHAR_EPNUM: u32 = 30720;
pub const USBFS_HCCHAR_EPDIR_POS: u32 = 15;
pub const USBFS_HCCHAR_EPDIR: u32 = 32768;
pub const USBFS_HCCHAR_LSDEV_POS: u32 = 17;
pub const USBFS_HCCHAR_LSDEV: u32 = 131072;
pub const USBFS_HCCHAR_EPTYP_POS: u32 = 18;
pub const USBFS_HCCHAR_EPTYP: u32 = 786432;
pub const USBFS_HCCHAR_DAD_POS: u32 = 22;
pub const USBFS_HCCHAR_DAD: u32 = 532676608;
pub const USBFS_HCCHAR_ODDFRM_POS: u32 = 29;
pub const USBFS_HCCHAR_ODDFRM: u32 = 536870912;
pub const USBFS_HCCHAR_CHDIS_POS: u32 = 30;
pub const USBFS_HCCHAR_CHDIS: u32 = 1073741824;
pub const USBFS_HCCHAR_CHENA_POS: u32 = 31;
pub const USBFS_HCCHAR_CHENA: u32 = 2147483648;
pub const USBFS_HCINT_XFRC_POS: u32 = 0;
pub const USBFS_HCINT_XFRC: u32 = 1;
pub const USBFS_HCINT_CHH_POS: u32 = 1;
pub const USBFS_HCINT_CHH: u32 = 2;
pub const USBFS_HCINT_STALL_POS: u32 = 3;
pub const USBFS_HCINT_STALL: u32 = 8;
pub const USBFS_HCINT_NAK_POS: u32 = 4;
pub const USBFS_HCINT_NAK: u32 = 16;
pub const USBFS_HCINT_ACK_POS: u32 = 5;
pub const USBFS_HCINT_ACK: u32 = 32;
pub const USBFS_HCINT_TXERR_POS: u32 = 7;
pub const USBFS_HCINT_TXERR: u32 = 128;
pub const USBFS_HCINT_BBERR_POS: u32 = 8;
pub const USBFS_HCINT_BBERR: u32 = 256;
pub const USBFS_HCINT_FRMOR_POS: u32 = 9;
pub const USBFS_HCINT_FRMOR: u32 = 512;
pub const USBFS_HCINT_DTERR_POS: u32 = 10;
pub const USBFS_HCINT_DTERR: u32 = 1024;
pub const USBFS_HCINTMSK_XFRCM_POS: u32 = 0;
pub const USBFS_HCINTMSK_XFRCM: u32 = 1;
pub const USBFS_HCINTMSK_CHHM_POS: u32 = 1;
pub const USBFS_HCINTMSK_CHHM: u32 = 2;
pub const USBFS_HCINTMSK_STALLM_POS: u32 = 3;
pub const USBFS_HCINTMSK_STALLM: u32 = 8;
pub const USBFS_HCINTMSK_NAKM_POS: u32 = 4;
pub const USBFS_HCINTMSK_NAKM: u32 = 16;
pub const USBFS_HCINTMSK_ACKM_POS: u32 = 5;
pub const USBFS_HCINTMSK_ACKM: u32 = 32;
pub const USBFS_HCINTMSK_TXERRM_POS: u32 = 7;
pub const USBFS_HCINTMSK_TXERRM: u32 = 128;
pub const USBFS_HCINTMSK_BBERRM_POS: u32 = 8;
pub const USBFS_HCINTMSK_BBERRM: u32 = 256;
pub const USBFS_HCINTMSK_FRMORM_POS: u32 = 9;
pub const USBFS_HCINTMSK_FRMORM: u32 = 512;
pub const USBFS_HCINTMSK_DTERRM_POS: u32 = 10;
pub const USBFS_HCINTMSK_DTERRM: u32 = 1024;
pub const USBFS_HCTSIZ_XFRSIZ_POS: u32 = 0;
pub const USBFS_HCTSIZ_XFRSIZ: u32 = 524287;
pub const USBFS_HCTSIZ_PKTCNT_POS: u32 = 19;
pub const USBFS_HCTSIZ_PKTCNT: u32 = 536346624;
pub const USBFS_HCTSIZ_DPID_POS: u32 = 29;
pub const USBFS_HCTSIZ_DPID: u32 = 1610612736;
pub const USBFS_HCDMA: u32 = 4294967295;
pub const USBFS_DCFG_DSPD_POS: u32 = 0;
pub const USBFS_DCFG_DSPD: u32 = 3;
pub const USBFS_DCFG_NZLSOHSK_POS: u32 = 2;
pub const USBFS_DCFG_NZLSOHSK: u32 = 4;
pub const USBFS_DCFG_DAD_POS: u32 = 4;
pub const USBFS_DCFG_DAD: u32 = 2032;
pub const USBFS_DCFG_PFIVL_POS: u32 = 11;
pub const USBFS_DCFG_PFIVL: u32 = 6144;
pub const USBFS_DCTL_RWUSIG_POS: u32 = 0;
pub const USBFS_DCTL_RWUSIG: u32 = 1;
pub const USBFS_DCTL_SDIS_POS: u32 = 1;
pub const USBFS_DCTL_SDIS: u32 = 2;
pub const USBFS_DCTL_GINSTS_POS: u32 = 2;
pub const USBFS_DCTL_GINSTS: u32 = 4;
pub const USBFS_DCTL_GONSTS_POS: u32 = 3;
pub const USBFS_DCTL_GONSTS: u32 = 8;
pub const USBFS_DCTL_SGINAK_POS: u32 = 7;
pub const USBFS_DCTL_SGINAK: u32 = 128;
pub const USBFS_DCTL_CGINAK_POS: u32 = 8;
pub const USBFS_DCTL_CGINAK: u32 = 256;
pub const USBFS_DCTL_SGONAK_POS: u32 = 9;
pub const USBFS_DCTL_SGONAK: u32 = 512;
pub const USBFS_DCTL_CGONAK_POS: u32 = 10;
pub const USBFS_DCTL_CGONAK: u32 = 1024;
pub const USBFS_DCTL_POPRGDNE_POS: u32 = 11;
pub const USBFS_DCTL_POPRGDNE: u32 = 2048;
pub const USBFS_DSTS_SUSPSTS_POS: u32 = 0;
pub const USBFS_DSTS_SUSPSTS: u32 = 1;
pub const USBFS_DSTS_ENUMSPD_POS: u32 = 1;
pub const USBFS_DSTS_ENUMSPD: u32 = 6;
pub const USBFS_DSTS_EERR_POS: u32 = 3;
pub const USBFS_DSTS_EERR: u32 = 8;
pub const USBFS_DSTS_FNSOF_POS: u32 = 8;
pub const USBFS_DSTS_FNSOF: u32 = 4194048;
pub const USBFS_DIEPMSK_XFRCM_POS: u32 = 0;
pub const USBFS_DIEPMSK_XFRCM: u32 = 1;
pub const USBFS_DIEPMSK_EPDM_POS: u32 = 1;
pub const USBFS_DIEPMSK_EPDM: u32 = 2;
pub const USBFS_DIEPMSK_TOM_POS: u32 = 3;
pub const USBFS_DIEPMSK_TOM: u32 = 8;
pub const USBFS_DIEPMSK_TTXFEMSK_POS: u32 = 4;
pub const USBFS_DIEPMSK_TTXFEMSK: u32 = 16;
pub const USBFS_DIEPMSK_INEPNMM_POS: u32 = 5;
pub const USBFS_DIEPMSK_INEPNMM: u32 = 32;
pub const USBFS_DIEPMSK_INEPNEM_POS: u32 = 6;
pub const USBFS_DIEPMSK_INEPNEM: u32 = 64;
pub const USBFS_DOEPMSK_XFRCM_POS: u32 = 0;
pub const USBFS_DOEPMSK_XFRCM: u32 = 1;
pub const USBFS_DOEPMSK_EPDM_POS: u32 = 1;
pub const USBFS_DOEPMSK_EPDM: u32 = 2;
pub const USBFS_DOEPMSK_STUPM_POS: u32 = 3;
pub const USBFS_DOEPMSK_STUPM: u32 = 8;
pub const USBFS_DOEPMSK_OTEPDM_POS: u32 = 4;
pub const USBFS_DOEPMSK_OTEPDM: u32 = 16;
pub const USBFS_DAINT_IEPINT_POS: u32 = 0;
pub const USBFS_DAINT_IEPINT: u32 = 63;
pub const USBFS_DAINT_OEPINT_POS: u32 = 16;
pub const USBFS_DAINT_OEPINT: u32 = 4128768;
pub const USBFS_DAINTMSK_IEPINTM_POS: u32 = 0;
pub const USBFS_DAINTMSK_IEPINTM: u32 = 63;
pub const USBFS_DAINTMSK_OEPINTM_POS: u32 = 16;
pub const USBFS_DAINTMSK_OEPINTM: u32 = 4128768;
pub const USBFS_DIEPEMPMSK_INEPTXFEM: u32 = 63;
pub const USBFS_DIEPCTL0_MPSIZ_POS: u32 = 0;
pub const USBFS_DIEPCTL0_MPSIZ: u32 = 3;
pub const USBFS_DIEPCTL0_USBAEP_POS: u32 = 15;
pub const USBFS_DIEPCTL0_USBAEP: u32 = 32768;
pub const USBFS_DIEPCTL0_NAKSTS_POS: u32 = 17;
pub const USBFS_DIEPCTL0_NAKSTS: u32 = 131072;
pub const USBFS_DIEPCTL0_EPTYP_POS: u32 = 18;
pub const USBFS_DIEPCTL0_EPTYP: u32 = 786432;
pub const USBFS_DIEPCTL0_STALL_POS: u32 = 21;
pub const USBFS_DIEPCTL0_STALL: u32 = 2097152;
pub const USBFS_DIEPCTL0_TXFNUM_POS: u32 = 22;
pub const USBFS_DIEPCTL0_TXFNUM: u32 = 62914560;
pub const USBFS_DIEPCTL0_CNAK_POS: u32 = 26;
pub const USBFS_DIEPCTL0_CNAK: u32 = 67108864;
pub const USBFS_DIEPCTL0_SNAK_POS: u32 = 27;
pub const USBFS_DIEPCTL0_SNAK: u32 = 134217728;
pub const USBFS_DIEPCTL0_EPDIS_POS: u32 = 30;
pub const USBFS_DIEPCTL0_EPDIS: u32 = 1073741824;
pub const USBFS_DIEPCTL0_EPENA_POS: u32 = 31;
pub const USBFS_DIEPCTL0_EPENA: u32 = 2147483648;
pub const USBFS_DIEPINT_XFRC_POS: u32 = 0;
pub const USBFS_DIEPINT_XFRC: u32 = 1;
pub const USBFS_DIEPINT_EPDISD_POS: u32 = 1;
pub const USBFS_DIEPINT_EPDISD: u32 = 2;
pub const USBFS_DIEPINT_TOC_POS: u32 = 3;
pub const USBFS_DIEPINT_TOC: u32 = 8;
pub const USBFS_DIEPINT_TTXFE_POS: u32 = 4;
pub const USBFS_DIEPINT_TTXFE: u32 = 16;
pub const USBFS_DIEPINT_INEPNE_POS: u32 = 6;
pub const USBFS_DIEPINT_INEPNE: u32 = 64;
pub const USBFS_DIEPINT_TXFE_POS: u32 = 7;
pub const USBFS_DIEPINT_TXFE: u32 = 128;
pub const USBFS_DIEPTSIZ0_XFRSIZ_POS: u32 = 0;
pub const USBFS_DIEPTSIZ0_XFRSIZ: u32 = 127;
pub const USBFS_DIEPTSIZ0_PKTCNT_POS: u32 = 19;
pub const USBFS_DIEPTSIZ0_PKTCNT: u32 = 1572864;
pub const USBFS_DIEPDMA: u32 = 4294967295;
pub const USBFS_DTXFSTS_INEPTFSAV: u32 = 65535;
pub const USBFS_DIEPCTL_MPSIZ_POS: u32 = 0;
pub const USBFS_DIEPCTL_MPSIZ: u32 = 2047;
pub const USBFS_DIEPCTL_USBAEP_POS: u32 = 15;
pub const USBFS_DIEPCTL_USBAEP: u32 = 32768;
pub const USBFS_DIEPCTL_EONUM_DPID_POS: u32 = 16;
pub const USBFS_DIEPCTL_EONUM_DPID: u32 = 65536;
pub const USBFS_DIEPCTL_NAKSTS_POS: u32 = 17;
pub const USBFS_DIEPCTL_NAKSTS: u32 = 131072;
pub const USBFS_DIEPCTL_EPTYP_POS: u32 = 18;
pub const USBFS_DIEPCTL_EPTYP: u32 = 786432;
pub const USBFS_DIEPCTL_STALL_POS: u32 = 21;
pub const USBFS_DIEPCTL_STALL: u32 = 2097152;
pub const USBFS_DIEPCTL_TXFNUM_POS: u32 = 22;
pub const USBFS_DIEPCTL_TXFNUM: u32 = 62914560;
pub const USBFS_DIEPCTL_CNAK_POS: u32 = 26;
pub const USBFS_DIEPCTL_CNAK: u32 = 67108864;
pub const USBFS_DIEPCTL_SNAK_POS: u32 = 27;
pub const USBFS_DIEPCTL_SNAK: u32 = 134217728;
pub const USBFS_DIEPCTL_SD0PID_SEVNFRM_POS: u32 = 28;
pub const USBFS_DIEPCTL_SD0PID_SEVNFRM: u32 = 268435456;
pub const USBFS_DIEPCTL_SODDFRM_POS: u32 = 29;
pub const USBFS_DIEPCTL_SODDFRM: u32 = 536870912;
pub const USBFS_DIEPCTL_EPDIS_POS: u32 = 30;
pub const USBFS_DIEPCTL_EPDIS: u32 = 1073741824;
pub const USBFS_DIEPCTL_EPENA_POS: u32 = 31;
pub const USBFS_DIEPCTL_EPENA: u32 = 2147483648;
pub const USBFS_DIEPTSIZ_XFRSIZ_POS: u32 = 0;
pub const USBFS_DIEPTSIZ_XFRSIZ: u32 = 524287;
pub const USBFS_DIEPTSIZ_PKTCNT_POS: u32 = 19;
pub const USBFS_DIEPTSIZ_PKTCNT: u32 = 536346624;
pub const USBFS_DOEPCTL0_MPSIZ_POS: u32 = 0;
pub const USBFS_DOEPCTL0_MPSIZ: u32 = 3;
pub const USBFS_DOEPCTL0_USBAEP_POS: u32 = 15;
pub const USBFS_DOEPCTL0_USBAEP: u32 = 32768;
pub const USBFS_DOEPCTL0_NAKSTS_POS: u32 = 17;
pub const USBFS_DOEPCTL0_NAKSTS: u32 = 131072;
pub const USBFS_DOEPCTL0_EPTYP_POS: u32 = 18;
pub const USBFS_DOEPCTL0_EPTYP: u32 = 786432;
pub const USBFS_DOEPCTL0_SNPM_POS: u32 = 20;
pub const USBFS_DOEPCTL0_SNPM: u32 = 1048576;
pub const USBFS_DOEPCTL0_STALL_POS: u32 = 21;
pub const USBFS_DOEPCTL0_STALL: u32 = 2097152;
pub const USBFS_DOEPCTL0_CNAK_POS: u32 = 26;
pub const USBFS_DOEPCTL0_CNAK: u32 = 67108864;
pub const USBFS_DOEPCTL0_SNAK_POS: u32 = 27;
pub const USBFS_DOEPCTL0_SNAK: u32 = 134217728;
pub const USBFS_DOEPCTL0_EPDIS_POS: u32 = 30;
pub const USBFS_DOEPCTL0_EPDIS: u32 = 1073741824;
pub const USBFS_DOEPCTL0_EPENA_POS: u32 = 31;
pub const USBFS_DOEPCTL0_EPENA: u32 = 2147483648;
pub const USBFS_DOEPINT_XFRC_POS: u32 = 0;
pub const USBFS_DOEPINT_XFRC: u32 = 1;
pub const USBFS_DOEPINT_EPDISD_POS: u32 = 1;
pub const USBFS_DOEPINT_EPDISD: u32 = 2;
pub const USBFS_DOEPINT_STUP_POS: u32 = 3;
pub const USBFS_DOEPINT_STUP: u32 = 8;
pub const USBFS_DOEPINT_OTEPDIS_POS: u32 = 4;
pub const USBFS_DOEPINT_OTEPDIS: u32 = 16;
pub const USBFS_DOEPINT_B2BSTUP_POS: u32 = 6;
pub const USBFS_DOEPINT_B2BSTUP: u32 = 64;
pub const USBFS_DOEPTSIZ0_XFRSIZ_POS: u32 = 0;
pub const USBFS_DOEPTSIZ0_XFRSIZ: u32 = 127;
pub const USBFS_DOEPTSIZ0_PKTCNT_POS: u32 = 19;
pub const USBFS_DOEPTSIZ0_PKTCNT: u32 = 524288;
pub const USBFS_DOEPTSIZ0_STUPCNT_POS: u32 = 29;
pub const USBFS_DOEPTSIZ0_STUPCNT: u32 = 1610612736;
pub const USBFS_DOEPDMA: u32 = 4294967295;
pub const USBFS_DOEPCTL_MPSIZ_POS: u32 = 0;
pub const USBFS_DOEPCTL_MPSIZ: u32 = 2047;
pub const USBFS_DOEPCTL_USBAEP_POS: u32 = 15;
pub const USBFS_DOEPCTL_USBAEP: u32 = 32768;
pub const USBFS_DOEPCTL_DPID_POS: u32 = 16;
pub const USBFS_DOEPCTL_DPID: u32 = 65536;
pub const USBFS_DOEPCTL_NAKSTS_POS: u32 = 17;
pub const USBFS_DOEPCTL_NAKSTS: u32 = 131072;
pub const USBFS_DOEPCTL_EPTYP_POS: u32 = 18;
pub const USBFS_DOEPCTL_EPTYP: u32 = 786432;
pub const USBFS_DOEPCTL_SNPM_POS: u32 = 20;
pub const USBFS_DOEPCTL_SNPM: u32 = 1048576;
pub const USBFS_DOEPCTL_STALL_POS: u32 = 21;
pub const USBFS_DOEPCTL_STALL: u32 = 2097152;
pub const USBFS_DOEPCTL_CNAK_POS: u32 = 26;
pub const USBFS_DOEPCTL_CNAK: u32 = 67108864;
pub const USBFS_DOEPCTL_SNAK_POS: u32 = 27;
pub const USBFS_DOEPCTL_SNAK: u32 = 134217728;
pub const USBFS_DOEPCTL_SD0PID_POS: u32 = 28;
pub const USBFS_DOEPCTL_SD0PID: u32 = 268435456;
pub const USBFS_DOEPCTL_SD1PID_POS: u32 = 29;
pub const USBFS_DOEPCTL_SD1PID: u32 = 536870912;
pub const USBFS_DOEPCTL_EPDIS_POS: u32 = 30;
pub const USBFS_DOEPCTL_EPDIS: u32 = 1073741824;
pub const USBFS_DOEPCTL_EPENA_POS: u32 = 31;
pub const USBFS_DOEPCTL_EPENA: u32 = 2147483648;
pub const USBFS_DOEPTSIZ_XFRSIZ_POS: u32 = 0;
pub const USBFS_DOEPTSIZ_XFRSIZ: u32 = 524287;
pub const USBFS_DOEPTSIZ_PKTCNT_POS: u32 = 19;
pub const USBFS_DOEPTSIZ_PKTCNT: u32 = 536346624;
pub const USBFS_GCCTL_STPPCLK_POS: u32 = 0;
pub const USBFS_GCCTL_STPPCLK: u32 = 1;
pub const USBFS_GCCTL_GATEHCLK_POS: u32 = 1;
pub const USBFS_GCCTL_GATEHCLK: u32 = 2;
pub const WDT_CR_PERI_POS: u32 = 0;
pub const WDT_CR_PERI: u32 = 3;
pub const WDT_CR_PERI_0: u32 = 1;
pub const WDT_CR_PERI_1: u32 = 2;
pub const WDT_CR_CKS_POS: u32 = 4;
pub const WDT_CR_CKS: u32 = 240;
pub const WDT_CR_WDPT_POS: u32 = 8;
pub const WDT_CR_WDPT: u32 = 3840;
pub const WDT_CR_SLPOFF_POS: u32 = 16;
pub const WDT_CR_SLPOFF: u32 = 65536;
pub const WDT_CR_ITS_POS: u32 = 31;
pub const WDT_CR_ITS: u32 = 2147483648;
pub const WDT_SR_CNT_POS: u32 = 0;
pub const WDT_SR_CNT: u32 = 65535;
pub const WDT_SR_UDF_POS: u32 = 16;
pub const WDT_SR_UDF: u32 = 65536;
pub const WDT_SR_REF_POS: u32 = 17;
pub const WDT_SR_REF: u32 = 131072;
pub const WDT_RR_RF: u32 = 65535;
pub const LL_ICG_ENABLE: u32 = 1;
pub const LL_UTILITY_ENABLE: u32 = 1;
pub const LL_PRINT_ENABLE: u32 = 0;
pub const LL_ADC_ENABLE: u32 = 1;
pub const LL_AES_ENABLE: u32 = 1;
pub const LL_AOS_ENABLE: u32 = 1;
pub const LL_CAN_ENABLE: u32 = 1;
pub const LL_CLK_ENABLE: u32 = 1;
pub const LL_CMP_ENABLE: u32 = 1;
pub const LL_CRC_ENABLE: u32 = 1;
pub const LL_DBGC_ENABLE: u32 = 1;
pub const LL_DCU_ENABLE: u32 = 1;
pub const LL_DMA_ENABLE: u32 = 1;
pub const LL_EFM_ENABLE: u32 = 1;
pub const LL_EMB_ENABLE: u32 = 1;
pub const LL_EVENT_PORT_ENABLE: u32 = 1;
pub const LL_FCG_ENABLE: u32 = 1;
pub const LL_FCM_ENABLE: u32 = 1;
pub const LL_GPIO_ENABLE: u32 = 1;
pub const LL_HASH_ENABLE: u32 = 1;
pub const LL_I2C_ENABLE: u32 = 1;
pub const LL_I2S_ENABLE: u32 = 1;
pub const LL_INTERRUPTS_ENABLE: u32 = 1;
pub const LL_INTERRUPTS_SHARE_ENABLE: u32 = 1;
pub const LL_KEYSCAN_ENABLE: u32 = 1;
pub const LL_MPU_ENABLE: u32 = 1;
pub const LL_OTS_ENABLE: u32 = 1;
pub const LL_PWC_ENABLE: u32 = 1;
pub const LL_QSPI_ENABLE: u32 = 1;
pub const LL_RMU_ENABLE: u32 = 1;
pub const LL_RTC_ENABLE: u32 = 1;
pub const LL_SDIOC_ENABLE: u32 = 1;
pub const LL_SPI_ENABLE: u32 = 1;
pub const LL_SRAM_ENABLE: u32 = 1;
pub const LL_SWDT_ENABLE: u32 = 1;
pub const LL_TMR0_ENABLE: u32 = 1;
pub const LL_TMR4_ENABLE: u32 = 1;
pub const LL_TMR6_ENABLE: u32 = 1;
pub const LL_TMRA_ENABLE: u32 = 1;
pub const LL_TRNG_ENABLE: u32 = 1;
pub const LL_USART_ENABLE: u32 = 1;
pub const LL_USB_ENABLE: u32 = 1;
pub const LL_WDT_ENABLE: u32 = 1;
pub const BSP_EV_HC32F460_LQFP100_V2: u32 = 4;
pub const BSP_EV_HC32F4XX: u32 = 0;
pub const BSP_24CXX_ENABLE: u32 = 0;
pub const BSP_W25QXX_ENABLE: u32 = 0;
pub const BSP_WM8731_ENABLE: u32 = 0;
pub const MRC_VALUE: u32 = 8000000;
pub const LRC_VALUE: u32 = 32768;
pub const SWDTLRC_VALUE: u32 = 10000;
pub const XTAL_VALUE: u32 = 8000000;
pub const XTAL32_VALUE: u32 = 32768;
pub const IRQn_Type_NMI_IRQn: IRQn_Type = -14;
pub const IRQn_Type_HardFault_IRQn: IRQn_Type = -13;
pub const IRQn_Type_MemManageFault_IRQn: IRQn_Type = -12;
pub const IRQn_Type_BusFault_IRQn: IRQn_Type = -11;
pub const IRQn_Type_UsageFault_IRQn: IRQn_Type = -10;
pub const IRQn_Type_SVC_IRQn: IRQn_Type = -5;
pub const IRQn_Type_DebugMonitor_IRQn: IRQn_Type = -4;
pub const IRQn_Type_PendSV_IRQn: IRQn_Type = -2;
pub const IRQn_Type_SysTick_IRQn: IRQn_Type = -1;
pub const IRQn_Type_INT000_IRQn: IRQn_Type = 0;
pub const IRQn_Type_INT001_IRQn: IRQn_Type = 1;
pub const IRQn_Type_INT002_IRQn: IRQn_Type = 2;
pub const IRQn_Type_INT003_IRQn: IRQn_Type = 3;
pub const IRQn_Type_INT004_IRQn: IRQn_Type = 4;
pub const IRQn_Type_INT005_IRQn: IRQn_Type = 5;
pub const IRQn_Type_INT006_IRQn: IRQn_Type = 6;
pub const IRQn_Type_INT007_IRQn: IRQn_Type = 7;
pub const IRQn_Type_INT008_IRQn: IRQn_Type = 8;
pub const IRQn_Type_INT009_IRQn: IRQn_Type = 9;
pub const IRQn_Type_INT010_IRQn: IRQn_Type = 10;
pub const IRQn_Type_INT011_IRQn: IRQn_Type = 11;
pub const IRQn_Type_INT012_IRQn: IRQn_Type = 12;
pub const IRQn_Type_INT013_IRQn: IRQn_Type = 13;
pub const IRQn_Type_INT014_IRQn: IRQn_Type = 14;
pub const IRQn_Type_INT015_IRQn: IRQn_Type = 15;
pub const IRQn_Type_INT016_IRQn: IRQn_Type = 16;
pub const IRQn_Type_INT017_IRQn: IRQn_Type = 17;
pub const IRQn_Type_INT018_IRQn: IRQn_Type = 18;
pub const IRQn_Type_INT019_IRQn: IRQn_Type = 19;
pub const IRQn_Type_INT020_IRQn: IRQn_Type = 20;
pub const IRQn_Type_INT021_IRQn: IRQn_Type = 21;
pub const IRQn_Type_INT022_IRQn: IRQn_Type = 22;
pub const IRQn_Type_INT023_IRQn: IRQn_Type = 23;
pub const IRQn_Type_INT024_IRQn: IRQn_Type = 24;
pub const IRQn_Type_INT025_IRQn: IRQn_Type = 25;
pub const IRQn_Type_INT026_IRQn: IRQn_Type = 26;
pub const IRQn_Type_INT027_IRQn: IRQn_Type = 27;
pub const IRQn_Type_INT028_IRQn: IRQn_Type = 28;
pub const IRQn_Type_INT029_IRQn: IRQn_Type = 29;
pub const IRQn_Type_INT030_IRQn: IRQn_Type = 30;
pub const IRQn_Type_INT031_IRQn: IRQn_Type = 31;
pub const IRQn_Type_INT032_IRQn: IRQn_Type = 32;
pub const IRQn_Type_INT033_IRQn: IRQn_Type = 33;
pub const IRQn_Type_INT034_IRQn: IRQn_Type = 34;
pub const IRQn_Type_INT035_IRQn: IRQn_Type = 35;
pub const IRQn_Type_INT036_IRQn: IRQn_Type = 36;
pub const IRQn_Type_INT037_IRQn: IRQn_Type = 37;
pub const IRQn_Type_INT038_IRQn: IRQn_Type = 38;
pub const IRQn_Type_INT039_IRQn: IRQn_Type = 39;
pub const IRQn_Type_INT040_IRQn: IRQn_Type = 40;
pub const IRQn_Type_INT041_IRQn: IRQn_Type = 41;
pub const IRQn_Type_INT042_IRQn: IRQn_Type = 42;
pub const IRQn_Type_INT043_IRQn: IRQn_Type = 43;
pub const IRQn_Type_INT044_IRQn: IRQn_Type = 44;
pub const IRQn_Type_INT045_IRQn: IRQn_Type = 45;
pub const IRQn_Type_INT046_IRQn: IRQn_Type = 46;
pub const IRQn_Type_INT047_IRQn: IRQn_Type = 47;
pub const IRQn_Type_INT048_IRQn: IRQn_Type = 48;
pub const IRQn_Type_INT049_IRQn: IRQn_Type = 49;
pub const IRQn_Type_INT050_IRQn: IRQn_Type = 50;
pub const IRQn_Type_INT051_IRQn: IRQn_Type = 51;
pub const IRQn_Type_INT052_IRQn: IRQn_Type = 52;
pub const IRQn_Type_INT053_IRQn: IRQn_Type = 53;
pub const IRQn_Type_INT054_IRQn: IRQn_Type = 54;
pub const IRQn_Type_INT055_IRQn: IRQn_Type = 55;
pub const IRQn_Type_INT056_IRQn: IRQn_Type = 56;
pub const IRQn_Type_INT057_IRQn: IRQn_Type = 57;
pub const IRQn_Type_INT058_IRQn: IRQn_Type = 58;
pub const IRQn_Type_INT059_IRQn: IRQn_Type = 59;
pub const IRQn_Type_INT060_IRQn: IRQn_Type = 60;
pub const IRQn_Type_INT061_IRQn: IRQn_Type = 61;
pub const IRQn_Type_INT062_IRQn: IRQn_Type = 62;
pub const IRQn_Type_INT063_IRQn: IRQn_Type = 63;
pub const IRQn_Type_INT064_IRQn: IRQn_Type = 64;
pub const IRQn_Type_INT065_IRQn: IRQn_Type = 65;
pub const IRQn_Type_INT066_IRQn: IRQn_Type = 66;
pub const IRQn_Type_INT067_IRQn: IRQn_Type = 67;
pub const IRQn_Type_INT068_IRQn: IRQn_Type = 68;
pub const IRQn_Type_INT069_IRQn: IRQn_Type = 69;
pub const IRQn_Type_INT070_IRQn: IRQn_Type = 70;
pub const IRQn_Type_INT071_IRQn: IRQn_Type = 71;
pub const IRQn_Type_INT072_IRQn: IRQn_Type = 72;
pub const IRQn_Type_INT073_IRQn: IRQn_Type = 73;
pub const IRQn_Type_INT074_IRQn: IRQn_Type = 74;
pub const IRQn_Type_INT075_IRQn: IRQn_Type = 75;
pub const IRQn_Type_INT076_IRQn: IRQn_Type = 76;
pub const IRQn_Type_INT077_IRQn: IRQn_Type = 77;
pub const IRQn_Type_INT078_IRQn: IRQn_Type = 78;
pub const IRQn_Type_INT079_IRQn: IRQn_Type = 79;
pub const IRQn_Type_INT080_IRQn: IRQn_Type = 80;
pub const IRQn_Type_INT081_IRQn: IRQn_Type = 81;
pub const IRQn_Type_INT082_IRQn: IRQn_Type = 82;
pub const IRQn_Type_INT083_IRQn: IRQn_Type = 83;
pub const IRQn_Type_INT084_IRQn: IRQn_Type = 84;
pub const IRQn_Type_INT085_IRQn: IRQn_Type = 85;
pub const IRQn_Type_INT086_IRQn: IRQn_Type = 86;
pub const IRQn_Type_INT087_IRQn: IRQn_Type = 87;
pub const IRQn_Type_INT088_IRQn: IRQn_Type = 88;
pub const IRQn_Type_INT089_IRQn: IRQn_Type = 89;
pub const IRQn_Type_INT090_IRQn: IRQn_Type = 90;
pub const IRQn_Type_INT091_IRQn: IRQn_Type = 91;
pub const IRQn_Type_INT092_IRQn: IRQn_Type = 92;
pub const IRQn_Type_INT093_IRQn: IRQn_Type = 93;
pub const IRQn_Type_INT094_IRQn: IRQn_Type = 94;
pub const IRQn_Type_INT095_IRQn: IRQn_Type = 95;
pub const IRQn_Type_INT096_IRQn: IRQn_Type = 96;
pub const IRQn_Type_INT097_IRQn: IRQn_Type = 97;
pub const IRQn_Type_INT098_IRQn: IRQn_Type = 98;
pub const IRQn_Type_INT099_IRQn: IRQn_Type = 99;
pub const IRQn_Type_INT100_IRQn: IRQn_Type = 100;
pub const IRQn_Type_INT101_IRQn: IRQn_Type = 101;
pub const IRQn_Type_INT102_IRQn: IRQn_Type = 102;
pub const IRQn_Type_INT103_IRQn: IRQn_Type = 103;
pub const IRQn_Type_INT104_IRQn: IRQn_Type = 104;
pub const IRQn_Type_INT105_IRQn: IRQn_Type = 105;
pub const IRQn_Type_INT106_IRQn: IRQn_Type = 106;
pub const IRQn_Type_INT107_IRQn: IRQn_Type = 107;
pub const IRQn_Type_INT108_IRQn: IRQn_Type = 108;
pub const IRQn_Type_INT109_IRQn: IRQn_Type = 109;
pub const IRQn_Type_INT110_IRQn: IRQn_Type = 110;
pub const IRQn_Type_INT111_IRQn: IRQn_Type = 111;
pub const IRQn_Type_INT112_IRQn: IRQn_Type = 112;
pub const IRQn_Type_INT113_IRQn: IRQn_Type = 113;
pub const IRQn_Type_INT114_IRQn: IRQn_Type = 114;
pub const IRQn_Type_INT115_IRQn: IRQn_Type = 115;
pub const IRQn_Type_INT116_IRQn: IRQn_Type = 116;
pub const IRQn_Type_INT117_IRQn: IRQn_Type = 117;
pub const IRQn_Type_INT118_IRQn: IRQn_Type = 118;
pub const IRQn_Type_INT119_IRQn: IRQn_Type = 119;
pub const IRQn_Type_INT120_IRQn: IRQn_Type = 120;
pub const IRQn_Type_INT121_IRQn: IRQn_Type = 121;
pub const IRQn_Type_INT122_IRQn: IRQn_Type = 122;
pub const IRQn_Type_INT123_IRQn: IRQn_Type = 123;
pub const IRQn_Type_INT124_IRQn: IRQn_Type = 124;
pub const IRQn_Type_INT125_IRQn: IRQn_Type = 125;
pub const IRQn_Type_INT126_IRQn: IRQn_Type = 126;
pub const IRQn_Type_INT127_IRQn: IRQn_Type = 127;
pub const IRQn_Type_INT128_IRQn: IRQn_Type = 128;
pub const IRQn_Type_INT129_IRQn: IRQn_Type = 129;
pub const IRQn_Type_INT130_IRQn: IRQn_Type = 130;
pub const IRQn_Type_INT131_IRQn: IRQn_Type = 131;
pub const IRQn_Type_INT132_IRQn: IRQn_Type = 132;
pub const IRQn_Type_INT133_IRQn: IRQn_Type = 133;
pub const IRQn_Type_INT134_IRQn: IRQn_Type = 134;
pub const IRQn_Type_INT135_IRQn: IRQn_Type = 135;
pub const IRQn_Type_INT136_IRQn: IRQn_Type = 136;
pub const IRQn_Type_INT137_IRQn: IRQn_Type = 137;
pub const IRQn_Type_INT138_IRQn: IRQn_Type = 138;
pub const IRQn_Type_INT139_IRQn: IRQn_Type = 139;
pub const IRQn_Type_INT140_IRQn: IRQn_Type = 140;
pub const IRQn_Type_INT141_IRQn: IRQn_Type = 141;
pub const IRQn_Type_INT142_IRQn: IRQn_Type = 142;
pub const IRQn_Type_INT143_IRQn: IRQn_Type = 143;
#[doc = " Interrupt Number Definition"]
pub type IRQn_Type = ::core::ffi::c_int;
pub const en_event_src_t_EVT_SRC_SWI_IRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_SWI_IRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_SWI_IRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_SWI_IRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_SWI_IRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_SWI_IRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_SWI_IRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_SWI_IRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_SWI_IRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_SWI_IRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_SWI_IRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_SWI_IRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_SWI_IRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_SWI_IRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_SWI_IRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_SWI_IRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_SWI_IRQ16: en_event_src_t = 16;
pub const en_event_src_t_EVT_SRC_SWI_IRQ17: en_event_src_t = 17;
pub const en_event_src_t_EVT_SRC_SWI_IRQ18: en_event_src_t = 18;
pub const en_event_src_t_EVT_SRC_SWI_IRQ19: en_event_src_t = 19;
pub const en_event_src_t_EVT_SRC_SWI_IRQ20: en_event_src_t = 20;
pub const en_event_src_t_EVT_SRC_SWI_IRQ21: en_event_src_t = 21;
pub const en_event_src_t_EVT_SRC_SWI_IRQ22: en_event_src_t = 22;
pub const en_event_src_t_EVT_SRC_SWI_IRQ23: en_event_src_t = 23;
pub const en_event_src_t_EVT_SRC_SWI_IRQ24: en_event_src_t = 24;
pub const en_event_src_t_EVT_SRC_SWI_IRQ25: en_event_src_t = 25;
pub const en_event_src_t_EVT_SRC_SWI_IRQ26: en_event_src_t = 26;
pub const en_event_src_t_EVT_SRC_SWI_IRQ27: en_event_src_t = 27;
pub const en_event_src_t_EVT_SRC_SWI_IRQ28: en_event_src_t = 28;
pub const en_event_src_t_EVT_SRC_SWI_IRQ29: en_event_src_t = 29;
pub const en_event_src_t_EVT_SRC_SWI_IRQ30: en_event_src_t = 30;
pub const en_event_src_t_EVT_SRC_SWI_IRQ31: en_event_src_t = 31;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_DMA1_TC0: en_event_src_t = 32;
pub const en_event_src_t_EVT_SRC_DMA1_TC1: en_event_src_t = 33;
pub const en_event_src_t_EVT_SRC_DMA1_TC2: en_event_src_t = 34;
pub const en_event_src_t_EVT_SRC_DMA1_TC3: en_event_src_t = 35;
pub const en_event_src_t_EVT_SRC_DMA2_TC0: en_event_src_t = 36;
pub const en_event_src_t_EVT_SRC_DMA2_TC1: en_event_src_t = 37;
pub const en_event_src_t_EVT_SRC_DMA2_TC2: en_event_src_t = 38;
pub const en_event_src_t_EVT_SRC_DMA2_TC3: en_event_src_t = 39;
pub const en_event_src_t_EVT_SRC_DMA1_BTC0: en_event_src_t = 40;
pub const en_event_src_t_EVT_SRC_DMA1_BTC1: en_event_src_t = 41;
pub const en_event_src_t_EVT_SRC_DMA1_BTC2: en_event_src_t = 42;
pub const en_event_src_t_EVT_SRC_DMA1_BTC3: en_event_src_t = 43;
pub const en_event_src_t_EVT_SRC_DMA2_BTC0: en_event_src_t = 44;
pub const en_event_src_t_EVT_SRC_DMA2_BTC1: en_event_src_t = 45;
pub const en_event_src_t_EVT_SRC_DMA2_BTC2: en_event_src_t = 46;
pub const en_event_src_t_EVT_SRC_DMA2_BTC3: en_event_src_t = 47;
pub const en_event_src_t_EVT_SRC_EFM_OPTEND: en_event_src_t = 52;
pub const en_event_src_t_EVT_SRC_USBFS_SOF: en_event_src_t = 53;
pub const en_event_src_t_EVT_SRC_DCU1: en_event_src_t = 55;
pub const en_event_src_t_EVT_SRC_DCU2: en_event_src_t = 56;
pub const en_event_src_t_EVT_SRC_DCU3: en_event_src_t = 57;
pub const en_event_src_t_EVT_SRC_DCU4: en_event_src_t = 58;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_A: en_event_src_t = 64;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_B: en_event_src_t = 65;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_A: en_event_src_t = 66;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_B: en_event_src_t = 67;
pub const en_event_src_t_EVT_SRC_RTC_ALM: en_event_src_t = 81;
pub const en_event_src_t_EVT_SRC_RTC_PRD: en_event_src_t = 82;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_A: en_event_src_t = 96;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_B: en_event_src_t = 97;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_C: en_event_src_t = 98;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_D: en_event_src_t = 99;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_E: en_event_src_t = 100;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_F: en_event_src_t = 101;
pub const en_event_src_t_EVT_SRC_TMR6_1_OVF: en_event_src_t = 102;
pub const en_event_src_t_EVT_SRC_TMR6_1_UDF: en_event_src_t = 103;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_A: en_event_src_t = 107;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_B: en_event_src_t = 108;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_A: en_event_src_t = 112;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_B: en_event_src_t = 113;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_C: en_event_src_t = 114;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_D: en_event_src_t = 115;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_E: en_event_src_t = 116;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_F: en_event_src_t = 117;
pub const en_event_src_t_EVT_SRC_TMR6_2_OVF: en_event_src_t = 118;
pub const en_event_src_t_EVT_SRC_TMR6_2_UDF: en_event_src_t = 119;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_A: en_event_src_t = 123;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_B: en_event_src_t = 124;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_A: en_event_src_t = 128;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_B: en_event_src_t = 129;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_C: en_event_src_t = 130;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_D: en_event_src_t = 131;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_E: en_event_src_t = 132;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_F: en_event_src_t = 133;
pub const en_event_src_t_EVT_SRC_TMR6_3_OVF: en_event_src_t = 134;
pub const en_event_src_t_EVT_SRC_TMR6_3_UDF: en_event_src_t = 135;
pub const en_event_src_t_EVT_SRC_TMR6_3_SCMP_A: en_event_src_t = 139;
pub const en_event_src_t_EVT_SRC_TMR6_3_SCMP_B: en_event_src_t = 140;
pub const en_event_src_t_EVT_SRC_TMRA_1_OVF: en_event_src_t = 256;
pub const en_event_src_t_EVT_SRC_TMRA_1_UDF: en_event_src_t = 257;
pub const en_event_src_t_EVT_SRC_TMRA_1_CMP: en_event_src_t = 258;
pub const en_event_src_t_EVT_SRC_TMRA_2_OVF: en_event_src_t = 259;
pub const en_event_src_t_EVT_SRC_TMRA_2_UDF: en_event_src_t = 260;
pub const en_event_src_t_EVT_SRC_TMRA_2_CMP: en_event_src_t = 261;
pub const en_event_src_t_EVT_SRC_TMRA_3_OVF: en_event_src_t = 262;
pub const en_event_src_t_EVT_SRC_TMRA_3_UDF: en_event_src_t = 263;
pub const en_event_src_t_EVT_SRC_TMRA_3_CMP: en_event_src_t = 264;
pub const en_event_src_t_EVT_SRC_TMRA_4_OVF: en_event_src_t = 265;
pub const en_event_src_t_EVT_SRC_TMRA_4_UDF: en_event_src_t = 266;
pub const en_event_src_t_EVT_SRC_TMRA_4_CMP: en_event_src_t = 267;
pub const en_event_src_t_EVT_SRC_TMRA_5_OVF: en_event_src_t = 268;
pub const en_event_src_t_EVT_SRC_TMRA_5_UDF: en_event_src_t = 269;
pub const en_event_src_t_EVT_SRC_TMRA_5_CMP: en_event_src_t = 270;
pub const en_event_src_t_EVT_SRC_TMRA_6_OVF: en_event_src_t = 272;
pub const en_event_src_t_EVT_SRC_TMRA_6_UDF: en_event_src_t = 273;
pub const en_event_src_t_EVT_SRC_TMRA_6_CMP: en_event_src_t = 274;
pub const en_event_src_t_EVT_SRC_USART1_EI: en_event_src_t = 278;
pub const en_event_src_t_EVT_SRC_USART1_RI: en_event_src_t = 279;
pub const en_event_src_t_EVT_SRC_USART1_TI: en_event_src_t = 280;
pub const en_event_src_t_EVT_SRC_USART1_TCI: en_event_src_t = 281;
pub const en_event_src_t_EVT_SRC_USART1_RTO: en_event_src_t = 282;
pub const en_event_src_t_EVT_SRC_USART2_EI: en_event_src_t = 283;
pub const en_event_src_t_EVT_SRC_USART2_RI: en_event_src_t = 284;
pub const en_event_src_t_EVT_SRC_USART2_TI: en_event_src_t = 285;
pub const en_event_src_t_EVT_SRC_USART2_TCI: en_event_src_t = 286;
pub const en_event_src_t_EVT_SRC_USART2_RTO: en_event_src_t = 287;
pub const en_event_src_t_EVT_SRC_USART3_EI: en_event_src_t = 288;
pub const en_event_src_t_EVT_SRC_USART3_RI: en_event_src_t = 289;
pub const en_event_src_t_EVT_SRC_USART3_TI: en_event_src_t = 290;
pub const en_event_src_t_EVT_SRC_USART3_TCI: en_event_src_t = 291;
pub const en_event_src_t_EVT_SRC_USART3_RTO: en_event_src_t = 292;
pub const en_event_src_t_EVT_SRC_USART4_EI: en_event_src_t = 293;
pub const en_event_src_t_EVT_SRC_USART4_RI: en_event_src_t = 294;
pub const en_event_src_t_EVT_SRC_USART4_TI: en_event_src_t = 295;
pub const en_event_src_t_EVT_SRC_USART4_TCI: en_event_src_t = 296;
pub const en_event_src_t_EVT_SRC_USART4_RTO: en_event_src_t = 297;
pub const en_event_src_t_EVT_SRC_SPI1_SPRI: en_event_src_t = 299;
pub const en_event_src_t_EVT_SRC_SPI1_SPTI: en_event_src_t = 300;
pub const en_event_src_t_EVT_SRC_SPI1_SPII: en_event_src_t = 301;
pub const en_event_src_t_EVT_SRC_SPI1_SPEI: en_event_src_t = 302;
pub const en_event_src_t_EVT_SRC_SPI1_SPTEND: en_event_src_t = 303;
pub const en_event_src_t_EVT_SRC_SPI2_SPRI: en_event_src_t = 304;
pub const en_event_src_t_EVT_SRC_SPI2_SPTI: en_event_src_t = 305;
pub const en_event_src_t_EVT_SRC_SPI2_SPII: en_event_src_t = 306;
pub const en_event_src_t_EVT_SRC_SPI2_SPEI: en_event_src_t = 307;
pub const en_event_src_t_EVT_SRC_SPI2_SPTEND: en_event_src_t = 308;
pub const en_event_src_t_EVT_SRC_SPI3_SPRI: en_event_src_t = 309;
pub const en_event_src_t_EVT_SRC_SPI3_SPTI: en_event_src_t = 310;
pub const en_event_src_t_EVT_SRC_SPI3_SPII: en_event_src_t = 311;
pub const en_event_src_t_EVT_SRC_SPI3_SPEI: en_event_src_t = 312;
pub const en_event_src_t_EVT_SRC_SPI3_SPTEND: en_event_src_t = 313;
pub const en_event_src_t_EVT_SRC_SPI4_SPRI: en_event_src_t = 314;
pub const en_event_src_t_EVT_SRC_SPI4_SPTI: en_event_src_t = 315;
pub const en_event_src_t_EVT_SRC_SPI4_SPII: en_event_src_t = 316;
pub const en_event_src_t_EVT_SRC_SPI4_SPEI: en_event_src_t = 317;
pub const en_event_src_t_EVT_SRC_SPI4_SPTEND: en_event_src_t = 318;
pub const en_event_src_t_EVT_SRC_AOS_STRG: en_event_src_t = 319;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP0: en_event_src_t = 368;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP1: en_event_src_t = 369;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP2: en_event_src_t = 370;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP3: en_event_src_t = 371;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP4: en_event_src_t = 372;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP5: en_event_src_t = 373;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP0: en_event_src_t = 374;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP1: en_event_src_t = 375;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP2: en_event_src_t = 376;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP3: en_event_src_t = 377;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP4: en_event_src_t = 378;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP5: en_event_src_t = 379;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP0: en_event_src_t = 384;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP1: en_event_src_t = 385;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP2: en_event_src_t = 386;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP3: en_event_src_t = 387;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP4: en_event_src_t = 388;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP5: en_event_src_t = 389;
pub const en_event_src_t_EVT_SRC_EVENT_PORT1: en_event_src_t = 394;
pub const en_event_src_t_EVT_SRC_EVENT_PORT2: en_event_src_t = 395;
pub const en_event_src_t_EVT_SRC_EVENT_PORT3: en_event_src_t = 396;
pub const en_event_src_t_EVT_SRC_EVENT_PORT4: en_event_src_t = 397;
pub const en_event_src_t_EVT_SRC_I2S1_TXIRQOUT: en_event_src_t = 400;
pub const en_event_src_t_EVT_SRC_I2S1_RXIRQOUT: en_event_src_t = 401;
pub const en_event_src_t_EVT_SRC_I2S2_TXIRQOUT: en_event_src_t = 403;
pub const en_event_src_t_EVT_SRC_I2S2_RXIRQOUT: en_event_src_t = 404;
pub const en_event_src_t_EVT_SRC_I2S3_TXIRQOUT: en_event_src_t = 406;
pub const en_event_src_t_EVT_SRC_I2S3_RXIRQOUT: en_event_src_t = 407;
pub const en_event_src_t_EVT_SRC_I2S4_TXIRQOUT: en_event_src_t = 409;
pub const en_event_src_t_EVT_SRC_I2S4_RXIRQOUT: en_event_src_t = 410;
pub const en_event_src_t_EVT_SRC_CMP1: en_event_src_t = 416;
pub const en_event_src_t_EVT_SRC_CMP2: en_event_src_t = 417;
pub const en_event_src_t_EVT_SRC_CMP3: en_event_src_t = 418;
pub const en_event_src_t_EVT_SRC_I2C1_RXI: en_event_src_t = 420;
pub const en_event_src_t_EVT_SRC_I2C1_TXI: en_event_src_t = 421;
pub const en_event_src_t_EVT_SRC_I2C1_TEI: en_event_src_t = 422;
pub const en_event_src_t_EVT_SRC_I2C1_EEI: en_event_src_t = 423;
pub const en_event_src_t_EVT_SRC_I2C2_RXI: en_event_src_t = 424;
pub const en_event_src_t_EVT_SRC_I2C2_TXI: en_event_src_t = 425;
pub const en_event_src_t_EVT_SRC_I2C2_TEI: en_event_src_t = 426;
pub const en_event_src_t_EVT_SRC_I2C2_EEI: en_event_src_t = 427;
pub const en_event_src_t_EVT_SRC_I2C3_RXI: en_event_src_t = 428;
pub const en_event_src_t_EVT_SRC_I2C3_TXI: en_event_src_t = 429;
pub const en_event_src_t_EVT_SRC_I2C3_TEI: en_event_src_t = 430;
pub const en_event_src_t_EVT_SRC_I2C3_EEI: en_event_src_t = 431;
pub const en_event_src_t_EVT_SRC_LVD1: en_event_src_t = 433;
pub const en_event_src_t_EVT_SRC_LVD2: en_event_src_t = 434;
pub const en_event_src_t_EVT_SRC_OTS: en_event_src_t = 435;
pub const en_event_src_t_EVT_SRC_WDT_REFUDF: en_event_src_t = 439;
pub const en_event_src_t_EVT_SRC_ADC1_EOCA: en_event_src_t = 448;
pub const en_event_src_t_EVT_SRC_ADC1_EOCB: en_event_src_t = 449;
pub const en_event_src_t_EVT_SRC_ADC1_CHCMP: en_event_src_t = 450;
pub const en_event_src_t_EVT_SRC_ADC1_SEQCMP: en_event_src_t = 451;
pub const en_event_src_t_EVT_SRC_ADC2_EOCA: en_event_src_t = 452;
pub const en_event_src_t_EVT_SRC_ADC2_EOCB: en_event_src_t = 453;
pub const en_event_src_t_EVT_SRC_ADC2_CHCMP: en_event_src_t = 454;
pub const en_event_src_t_EVT_SRC_ADC2_SEQCMP: en_event_src_t = 455;
pub const en_event_src_t_EVT_SRC_TRNG_END: en_event_src_t = 456;
pub const en_event_src_t_EVT_SRC_SDIOC1_DMAR: en_event_src_t = 480;
pub const en_event_src_t_EVT_SRC_SDIOC1_DMAW: en_event_src_t = 481;
pub const en_event_src_t_EVT_SRC_SDIOC2_DMAR: en_event_src_t = 483;
pub const en_event_src_t_EVT_SRC_SDIOC2_DMAW: en_event_src_t = 484;
pub const en_event_src_t_EVT_SRC_MAX: en_event_src_t = 511;
#[doc = " \\brief Event number enumeration"]
pub type en_event_src_t = ::core::ffi::c_uint;
pub const en_int_src_t_INT_SRC_SWI_IRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_SWI_IRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_SWI_IRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_SWI_IRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_SWI_IRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_SWI_IRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_SWI_IRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_SWI_IRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_SWI_IRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_SWI_IRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_SWI_IRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_SWI_IRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_SWI_IRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_SWI_IRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_SWI_IRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_SWI_IRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_SWI_IRQ16: en_int_src_t = 16;
pub const en_int_src_t_INT_SRC_SWI_IRQ17: en_int_src_t = 17;
pub const en_int_src_t_INT_SRC_SWI_IRQ18: en_int_src_t = 18;
pub const en_int_src_t_INT_SRC_SWI_IRQ19: en_int_src_t = 19;
pub const en_int_src_t_INT_SRC_SWI_IRQ20: en_int_src_t = 20;
pub const en_int_src_t_INT_SRC_SWI_IRQ21: en_int_src_t = 21;
pub const en_int_src_t_INT_SRC_SWI_IRQ22: en_int_src_t = 22;
pub const en_int_src_t_INT_SRC_SWI_IRQ23: en_int_src_t = 23;
pub const en_int_src_t_INT_SRC_SWI_IRQ24: en_int_src_t = 24;
pub const en_int_src_t_INT_SRC_SWI_IRQ25: en_int_src_t = 25;
pub const en_int_src_t_INT_SRC_SWI_IRQ26: en_int_src_t = 26;
pub const en_int_src_t_INT_SRC_SWI_IRQ27: en_int_src_t = 27;
pub const en_int_src_t_INT_SRC_SWI_IRQ28: en_int_src_t = 28;
pub const en_int_src_t_INT_SRC_SWI_IRQ29: en_int_src_t = 29;
pub const en_int_src_t_INT_SRC_SWI_IRQ30: en_int_src_t = 30;
pub const en_int_src_t_INT_SRC_SWI_IRQ31: en_int_src_t = 31;
pub const en_int_src_t_INT_SRC_PORT_EIRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_PORT_EIRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_PORT_EIRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_PORT_EIRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_PORT_EIRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_PORT_EIRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_PORT_EIRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_PORT_EIRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_PORT_EIRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_PORT_EIRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_PORT_EIRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_PORT_EIRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_PORT_EIRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_PORT_EIRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_PORT_EIRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_PORT_EIRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_DMA1_TC0: en_int_src_t = 32;
pub const en_int_src_t_INT_SRC_DMA1_TC1: en_int_src_t = 33;
pub const en_int_src_t_INT_SRC_DMA1_TC2: en_int_src_t = 34;
pub const en_int_src_t_INT_SRC_DMA1_TC3: en_int_src_t = 35;
pub const en_int_src_t_INT_SRC_DMA2_TC0: en_int_src_t = 36;
pub const en_int_src_t_INT_SRC_DMA2_TC1: en_int_src_t = 37;
pub const en_int_src_t_INT_SRC_DMA2_TC2: en_int_src_t = 38;
pub const en_int_src_t_INT_SRC_DMA2_TC3: en_int_src_t = 39;
pub const en_int_src_t_INT_SRC_DMA1_BTC0: en_int_src_t = 40;
pub const en_int_src_t_INT_SRC_DMA1_BTC1: en_int_src_t = 41;
pub const en_int_src_t_INT_SRC_DMA1_BTC2: en_int_src_t = 42;
pub const en_int_src_t_INT_SRC_DMA1_BTC3: en_int_src_t = 43;
pub const en_int_src_t_INT_SRC_DMA2_BTC0: en_int_src_t = 44;
pub const en_int_src_t_INT_SRC_DMA2_BTC1: en_int_src_t = 45;
pub const en_int_src_t_INT_SRC_DMA2_BTC2: en_int_src_t = 46;
pub const en_int_src_t_INT_SRC_DMA2_BTC3: en_int_src_t = 47;
pub const en_int_src_t_INT_SRC_DMA1_ERR: en_int_src_t = 48;
pub const en_int_src_t_INT_SRC_DMA2_ERR: en_int_src_t = 49;
pub const en_int_src_t_INT_SRC_EFM_PEERR: en_int_src_t = 50;
pub const en_int_src_t_INT_SRC_EFM_COLERR: en_int_src_t = 51;
pub const en_int_src_t_INT_SRC_EFM_OPTEND: en_int_src_t = 52;
pub const en_int_src_t_INT_SRC_QSPI_INTR: en_int_src_t = 54;
pub const en_int_src_t_INT_SRC_DCU1: en_int_src_t = 55;
pub const en_int_src_t_INT_SRC_DCU2: en_int_src_t = 56;
pub const en_int_src_t_INT_SRC_DCU3: en_int_src_t = 57;
pub const en_int_src_t_INT_SRC_DCU4: en_int_src_t = 58;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_A: en_int_src_t = 64;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_B: en_int_src_t = 65;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_A: en_int_src_t = 66;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_B: en_int_src_t = 67;
pub const en_int_src_t_INT_SRC_RTC_ALM: en_int_src_t = 81;
pub const en_int_src_t_INT_SRC_RTC_PRD: en_int_src_t = 82;
pub const en_int_src_t_INT_SRC_XTAL32_STOP: en_int_src_t = 84;
pub const en_int_src_t_INT_SRC_XTAL_STOP: en_int_src_t = 85;
pub const en_int_src_t_INT_SRC_WKTM_PRD: en_int_src_t = 86;
pub const en_int_src_t_INT_SRC_SWDT_REFUDF: en_int_src_t = 87;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_A: en_int_src_t = 96;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_B: en_int_src_t = 97;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_C: en_int_src_t = 98;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_D: en_int_src_t = 99;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_E: en_int_src_t = 100;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_F: en_int_src_t = 101;
pub const en_int_src_t_INT_SRC_TMR6_1_OVF: en_int_src_t = 102;
pub const en_int_src_t_INT_SRC_TMR6_1_UDF: en_int_src_t = 103;
pub const en_int_src_t_INT_SRC_TMR6_1_DTE: en_int_src_t = 104;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_A: en_int_src_t = 107;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_B: en_int_src_t = 108;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_A: en_int_src_t = 112;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_B: en_int_src_t = 113;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_C: en_int_src_t = 114;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_D: en_int_src_t = 115;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_E: en_int_src_t = 116;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_F: en_int_src_t = 117;
pub const en_int_src_t_INT_SRC_TMR6_2_OVF: en_int_src_t = 118;
pub const en_int_src_t_INT_SRC_TMR6_2_UDF: en_int_src_t = 119;
pub const en_int_src_t_INT_SRC_TMR6_2_DTE: en_int_src_t = 120;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_A: en_int_src_t = 123;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_B: en_int_src_t = 124;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_A: en_int_src_t = 128;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_B: en_int_src_t = 129;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_C: en_int_src_t = 130;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_D: en_int_src_t = 131;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_E: en_int_src_t = 132;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_F: en_int_src_t = 133;
pub const en_int_src_t_INT_SRC_TMR6_3_OVF: en_int_src_t = 134;
pub const en_int_src_t_INT_SRC_TMR6_3_UDF: en_int_src_t = 135;
pub const en_int_src_t_INT_SRC_TMR6_3_DTE: en_int_src_t = 136;
pub const en_int_src_t_INT_SRC_TMR6_3_SCMP_A: en_int_src_t = 139;
pub const en_int_src_t_INT_SRC_TMR6_3_SCMP_B: en_int_src_t = 140;
pub const en_int_src_t_INT_SRC_TMRA_1_OVF: en_int_src_t = 256;
pub const en_int_src_t_INT_SRC_TMRA_1_UDF: en_int_src_t = 257;
pub const en_int_src_t_INT_SRC_TMRA_1_CMP: en_int_src_t = 258;
pub const en_int_src_t_INT_SRC_TMRA_2_OVF: en_int_src_t = 259;
pub const en_int_src_t_INT_SRC_TMRA_2_UDF: en_int_src_t = 260;
pub const en_int_src_t_INT_SRC_TMRA_2_CMP: en_int_src_t = 261;
pub const en_int_src_t_INT_SRC_TMRA_3_OVF: en_int_src_t = 262;
pub const en_int_src_t_INT_SRC_TMRA_3_UDF: en_int_src_t = 263;
pub const en_int_src_t_INT_SRC_TMRA_3_CMP: en_int_src_t = 264;
pub const en_int_src_t_INT_SRC_TMRA_4_OVF: en_int_src_t = 265;
pub const en_int_src_t_INT_SRC_TMRA_4_UDF: en_int_src_t = 266;
pub const en_int_src_t_INT_SRC_TMRA_4_CMP: en_int_src_t = 267;
pub const en_int_src_t_INT_SRC_TMRA_5_OVF: en_int_src_t = 268;
pub const en_int_src_t_INT_SRC_TMRA_5_UDF: en_int_src_t = 269;
pub const en_int_src_t_INT_SRC_TMRA_5_CMP: en_int_src_t = 270;
pub const en_int_src_t_INT_SRC_TMRA_6_OVF: en_int_src_t = 272;
pub const en_int_src_t_INT_SRC_TMRA_6_UDF: en_int_src_t = 273;
pub const en_int_src_t_INT_SRC_TMRA_6_CMP: en_int_src_t = 274;
pub const en_int_src_t_INT_SRC_USBFS_GLB: en_int_src_t = 275;
pub const en_int_src_t_INT_SRC_USART1_EI: en_int_src_t = 278;
pub const en_int_src_t_INT_SRC_USART1_RI: en_int_src_t = 279;
pub const en_int_src_t_INT_SRC_USART1_TI: en_int_src_t = 280;
pub const en_int_src_t_INT_SRC_USART1_TCI: en_int_src_t = 281;
pub const en_int_src_t_INT_SRC_USART1_RTO: en_int_src_t = 282;
pub const en_int_src_t_INT_SRC_USART1_WUPI: en_int_src_t = 432;
pub const en_int_src_t_INT_SRC_USART2_EI: en_int_src_t = 283;
pub const en_int_src_t_INT_SRC_USART2_RI: en_int_src_t = 284;
pub const en_int_src_t_INT_SRC_USART2_TI: en_int_src_t = 285;
pub const en_int_src_t_INT_SRC_USART2_TCI: en_int_src_t = 286;
pub const en_int_src_t_INT_SRC_USART2_RTO: en_int_src_t = 287;
pub const en_int_src_t_INT_SRC_USART3_EI: en_int_src_t = 288;
pub const en_int_src_t_INT_SRC_USART3_RI: en_int_src_t = 289;
pub const en_int_src_t_INT_SRC_USART3_TI: en_int_src_t = 290;
pub const en_int_src_t_INT_SRC_USART3_TCI: en_int_src_t = 291;
pub const en_int_src_t_INT_SRC_USART3_RTO: en_int_src_t = 292;
pub const en_int_src_t_INT_SRC_USART4_EI: en_int_src_t = 293;
pub const en_int_src_t_INT_SRC_USART4_RI: en_int_src_t = 294;
pub const en_int_src_t_INT_SRC_USART4_TI: en_int_src_t = 295;
pub const en_int_src_t_INT_SRC_USART4_TCI: en_int_src_t = 296;
pub const en_int_src_t_INT_SRC_USART4_RTO: en_int_src_t = 297;
pub const en_int_src_t_INT_SRC_SPI1_SPRI: en_int_src_t = 299;
pub const en_int_src_t_INT_SRC_SPI1_SPTI: en_int_src_t = 300;
pub const en_int_src_t_INT_SRC_SPI1_SPII: en_int_src_t = 301;
pub const en_int_src_t_INT_SRC_SPI1_SPEI: en_int_src_t = 302;
pub const en_int_src_t_INT_SRC_SPI2_SPRI: en_int_src_t = 304;
pub const en_int_src_t_INT_SRC_SPI2_SPTI: en_int_src_t = 305;
pub const en_int_src_t_INT_SRC_SPI2_SPII: en_int_src_t = 306;
pub const en_int_src_t_INT_SRC_SPI2_SPEI: en_int_src_t = 307;
pub const en_int_src_t_INT_SRC_SPI3_SPRI: en_int_src_t = 309;
pub const en_int_src_t_INT_SRC_SPI3_SPTI: en_int_src_t = 310;
pub const en_int_src_t_INT_SRC_SPI3_SPII: en_int_src_t = 311;
pub const en_int_src_t_INT_SRC_SPI3_SPEI: en_int_src_t = 312;
pub const en_int_src_t_INT_SRC_SPI4_SPRI: en_int_src_t = 314;
pub const en_int_src_t_INT_SRC_SPI4_SPTI: en_int_src_t = 315;
pub const en_int_src_t_INT_SRC_SPI4_SPII: en_int_src_t = 316;
pub const en_int_src_t_INT_SRC_SPI4_SPEI: en_int_src_t = 317;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UH: en_int_src_t = 320;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UL: en_int_src_t = 321;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VH: en_int_src_t = 322;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VL: en_int_src_t = 323;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WH: en_int_src_t = 324;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WL: en_int_src_t = 325;
pub const en_int_src_t_INT_SRC_TMR4_1_OVF: en_int_src_t = 326;
pub const en_int_src_t_INT_SRC_TMR4_1_UDF: en_int_src_t = 327;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_U: en_int_src_t = 328;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_V: en_int_src_t = 329;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_W: en_int_src_t = 330;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UH: en_int_src_t = 336;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UL: en_int_src_t = 337;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VH: en_int_src_t = 338;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VL: en_int_src_t = 339;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WH: en_int_src_t = 340;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WL: en_int_src_t = 341;
pub const en_int_src_t_INT_SRC_TMR4_2_OVF: en_int_src_t = 342;
pub const en_int_src_t_INT_SRC_TMR4_2_UDF: en_int_src_t = 343;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_U: en_int_src_t = 344;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_V: en_int_src_t = 345;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_W: en_int_src_t = 346;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UH: en_int_src_t = 352;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UL: en_int_src_t = 353;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VH: en_int_src_t = 354;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VL: en_int_src_t = 355;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WH: en_int_src_t = 356;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WL: en_int_src_t = 357;
pub const en_int_src_t_INT_SRC_TMR4_3_OVF: en_int_src_t = 358;
pub const en_int_src_t_INT_SRC_TMR4_3_UDF: en_int_src_t = 359;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_U: en_int_src_t = 360;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_V: en_int_src_t = 361;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_W: en_int_src_t = 362;
pub const en_int_src_t_INT_SRC_EMB_GR0: en_int_src_t = 390;
pub const en_int_src_t_INT_SRC_EMB_GR1: en_int_src_t = 391;
pub const en_int_src_t_INT_SRC_EMB_GR2: en_int_src_t = 392;
pub const en_int_src_t_INT_SRC_EMB_GR3: en_int_src_t = 393;
pub const en_int_src_t_INT_SRC_EVENT_PORT1: en_int_src_t = 394;
pub const en_int_src_t_INT_SRC_EVENT_PORT2: en_int_src_t = 395;
pub const en_int_src_t_INT_SRC_EVENT_PORT3: en_int_src_t = 396;
pub const en_int_src_t_INT_SRC_EVENT_PORT4: en_int_src_t = 397;
pub const en_int_src_t_INT_SRC_I2S1_TXIRQOUT: en_int_src_t = 400;
pub const en_int_src_t_INT_SRC_I2S1_RXIRQOUT: en_int_src_t = 401;
pub const en_int_src_t_INT_SRC_I2S1_ERRIRQOUT: en_int_src_t = 402;
pub const en_int_src_t_INT_SRC_I2S2_TXIRQOUT: en_int_src_t = 403;
pub const en_int_src_t_INT_SRC_I2S2_RXIRQOUT: en_int_src_t = 404;
pub const en_int_src_t_INT_SRC_I2S2_ERRIRQOUT: en_int_src_t = 405;
pub const en_int_src_t_INT_SRC_I2S3_TXIRQOUT: en_int_src_t = 406;
pub const en_int_src_t_INT_SRC_I2S3_RXIRQOUT: en_int_src_t = 407;
pub const en_int_src_t_INT_SRC_I2S3_ERRIRQOUT: en_int_src_t = 408;
pub const en_int_src_t_INT_SRC_I2S4_TXIRQOUT: en_int_src_t = 409;
pub const en_int_src_t_INT_SRC_I2S4_RXIRQOUT: en_int_src_t = 410;
pub const en_int_src_t_INT_SRC_I2S4_ERRIRQOUT: en_int_src_t = 411;
pub const en_int_src_t_INT_SRC_CMP1: en_int_src_t = 416;
pub const en_int_src_t_INT_SRC_CMP2: en_int_src_t = 417;
pub const en_int_src_t_INT_SRC_CMP3: en_int_src_t = 418;
pub const en_int_src_t_INT_SRC_I2C1_RXI: en_int_src_t = 420;
pub const en_int_src_t_INT_SRC_I2C1_TXI: en_int_src_t = 421;
pub const en_int_src_t_INT_SRC_I2C1_TEI: en_int_src_t = 422;
pub const en_int_src_t_INT_SRC_I2C1_EEI: en_int_src_t = 423;
pub const en_int_src_t_INT_SRC_I2C2_RXI: en_int_src_t = 424;
pub const en_int_src_t_INT_SRC_I2C2_TXI: en_int_src_t = 425;
pub const en_int_src_t_INT_SRC_I2C2_TEI: en_int_src_t = 426;
pub const en_int_src_t_INT_SRC_I2C2_EEI: en_int_src_t = 427;
pub const en_int_src_t_INT_SRC_I2C3_RXI: en_int_src_t = 428;
pub const en_int_src_t_INT_SRC_I2C3_TXI: en_int_src_t = 429;
pub const en_int_src_t_INT_SRC_I2C3_TEI: en_int_src_t = 430;
pub const en_int_src_t_INT_SRC_I2C3_EEI: en_int_src_t = 431;
pub const en_int_src_t_INT_SRC_LVD1: en_int_src_t = 433;
pub const en_int_src_t_INT_SRC_LVD2: en_int_src_t = 434;
pub const en_int_src_t_INT_SRC_OTS: en_int_src_t = 435;
pub const en_int_src_t_INT_SRC_FCMFERRI: en_int_src_t = 436;
pub const en_int_src_t_INT_SRC_FCMMENDI: en_int_src_t = 437;
pub const en_int_src_t_INT_SRC_FCMCOVFI: en_int_src_t = 438;
pub const en_int_src_t_INT_SRC_WDT_REFUDF: en_int_src_t = 439;
pub const en_int_src_t_INT_SRC_ADC1_EOCA: en_int_src_t = 448;
pub const en_int_src_t_INT_SRC_ADC1_EOCB: en_int_src_t = 449;
pub const en_int_src_t_INT_SRC_ADC1_CHCMP: en_int_src_t = 450;
pub const en_int_src_t_INT_SRC_ADC1_SEQCMP: en_int_src_t = 451;
pub const en_int_src_t_INT_SRC_ADC2_EOCA: en_int_src_t = 452;
pub const en_int_src_t_INT_SRC_ADC2_EOCB: en_int_src_t = 453;
pub const en_int_src_t_INT_SRC_ADC2_CHCMP: en_int_src_t = 454;
pub const en_int_src_t_INT_SRC_ADC2_SEQCMP: en_int_src_t = 455;
pub const en_int_src_t_INT_SRC_TRNG_END: en_int_src_t = 456;
pub const en_int_src_t_INT_SRC_SDIOC1_SD: en_int_src_t = 482;
pub const en_int_src_t_INT_SRC_SDIOC2_SD: en_int_src_t = 485;
pub const en_int_src_t_INT_SRC_CAN_INT: en_int_src_t = 486;
pub const en_int_src_t_INT_SRC_MAX: en_int_src_t = 511;
#[doc = " \\brief Interrupt number enumeration"]
pub type en_int_src_t = ::core::ffi::c_uint;
#[doc = " @brief ADC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_ADC_TypeDef {
    pub STR: u8,
    pub RESERVED0: [u8; 1usize],
    pub CR0: u16,
    pub CR1: u16,
    pub RESERVED1: [u8; 4usize],
    pub TRGSR: u16,
    pub CHSELRA: u32,
    pub CHSELRB: u32,
    pub AVCHSELR: u32,
    pub RESERVED2: [u8; 8usize],
    pub SSTR0: u8,
    pub SSTR1: u8,
    pub SSTR2: u8,
    pub SSTR3: u8,
    pub SSTR4: u8,
    pub SSTR5: u8,
    pub SSTR6: u8,
    pub SSTR7: u8,
    pub SSTR8: u8,
    pub SSTR9: u8,
    pub SSTR10: u8,
    pub SSTR11: u8,
    pub SSTR12: u8,
    pub SSTR13: u8,
    pub SSTR14: u8,
    pub SSTR15: u8,
    pub SSTRL: u8,
    pub RESERVED3: [u8; 7usize],
    pub CHMUXR0: u16,
    pub CHMUXR1: u16,
    pub CHMUXR2: u16,
    pub CHMUXR3: u16,
    pub RESERVED4: [u8; 6usize],
    pub ISR: u8,
    pub ICR: u8,
    pub RESERVED5: [u8; 4usize],
    pub SYNCCR: u16,
    pub RESERVED6: [u8; 2usize],
    pub DR0: u16,
    pub DR1: u16,
    pub DR2: u16,
    pub DR3: u16,
    pub DR4: u16,
    pub DR5: u16,
    pub DR6: u16,
    pub DR7: u16,
    pub DR8: u16,
    pub DR9: u16,
    pub DR10: u16,
    pub DR11: u16,
    pub DR12: u16,
    pub DR13: u16,
    pub DR14: u16,
    pub DR15: u16,
    pub DR16: u16,
    pub RESERVED7: [u8; 46usize],
    pub AWDCR: u16,
    pub RESERVED8: [u8; 2usize],
    pub AWDDR0: u16,
    pub AWDDR1: u16,
    pub RESERVED9: [u8; 4usize],
    pub AWDCHSR: u32,
    pub AWDSR: u32,
    pub RESERVED10: [u8; 12usize],
    pub PGACR: u16,
    pub PGAGSR: u16,
    pub RESERVED11: [u8; 8usize],
    pub PGAINSR0: u16,
    pub PGAINSR1: u16,
}
#[doc = " @brief AES"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_AES_TypeDef {
    pub CR: u32,
    pub RESERVED0: [u8; 12usize],
    pub DR0: u32,
    pub DR1: u32,
    pub DR2: u32,
    pub DR3: u32,
    pub KR0: u32,
    pub KR1: u32,
    pub KR2: u32,
    pub KR3: u32,
}
#[doc = " @brief AOS"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_AOS_TypeDef {
    pub INTSFTTRG: u32,
    pub DCU_TRGSEL1: u32,
    pub DCU_TRGSEL2: u32,
    pub DCU_TRGSEL3: u32,
    pub DCU_TRGSEL4: u32,
    pub DMA1_TRGSEL0: u32,
    pub DMA1_TRGSEL1: u32,
    pub DMA1_TRGSEL2: u32,
    pub DMA1_TRGSEL3: u32,
    pub DMA2_TRGSEL0: u32,
    pub DMA2_TRGSEL1: u32,
    pub DMA2_TRGSEL2: u32,
    pub DMA2_TRGSEL3: u32,
    pub DMA_RC_TRGSEL: u32,
    pub TMR6_TRGSEL0: u32,
    pub TMR6_TRGSEL1: u32,
    pub TMR0_TRGSEL: u32,
    pub PEVNT_TRGSEL12: u32,
    pub PEVNT_TRGSEL34: u32,
    pub TMRA_TRGSEL0: u32,
    pub TMRA_TRGSEL1: u32,
    pub OTS_TRGSEL: u32,
    pub ADC1_TRGSEL0: u32,
    pub ADC1_TRGSEL1: u32,
    pub ADC2_TRGSEL0: u32,
    pub ADC2_TRGSEL1: u32,
    pub COMTRG1: u32,
    pub COMTRG2: u32,
    pub RESERVED0: [u8; 144usize],
    pub PEVNTDIRR1: u32,
    pub PEVNTIDR1: u32,
    pub PEVNTODR1: u32,
    pub PEVNTORR1: u32,
    pub PEVNTOSR1: u32,
    pub PEVNTRISR1: u32,
    pub PEVNTFALR1: u32,
    pub PEVNTDIRR2: u32,
    pub PEVNTIDR2: u32,
    pub PEVNTODR2: u32,
    pub PEVNTORR2: u32,
    pub PEVNTOSR2: u32,
    pub PEVNTRISR2: u32,
    pub PEVNTFALR2: u32,
    pub PEVNTDIRR3: u32,
    pub PEVNTIDR3: u32,
    pub PEVNTODR3: u32,
    pub PEVNTORR3: u32,
    pub PEVNTOSR3: u32,
    pub PEVNTRISR3: u32,
    pub PEVNTFALR3: u32,
    pub PEVNTDIRR4: u32,
    pub PEVNTIDR4: u32,
    pub PEVNTODR4: u32,
    pub PEVNTORR4: u32,
    pub PEVNTOSR4: u32,
    pub PEVNTRISR4: u32,
    pub PEVNTFALR4: u32,
    pub PEVNTNFCR: u32,
}
#[doc = " @brief CAN"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CAN_TypeDef {
    pub RBUF: u32,
    pub RESERVED0: [u8; 76usize],
    pub TBUF: u32,
    pub RESERVED1: [u8; 76usize],
    pub CFG_STAT: u8,
    pub TCMD: u8,
    pub TCTRL: u8,
    pub RCTRL: u8,
    pub RTIE: u8,
    pub RTIF: u8,
    pub ERRINT: u8,
    pub LIMIT: u8,
    pub SBT: u32,
    pub RESERVED2: [u8; 4usize],
    pub EALCAP: u8,
    pub RESERVED3: [u8; 1usize],
    pub RECNT: u8,
    pub TECNT: u8,
    pub ACFCTRL: u8,
    pub RESERVED4: [u8; 1usize],
    pub ACFEN: u8,
    pub RESERVED5: [u8; 1usize],
    pub ACF: u32,
    pub RESERVED6: [u8; 2usize],
    pub TBSLOT: u8,
    pub TTCFG: u8,
    pub REF_MSG: u32,
    pub TRG_CFG: u16,
    pub TT_TRIG: u16,
    pub TT_WTRIG: u16,
}
#[doc = " @brief CMP"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMP_TypeDef {
    pub CTRL: u16,
    pub VLTSEL: u16,
    pub OUTMON: u16,
    pub CVSSTB: u16,
    pub CVSPRD: u16,
}
#[doc = " @brief CMP_COMMON"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMP_COMMON_TypeDef {
    pub RESERVED0: [u8; 256usize],
    pub DADR1: u16,
    pub DADR2: u16,
    pub RESERVED1: [u8; 4usize],
    pub DACR: u16,
    pub RESERVED2: [u8; 2usize],
    pub RVADC: u16,
}
#[doc = " @brief CMU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMU_TypeDef {
    pub RESERVED0: [u8; 16usize],
    pub PERICKSEL: u16,
    pub I2SCKSEL: u16,
    pub RESERVED1: [u8; 12usize],
    pub SCFGR: u32,
    pub USBCKCFGR: u8,
    pub RESERVED2: [u8; 1usize],
    pub CKSWR: u8,
    pub RESERVED3: [u8; 3usize],
    pub PLLCR: u8,
    pub RESERVED4: [u8; 3usize],
    pub UPLLCR: u8,
    pub RESERVED5: [u8; 3usize],
    pub XTALCR: u8,
    pub RESERVED6: [u8; 3usize],
    pub HRCCR: u8,
    pub RESERVED7: [u8; 1usize],
    pub MRCCR: u8,
    pub RESERVED8: [u8; 3usize],
    pub OSCSTBSR: u8,
    pub MCO1CFGR: u8,
    pub MCO2CFGR: u8,
    pub TPIUCKCFGR: u8,
    pub XTALSTDCR: u8,
    pub XTALSTDSR: u8,
    pub RESERVED9: [u8; 31usize],
    pub MRCTRM: u8,
    pub HRCTRM: u8,
    pub RESERVED10: [u8; 63usize],
    pub XTALSTBCR: u8,
    pub RESERVED11: [u8; 93usize],
    pub PLLCFGR: u32,
    pub UPLLCFGR: u32,
    pub RESERVED12: [u8; 776usize],
    pub XTALCFGR: u8,
    pub RESERVED13: [u8; 15usize],
    pub XTAL32CR: u8,
    pub XTAL32CFGR: u8,
    pub RESERVED14: [u8; 3usize],
    pub XTAL32NFR: u8,
    pub RESERVED15: [u8; 1usize],
    pub LRCCR: u8,
    pub RESERVED16: [u8; 1usize],
    pub LRCTRM: u8,
}
#[doc = " @brief CRC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CRC_TypeDef {
    pub CR: u32,
    pub RESLT: u32,
    pub RESERVED0: [u8; 4usize],
    pub FLG: u32,
    pub RESERVED1: [u8; 112usize],
    pub DAT0: u32,
    pub DAT1: u32,
    pub DAT2: u32,
    pub DAT3: u32,
    pub DAT4: u32,
    pub DAT5: u32,
    pub DAT6: u32,
    pub DAT7: u32,
    pub DAT8: u32,
    pub DAT9: u32,
    pub DAT10: u32,
    pub DAT11: u32,
    pub DAT12: u32,
    pub DAT13: u32,
    pub DAT14: u32,
    pub DAT15: u32,
    pub DAT16: u32,
    pub DAT17: u32,
    pub DAT18: u32,
    pub DAT19: u32,
    pub DAT20: u32,
    pub DAT21: u32,
    pub DAT22: u32,
    pub DAT23: u32,
    pub DAT24: u32,
    pub DAT25: u32,
    pub DAT26: u32,
    pub DAT27: u32,
    pub DAT28: u32,
    pub DAT29: u32,
    pub DAT30: u32,
    pub DAT31: u32,
}
#[doc = " @brief DBGC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DBGC_TypeDef {
    pub RESERVED0: [u8; 28usize],
    pub MCUDBGSTAT: u32,
    pub MCUSTPCTL: u32,
    pub MCUTRACECTL: u32,
}
#[doc = " @brief DCU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DCU_TypeDef {
    pub CTL: u32,
    pub FLAG: u32,
    pub DATA0: u32,
    pub DATA1: u32,
    pub DATA2: u32,
    pub FLAGCLR: u32,
    pub INTEVTSEL: u32,
}
#[doc = " @brief DMA"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct CM_DMA_TypeDef {
    pub EN: u32,
    pub INTSTAT0: u32,
    pub INTSTAT1: u32,
    pub INTMASK0: u32,
    pub INTMASK1: u32,
    pub INTCLR0: u32,
    pub INTCLR1: u32,
    pub CHEN: u32,
    pub REQSTAT: u32,
    pub CHSTAT: u32,
    pub RESERVED0: [u8; 4usize],
    pub RCFGCTL: u32,
    pub SWREQ: u32,
    pub RESERVED1: [u8; 12usize],
    pub SAR0: u32,
    pub DAR0: u32,
    pub DTCTL0: u32,
    pub __bindgen_anon_1: CM_DMA_TypeDef__bindgen_ty_1,
    pub __bindgen_anon_2: CM_DMA_TypeDef__bindgen_ty_2,
    pub __bindgen_anon_3: CM_DMA_TypeDef__bindgen_ty_3,
    pub LLP0: u32,
    pub CHCTL0: u32,
    pub MONSAR0: u32,
    pub MONDAR0: u32,
    pub MONDTCTL0: u32,
    pub MONRPT0: u32,
    pub MONSNSEQCTL0: u32,
    pub MONDNSEQCTL0: u32,
    pub RESERVED2: [u8; 8usize],
    pub SAR1: u32,
    pub DAR1: u32,
    pub DTCTL1: u32,
    pub __bindgen_anon_4: CM_DMA_TypeDef__bindgen_ty_4,
    pub __bindgen_anon_5: CM_DMA_TypeDef__bindgen_ty_5,
    pub __bindgen_anon_6: CM_DMA_TypeDef__bindgen_ty_6,
    pub LLP1: u32,
    pub CHCTL1: u32,
    pub MONSAR1: u32,
    pub MONDAR1: u32,
    pub MONDTCTL1: u32,
    pub MONRPT1: u32,
    pub MONSNSEQCTL1: u32,
    pub MONDNSEQCTL1: u32,
    pub RESERVED3: [u8; 8usize],
    pub SAR2: u32,
    pub DAR2: u32,
    pub DTCTL2: u32,
    pub __bindgen_anon_7: CM_DMA_TypeDef__bindgen_ty_7,
    pub __bindgen_anon_8: CM_DMA_TypeDef__bindgen_ty_8,
    pub __bindgen_anon_9: CM_DMA_TypeDef__bindgen_ty_9,
    pub LLP2: u32,
    pub CHCTL2: u32,
    pub MONSAR2: u32,
    pub MONDAR2: u32,
    pub MONDTCTL2: u32,
    pub MONRPT2: u32,
    pub MONSNSEQCTL2: u32,
    pub MONDNSEQCTL2: u32,
    pub RESERVED4: [u8; 8usize],
    pub SAR3: u32,
    pub DAR3: u32,
    pub DTCTL3: u32,
    pub __bindgen_anon_10: CM_DMA_TypeDef__bindgen_ty_10,
    pub __bindgen_anon_11: CM_DMA_TypeDef__bindgen_ty_11,
    pub __bindgen_anon_12: CM_DMA_TypeDef__bindgen_ty_12,
    pub LLP3: u32,
    pub CHCTL3: u32,
    pub MONSAR3: u32,
    pub MONDAR3: u32,
    pub MONDTCTL3: u32,
    pub MONRPT3: u32,
    pub MONSNSEQCTL3: u32,
    pub MONDNSEQCTL3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_1 {
    pub RPT0: u32,
    pub RPTB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_2 {
    pub SNSEQCTL0: u32,
    pub SNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_3 {
    pub DNSEQCTL0: u32,
    pub DNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_4 {
    pub RPT1: u32,
    pub RPTB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_5 {
    pub SNSEQCTL1: u32,
    pub SNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_6 {
    pub DNSEQCTL1: u32,
    pub DNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_7 {
    pub RPT2: u32,
    pub RPTB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_8 {
    pub SNSEQCTL2: u32,
    pub SNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_9 {
    pub DNSEQCTL2: u32,
    pub DNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_10 {
    pub RPT3: u32,
    pub RPTB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_11 {
    pub SNSEQCTL3: u32,
    pub SNSEQCTLB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_12 {
    pub DNSEQCTL3: u32,
    pub DNSEQCTLB3: u32,
}
#[doc = " @brief EFM"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_EFM_TypeDef {
    pub FAPRT: u32,
    pub FSTP: u32,
    pub FRMC: u32,
    pub FWMC: u32,
    pub FSR: u32,
    pub FSCLR: u32,
    pub FITE: u32,
    pub FSWP: u32,
    pub FPMTSW: u32,
    pub FPMTEW: u32,
    pub RESERVED0: [u8; 40usize],
    pub UQID0: u32,
    pub UQID1: u32,
    pub UQID2: u32,
    pub RESERVED1: [u8; 164usize],
    pub MMF_REMPRT: u32,
    pub MMF_REMCR0: u32,
    pub MMF_REMCR1: u32,
}
#[doc = " @brief EMB"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_EMB_TypeDef {
    pub CTL: u32,
    pub PWMLV: u32,
    pub SOE: u32,
    pub STAT: u32,
    pub STATCLR: u32,
    pub INTEN: u32,
}
#[doc = " @brief FCM"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_FCM_TypeDef {
    pub LVR: u32,
    pub UVR: u32,
    pub CNTR: u32,
    pub STR: u32,
    pub MCCR: u32,
    pub RCCR: u32,
    pub RIER: u32,
    pub SR: u32,
    pub CLR: u32,
}
#[doc = " @brief GPIO"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_GPIO_TypeDef {
    pub PIDRA: u16,
    pub RESERVED0: [u8; 2usize],
    pub PODRA: u16,
    pub POERA: u16,
    pub POSRA: u16,
    pub PORRA: u16,
    pub POTRA: u16,
    pub RESERVED1: [u8; 2usize],
    pub PIDRB: u16,
    pub RESERVED2: [u8; 2usize],
    pub PODRB: u16,
    pub POERB: u16,
    pub POSRB: u16,
    pub PORRB: u16,
    pub POTRB: u16,
    pub RESERVED3: [u8; 2usize],
    pub PIDRC: u16,
    pub RESERVED4: [u8; 2usize],
    pub PODRC: u16,
    pub POERC: u16,
    pub POSRC: u16,
    pub PORRC: u16,
    pub POTRC: u16,
    pub RESERVED5: [u8; 2usize],
    pub PIDRD: u16,
    pub RESERVED6: [u8; 2usize],
    pub PODRD: u16,
    pub POERD: u16,
    pub POSRD: u16,
    pub PORRD: u16,
    pub POTRD: u16,
    pub RESERVED7: [u8; 2usize],
    pub PIDRE: u16,
    pub RESERVED8: [u8; 2usize],
    pub PODRE: u16,
    pub POERE: u16,
    pub POSRE: u16,
    pub PORRE: u16,
    pub POTRE: u16,
    pub RESERVED9: [u8; 2usize],
    pub PIDRH: u16,
    pub RESERVED10: [u8; 2usize],
    pub PODRH: u16,
    pub POERH: u16,
    pub POSRH: u16,
    pub PORRH: u16,
    pub POTRH: u16,
    pub RESERVED11: [u8; 918usize],
    pub PSPCR: u16,
    pub RESERVED12: [u8; 2usize],
    pub PCCR: u16,
    pub PINAER: u16,
    pub PWPR: u16,
    pub RESERVED13: [u8; 2usize],
    pub PCRA0: u16,
    pub PFSRA0: u16,
    pub PCRA1: u16,
    pub PFSRA1: u16,
    pub PCRA2: u16,
    pub PFSRA2: u16,
    pub PCRA3: u16,
    pub PFSRA3: u16,
    pub PCRA4: u16,
    pub PFSRA4: u16,
    pub PCRA5: u16,
    pub PFSRA5: u16,
    pub PCRA6: u16,
    pub PFSRA6: u16,
    pub PCRA7: u16,
    pub PFSRA7: u16,
    pub PCRA8: u16,
    pub PFSRA8: u16,
    pub PCRA9: u16,
    pub PFSRA9: u16,
    pub PCRA10: u16,
    pub PFSRA10: u16,
    pub PCRA11: u16,
    pub PFSRA11: u16,
    pub PCRA12: u16,
    pub PFSRA12: u16,
    pub PCRA13: u16,
    pub PFSRA13: u16,
    pub PCRA14: u16,
    pub PFSRA14: u16,
    pub PCRA15: u16,
    pub PFSRA15: u16,
    pub PCRB0: u16,
    pub PFSRB0: u16,
    pub PCRB1: u16,
    pub PFSRB1: u16,
    pub PCRB2: u16,
    pub PFSRB2: u16,
    pub PCRB3: u16,
    pub PFSRB3: u16,
    pub PCRB4: u16,
    pub PFSRB4: u16,
    pub PCRB5: u16,
    pub PFSRB5: u16,
    pub PCRB6: u16,
    pub PFSRB6: u16,
    pub PCRB7: u16,
    pub PFSRB7: u16,
    pub PCRB8: u16,
    pub PFSRB8: u16,
    pub PCRB9: u16,
    pub PFSRB9: u16,
    pub PCRB10: u16,
    pub PFSRB10: u16,
    pub PCRB11: u16,
    pub PFSRB11: u16,
    pub PCRB12: u16,
    pub PFSRB12: u16,
    pub PCRB13: u16,
    pub PFSRB13: u16,
    pub PCRB14: u16,
    pub PFSRB14: u16,
    pub PCRB15: u16,
    pub PFSRB15: u16,
    pub PCRC0: u16,
    pub PFSRC0: u16,
    pub PCRC1: u16,
    pub PFSRC1: u16,
    pub PCRC2: u16,
    pub PFSRC2: u16,
    pub PCRC3: u16,
    pub PFSRC3: u16,
    pub PCRC4: u16,
    pub PFSRC4: u16,
    pub PCRC5: u16,
    pub PFSRC5: u16,
    pub PCRC6: u16,
    pub PFSRC6: u16,
    pub PCRC7: u16,
    pub PFSRC7: u16,
    pub PCRC8: u16,
    pub PFSRC8: u16,
    pub PCRC9: u16,
    pub PFSRC9: u16,
    pub PCRC10: u16,
    pub PFSRC10: u16,
    pub PCRC11: u16,
    pub PFSRC11: u16,
    pub PCRC12: u16,
    pub PFSRC12: u16,
    pub PCRC13: u16,
    pub PFSRC13: u16,
    pub PCRC14: u16,
    pub PFSRC14: u16,
    pub PCRC15: u16,
    pub PFSRC15: u16,
    pub PCRD0: u16,
    pub PFSRD0: u16,
    pub PCRD1: u16,
    pub PFSRD1: u16,
    pub PCRD2: u16,
    pub PFSRD2: u16,
    pub PCRD3: u16,
    pub PFSRD3: u16,
    pub PCRD4: u16,
    pub PFSRD4: u16,
    pub PCRD5: u16,
    pub PFSRD5: u16,
    pub PCRD6: u16,
    pub PFSRD6: u16,
    pub PCRD7: u16,
    pub PFSRD7: u16,
    pub PCRD8: u16,
    pub PFSRD8: u16,
    pub PCRD9: u16,
    pub PFSRD9: u16,
    pub PCRD10: u16,
    pub PFSRD10: u16,
    pub PCRD11: u16,
    pub PFSRD11: u16,
    pub PCRD12: u16,
    pub PFSRD12: u16,
    pub PCRD13: u16,
    pub PFSRD13: u16,
    pub PCRD14: u16,
    pub PFSRD14: u16,
    pub PCRD15: u16,
    pub PFSRD15: u16,
    pub PCRE0: u16,
    pub PFSRE0: u16,
    pub PCRE1: u16,
    pub PFSRE1: u16,
    pub PCRE2: u16,
    pub PFSRE2: u16,
    pub PCRE3: u16,
    pub PFSRE3: u16,
    pub PCRE4: u16,
    pub PFSRE4: u16,
    pub PCRE5: u16,
    pub PFSRE5: u16,
    pub PCRE6: u16,
    pub PFSRE6: u16,
    pub PCRE7: u16,
    pub PFSRE7: u16,
    pub PCRE8: u16,
    pub PFSRE8: u16,
    pub PCRE9: u16,
    pub PFSRE9: u16,
    pub PCRE10: u16,
    pub PFSRE10: u16,
    pub PCRE11: u16,
    pub PFSRE11: u16,
    pub PCRE12: u16,
    pub PFSRE12: u16,
    pub PCRE13: u16,
    pub PFSRE13: u16,
    pub PCRE14: u16,
    pub PFSRE14: u16,
    pub PCRE15: u16,
    pub PFSRE15: u16,
    pub PCRH0: u16,
    pub PFSRH0: u16,
    pub PCRH1: u16,
    pub PFSRH1: u16,
    pub PCRH2: u16,
    pub PFSRH2: u16,
}
#[doc = " @brief HASH"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_HASH_TypeDef {
    pub CR: u32,
    pub RESERVED0: [u8; 12usize],
    pub HR7: u32,
    pub HR6: u32,
    pub HR5: u32,
    pub HR4: u32,
    pub HR3: u32,
    pub HR2: u32,
    pub HR1: u32,
    pub HR0: u32,
    pub RESERVED1: [u8; 16usize],
    pub DR15: u32,
    pub DR14: u32,
    pub DR13: u32,
    pub DR12: u32,
    pub DR11: u32,
    pub DR10: u32,
    pub DR9: u32,
    pub DR8: u32,
    pub DR7: u32,
    pub DR6: u32,
    pub DR5: u32,
    pub DR4: u32,
    pub DR3: u32,
    pub DR2: u32,
    pub DR1: u32,
    pub DR0: u32,
}
#[doc = " @brief I2C"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2C_TypeDef {
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub CR4: u32,
    pub SLR0: u32,
    pub SLR1: u32,
    pub SLTR: u32,
    pub SR: u32,
    pub CLR: u32,
    pub DTR: u8,
    pub RESERVED0: [u8; 3usize],
    pub DRR: u8,
    pub RESERVED1: [u8; 3usize],
    pub CCR: u32,
    pub FLTR: u32,
}
#[doc = " @brief I2S"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2S_TypeDef {
    pub CTRL: u32,
    pub SR: u32,
    pub ER: u32,
    pub CFGR: u32,
    pub TXBUF: u32,
    pub RXBUF: u32,
    pub PR: u32,
}
#[doc = " @brief ICG"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_ICG_TypeDef {
    pub ICG0: u32,
    pub ICG1: u32,
    pub ICG2: u32,
    pub ICG3: u32,
    pub ICG4: u32,
    pub ICG5: u32,
    pub ICG6: u32,
    pub ICG7: u32,
}
#[doc = " @brief INTC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_INTC_TypeDef {
    pub NMICR: u32,
    pub NMIENR: u32,
    pub NMIFR: u32,
    pub NMICFR: u32,
    pub EIRQCR0: u32,
    pub EIRQCR1: u32,
    pub EIRQCR2: u32,
    pub EIRQCR3: u32,
    pub EIRQCR4: u32,
    pub EIRQCR5: u32,
    pub EIRQCR6: u32,
    pub EIRQCR7: u32,
    pub EIRQCR8: u32,
    pub EIRQCR9: u32,
    pub EIRQCR10: u32,
    pub EIRQCR11: u32,
    pub EIRQCR12: u32,
    pub EIRQCR13: u32,
    pub EIRQCR14: u32,
    pub EIRQCR15: u32,
    pub WUPEN: u32,
    pub EIFR: u32,
    pub EIFCR: u32,
    pub SEL0: u32,
    pub SEL1: u32,
    pub SEL2: u32,
    pub SEL3: u32,
    pub SEL4: u32,
    pub SEL5: u32,
    pub SEL6: u32,
    pub SEL7: u32,
    pub SEL8: u32,
    pub SEL9: u32,
    pub SEL10: u32,
    pub SEL11: u32,
    pub SEL12: u32,
    pub SEL13: u32,
    pub SEL14: u32,
    pub SEL15: u32,
    pub SEL16: u32,
    pub SEL17: u32,
    pub SEL18: u32,
    pub SEL19: u32,
    pub SEL20: u32,
    pub SEL21: u32,
    pub SEL22: u32,
    pub SEL23: u32,
    pub SEL24: u32,
    pub SEL25: u32,
    pub SEL26: u32,
    pub SEL27: u32,
    pub SEL28: u32,
    pub SEL29: u32,
    pub SEL30: u32,
    pub SEL31: u32,
    pub SEL32: u32,
    pub SEL33: u32,
    pub SEL34: u32,
    pub SEL35: u32,
    pub SEL36: u32,
    pub SEL37: u32,
    pub SEL38: u32,
    pub SEL39: u32,
    pub SEL40: u32,
    pub SEL41: u32,
    pub SEL42: u32,
    pub SEL43: u32,
    pub SEL44: u32,
    pub SEL45: u32,
    pub SEL46: u32,
    pub SEL47: u32,
    pub SEL48: u32,
    pub SEL49: u32,
    pub SEL50: u32,
    pub SEL51: u32,
    pub SEL52: u32,
    pub SEL53: u32,
    pub SEL54: u32,
    pub SEL55: u32,
    pub SEL56: u32,
    pub SEL57: u32,
    pub SEL58: u32,
    pub SEL59: u32,
    pub SEL60: u32,
    pub SEL61: u32,
    pub SEL62: u32,
    pub SEL63: u32,
    pub SEL64: u32,
    pub SEL65: u32,
    pub SEL66: u32,
    pub SEL67: u32,
    pub SEL68: u32,
    pub SEL69: u32,
    pub SEL70: u32,
    pub SEL71: u32,
    pub SEL72: u32,
    pub SEL73: u32,
    pub SEL74: u32,
    pub SEL75: u32,
    pub SEL76: u32,
    pub SEL77: u32,
    pub SEL78: u32,
    pub SEL79: u32,
    pub SEL80: u32,
    pub SEL81: u32,
    pub SEL82: u32,
    pub SEL83: u32,
    pub SEL84: u32,
    pub SEL85: u32,
    pub SEL86: u32,
    pub SEL87: u32,
    pub SEL88: u32,
    pub SEL89: u32,
    pub SEL90: u32,
    pub SEL91: u32,
    pub SEL92: u32,
    pub SEL93: u32,
    pub SEL94: u32,
    pub SEL95: u32,
    pub SEL96: u32,
    pub SEL97: u32,
    pub SEL98: u32,
    pub SEL99: u32,
    pub SEL100: u32,
    pub SEL101: u32,
    pub SEL102: u32,
    pub SEL103: u32,
    pub SEL104: u32,
    pub SEL105: u32,
    pub SEL106: u32,
    pub SEL107: u32,
    pub SEL108: u32,
    pub SEL109: u32,
    pub SEL110: u32,
    pub SEL111: u32,
    pub SEL112: u32,
    pub SEL113: u32,
    pub SEL114: u32,
    pub SEL115: u32,
    pub SEL116: u32,
    pub SEL117: u32,
    pub SEL118: u32,
    pub SEL119: u32,
    pub SEL120: u32,
    pub SEL121: u32,
    pub SEL122: u32,
    pub SEL123: u32,
    pub SEL124: u32,
    pub SEL125: u32,
    pub SEL126: u32,
    pub SEL127: u32,
    pub VSSEL128: u32,
    pub VSSEL129: u32,
    pub VSSEL130: u32,
    pub VSSEL131: u32,
    pub VSSEL132: u32,
    pub VSSEL133: u32,
    pub VSSEL134: u32,
    pub VSSEL135: u32,
    pub VSSEL136: u32,
    pub VSSEL137: u32,
    pub VSSEL138: u32,
    pub VSSEL139: u32,
    pub VSSEL140: u32,
    pub VSSEL141: u32,
    pub VSSEL142: u32,
    pub VSSEL143: u32,
    pub SWIER: u32,
    pub EVTER: u32,
    pub IER: u32,
}
#[doc = " @brief KEYSCAN"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_KEYSCAN_TypeDef {
    pub SCR: u32,
    pub SER: u32,
    pub SSR: u32,
}
#[doc = " @brief MPU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_MPU_TypeDef {
    pub RGD0: u32,
    pub RGD1: u32,
    pub RGD2: u32,
    pub RGD3: u32,
    pub RGD4: u32,
    pub RGD5: u32,
    pub RGD6: u32,
    pub RGD7: u32,
    pub RGD8: u32,
    pub RGD9: u32,
    pub RGD10: u32,
    pub RGD11: u32,
    pub RGD12: u32,
    pub RGD13: u32,
    pub RGD14: u32,
    pub RGD15: u32,
    pub RGCR0: u32,
    pub RGCR1: u32,
    pub RGCR2: u32,
    pub RGCR3: u32,
    pub RGCR4: u32,
    pub RGCR5: u32,
    pub RGCR6: u32,
    pub RGCR7: u32,
    pub RGCR8: u32,
    pub RGCR9: u32,
    pub RGCR10: u32,
    pub RGCR11: u32,
    pub RGCR12: u32,
    pub RGCR13: u32,
    pub RGCR14: u32,
    pub RGCR15: u32,
    pub CR: u32,
    pub SR: u32,
    pub ECLR: u32,
    pub WP: u32,
    pub RESERVED0: [u8; 16268usize],
    pub IPPR: u32,
}
#[doc = " @brief OTS"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_OTS_TypeDef {
    pub CTL: u16,
    pub DR1: u16,
    pub DR2: u16,
    pub ECR: u16,
}
#[doc = " @brief PERIC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_PERIC_TypeDef {
    pub USBFS_SYCTLREG: u32,
    pub SDIOC_SYCTLREG: u32,
}
#[doc = " @brief PWC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_PWC_TypeDef {
    pub FCG0: u32,
    pub FCG1: u32,
    pub FCG2: u32,
    pub FCG3: u32,
    pub FCG0PC: u32,
    pub RESERVED0: [u8; 17388usize],
    pub WKTCR: u16,
    pub RESERVED1: [u8; 31754usize],
    pub STPMCR: u16,
    pub RESERVED2: [u8; 6usize],
    pub RAMPC0: u32,
    pub RAMOPM: u16,
    pub RESERVED3: [u8; 198usize],
    pub PVDICR: u8,
    pub PVDDSR: u8,
    pub RESERVED4: [u8; 796usize],
    pub FPRC: u16,
    pub PWRC0: u8,
    pub PWRC1: u8,
    pub PWRC2: u8,
    pub PWRC3: u8,
    pub PDWKE0: u8,
    pub PDWKE1: u8,
    pub PDWKE2: u8,
    pub PDWKES: u8,
    pub PDWKF0: u8,
    pub PDWKF1: u8,
    pub PWCMR: u8,
    pub RESERVED5: [u8; 4usize],
    pub MDSWCR: u8,
    pub RESERVED6: [u8; 2usize],
    pub PVDCR0: u8,
    pub PVDCR1: u8,
    pub PVDFCR: u8,
    pub PVDLCR: u8,
    pub RESERVED7: [u8; 21usize],
    pub XTAL32CS: u8,
}
#[doc = " @brief QSPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_QSPI_TypeDef {
    pub CR: u32,
    pub CSCR: u32,
    pub FCR: u32,
    pub SR: u32,
    pub DCOM: u32,
    pub CCMD: u32,
    pub XCMD: u32,
    pub RESERVED0: [u8; 8usize],
    pub CLR: u32,
    pub RESERVED1: [u8; 2012usize],
    pub EXAR: u32,
}
#[doc = " @brief RMU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_RMU_TypeDef {
    pub RSTF0: u16,
}
#[doc = " @brief RTC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_RTC_TypeDef {
    pub CR0: u8,
    pub RESERVED0: [u8; 3usize],
    pub CR1: u8,
    pub RESERVED1: [u8; 3usize],
    pub CR2: u8,
    pub RESERVED2: [u8; 3usize],
    pub CR3: u8,
    pub RESERVED3: [u8; 3usize],
    pub SEC: u8,
    pub RESERVED4: [u8; 3usize],
    pub MIN: u8,
    pub RESERVED5: [u8; 3usize],
    pub HOUR: u8,
    pub RESERVED6: [u8; 3usize],
    pub WEEK: u8,
    pub RESERVED7: [u8; 3usize],
    pub DAY: u8,
    pub RESERVED8: [u8; 3usize],
    pub MON: u8,
    pub RESERVED9: [u8; 3usize],
    pub YEAR: u8,
    pub RESERVED10: [u8; 3usize],
    pub ALMMIN: u8,
    pub RESERVED11: [u8; 3usize],
    pub ALMHOUR: u8,
    pub RESERVED12: [u8; 3usize],
    pub ALMWEEK: u8,
    pub RESERVED13: [u8; 3usize],
    pub ERRCRH: u8,
    pub RESERVED14: [u8; 3usize],
    pub ERRCRL: u8,
}
#[doc = " @brief SDIOC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SDIOC_TypeDef {
    pub RESERVED0: [u8; 4usize],
    pub BLKSIZE: u16,
    pub BLKCNT: u16,
    pub ARG0: u16,
    pub ARG1: u16,
    pub TRANSMODE: u16,
    pub CMD: u16,
    pub RESP0: u16,
    pub RESP1: u16,
    pub RESP2: u16,
    pub RESP3: u16,
    pub RESP4: u16,
    pub RESP5: u16,
    pub RESP6: u16,
    pub RESP7: u16,
    pub BUF0: u16,
    pub BUF1: u16,
    pub PSTAT: u32,
    pub HOSTCON: u8,
    pub PWRCON: u8,
    pub BLKGPCON: u8,
    pub RESERVED1: [u8; 1usize],
    pub CLKCON: u16,
    pub TOUTCON: u8,
    pub SFTRST: u8,
    pub NORINTST: u16,
    pub ERRINTST: u16,
    pub NORINTSTEN: u16,
    pub ERRINTSTEN: u16,
    pub NORINTSGEN: u16,
    pub ERRINTSGEN: u16,
    pub ATCERRST: u16,
    pub RESERVED2: [u8; 18usize],
    pub FEA: u16,
    pub FEE: u16,
}
#[doc = " @brief SPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SPI_TypeDef {
    pub DR: u32,
    pub CR1: u32,
    pub RESERVED0: [u8; 4usize],
    pub CFG1: u32,
    pub RESERVED1: [u8; 4usize],
    pub SR: u32,
    pub CFG2: u32,
}
#[doc = " @brief SRAMC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SRAMC_TypeDef {
    pub WTCR: u32,
    pub WTPR: u32,
    pub CKCR: u32,
    pub CKPR: u32,
    pub CKSR: u32,
}
#[doc = " @brief SWDT"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SWDT_TypeDef {
    pub RESERVED0: [u8; 4usize],
    pub SR: u32,
    pub RR: u32,
}
#[doc = " @brief TMR0"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR0_TypeDef {
    pub CNTAR: u32,
    pub CNTBR: u32,
    pub CMPAR: u32,
    pub CMPBR: u32,
    pub BCONR: u32,
    pub STFLR: u32,
}
#[doc = " @brief TMR4"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR4_TypeDef {
    pub RESERVED0: [u8; 2usize],
    pub OCCRUH: u16,
    pub RESERVED1: [u8; 2usize],
    pub OCCRUL: u16,
    pub RESERVED2: [u8; 2usize],
    pub OCCRVH: u16,
    pub RESERVED3: [u8; 2usize],
    pub OCCRVL: u16,
    pub RESERVED4: [u8; 2usize],
    pub OCCRWH: u16,
    pub RESERVED5: [u8; 2usize],
    pub OCCRWL: u16,
    pub OCSRU: u16,
    pub OCERU: u16,
    pub OCSRV: u16,
    pub OCERV: u16,
    pub OCSRW: u16,
    pub OCERW: u16,
    pub OCMRUH: u16,
    pub RESERVED6: [u8; 2usize],
    pub OCMRUL: u32,
    pub OCMRVH: u16,
    pub RESERVED7: [u8; 2usize],
    pub OCMRVL: u32,
    pub OCMRWH: u16,
    pub RESERVED8: [u8; 2usize],
    pub OCMRWL: u32,
    pub RESERVED9: [u8; 6usize],
    pub CPSR: u16,
    pub RESERVED10: [u8; 2usize],
    pub CNTR: u16,
    pub CCSR: u16,
    pub CVPR: u16,
    pub RESERVED11: [u8; 54usize],
    pub PFSRU: u16,
    pub PDARU: u16,
    pub PDBRU: u16,
    pub RESERVED12: [u8; 2usize],
    pub PFSRV: u16,
    pub PDARV: u16,
    pub PDBRV: u16,
    pub RESERVED13: [u8; 2usize],
    pub PFSRW: u16,
    pub PDARW: u16,
    pub PDBRW: u16,
    pub POCRU: u16,
    pub RESERVED14: [u8; 2usize],
    pub POCRV: u16,
    pub RESERVED15: [u8; 2usize],
    pub POCRW: u16,
    pub RESERVED16: [u8; 2usize],
    pub RCSR: u16,
    pub RESERVED17: [u8; 12usize],
    pub SCCRUH: u16,
    pub RESERVED18: [u8; 2usize],
    pub SCCRUL: u16,
    pub RESERVED19: [u8; 2usize],
    pub SCCRVH: u16,
    pub RESERVED20: [u8; 2usize],
    pub SCCRVL: u16,
    pub RESERVED21: [u8; 2usize],
    pub SCCRWH: u16,
    pub RESERVED22: [u8; 2usize],
    pub SCCRWL: u16,
    pub SCSRUH: u16,
    pub SCMRUH: u16,
    pub SCSRUL: u16,
    pub SCMRUL: u16,
    pub SCSRVH: u16,
    pub SCMRVH: u16,
    pub SCSRVL: u16,
    pub SCMRVL: u16,
    pub SCSRWH: u16,
    pub SCMRWH: u16,
    pub SCSRWL: u16,
    pub SCMRWL: u16,
    pub RESERVED23: [u8; 16usize],
    pub ECSR: u16,
}
#[doc = " @brief TMR4_ECER"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR4_ECER_TypeDef {
    pub ECER1: u32,
    pub ECER2: u32,
    pub ECER3: u32,
}
#[doc = " @brief TMR6"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_TypeDef {
    pub CNTER: u32,
    pub PERAR: u32,
    pub PERBR: u32,
    pub PERCR: u32,
    pub GCMAR: u32,
    pub GCMBR: u32,
    pub GCMCR: u32,
    pub GCMDR: u32,
    pub GCMER: u32,
    pub GCMFR: u32,
    pub SCMAR: u32,
    pub SCMBR: u32,
    pub SCMCR: u32,
    pub SCMDR: u32,
    pub SCMER: u32,
    pub SCMFR: u32,
    pub DTUAR: u32,
    pub DTDAR: u32,
    pub DTUBR: u32,
    pub DTDBR: u32,
    pub GCONR: u32,
    pub ICONR: u32,
    pub PCONR: u32,
    pub BCONR: u32,
    pub DCONR: u32,
    pub RESERVED0: [u8; 4usize],
    pub FCONR: u32,
    pub VPERR: u32,
    pub STFLR: u32,
    pub HSTAR: u32,
    pub HSTPR: u32,
    pub HCLRR: u32,
    pub HCPAR: u32,
    pub HCPBR: u32,
    pub HCUPR: u32,
    pub HCDOR: u32,
}
#[doc = " @brief TMR6_COMMON"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_COMMON_TypeDef {
    pub RESERVED0: [u8; 244usize],
    pub SSTAR: u32,
    pub SSTPR: u32,
    pub SCLRR: u32,
}
#[doc = " @brief TMRA"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMRA_TypeDef {
    pub CNTER: u16,
    pub RESERVED0: [u8; 2usize],
    pub PERAR: u16,
    pub RESERVED1: [u8; 58usize],
    pub CMPAR1: u16,
    pub RESERVED2: [u8; 2usize],
    pub CMPAR2: u16,
    pub RESERVED3: [u8; 2usize],
    pub CMPAR3: u16,
    pub RESERVED4: [u8; 2usize],
    pub CMPAR4: u16,
    pub RESERVED5: [u8; 2usize],
    pub CMPAR5: u16,
    pub RESERVED6: [u8; 2usize],
    pub CMPAR6: u16,
    pub RESERVED7: [u8; 2usize],
    pub CMPAR7: u16,
    pub RESERVED8: [u8; 2usize],
    pub CMPAR8: u16,
    pub RESERVED9: [u8; 34usize],
    pub BCSTRL: u8,
    pub BCSTRH: u8,
    pub RESERVED10: [u8; 2usize],
    pub HCONR: u16,
    pub RESERVED11: [u8; 2usize],
    pub HCUPR: u16,
    pub RESERVED12: [u8; 2usize],
    pub HCDOR: u16,
    pub RESERVED13: [u8; 2usize],
    pub ICONR: u16,
    pub RESERVED14: [u8; 2usize],
    pub ECONR: u16,
    pub RESERVED15: [u8; 2usize],
    pub FCONR: u16,
    pub RESERVED16: [u8; 2usize],
    pub STFLR: u16,
    pub RESERVED17: [u8; 34usize],
    pub BCONR1: u16,
    pub RESERVED18: [u8; 6usize],
    pub BCONR2: u16,
    pub RESERVED19: [u8; 6usize],
    pub BCONR3: u16,
    pub RESERVED20: [u8; 6usize],
    pub BCONR4: u16,
    pub RESERVED21: [u8; 38usize],
    pub CCONR1: u16,
    pub RESERVED22: [u8; 2usize],
    pub CCONR2: u16,
    pub RESERVED23: [u8; 2usize],
    pub CCONR3: u16,
    pub RESERVED24: [u8; 2usize],
    pub CCONR4: u16,
    pub RESERVED25: [u8; 2usize],
    pub CCONR5: u16,
    pub RESERVED26: [u8; 2usize],
    pub CCONR6: u16,
    pub RESERVED27: [u8; 2usize],
    pub CCONR7: u16,
    pub RESERVED28: [u8; 2usize],
    pub CCONR8: u16,
    pub RESERVED29: [u8; 34usize],
    pub PCONR1: u16,
    pub RESERVED30: [u8; 2usize],
    pub PCONR2: u16,
    pub RESERVED31: [u8; 2usize],
    pub PCONR3: u16,
    pub RESERVED32: [u8; 2usize],
    pub PCONR4: u16,
    pub RESERVED33: [u8; 2usize],
    pub PCONR5: u16,
    pub RESERVED34: [u8; 2usize],
    pub PCONR6: u16,
    pub RESERVED35: [u8; 2usize],
    pub PCONR7: u16,
    pub RESERVED36: [u8; 2usize],
    pub PCONR8: u16,
}
#[doc = " @brief TRNG"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TRNG_TypeDef {
    pub CR: u32,
    pub MR: u32,
    pub RESERVED0: [u8; 4usize],
    pub DR0: u32,
    pub DR1: u32,
}
#[doc = " @brief USART"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_USART_TypeDef {
    pub SR: u32,
    pub TDR: u16,
    pub RDR: u16,
    pub BRR: u32,
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub PR: u32,
}
#[doc = " @brief USBFS"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_USBFS_TypeDef {
    pub GVBUSCFG: u32,
    pub RESERVED0: [u8; 4usize],
    pub GAHBCFG: u32,
    pub GUSBCFG: u32,
    pub GRSTCTL: u32,
    pub GINTSTS: u32,
    pub GINTMSK: u32,
    pub GRXSTSR: u32,
    pub GRXSTSP: u32,
    pub GRXFSIZ: u32,
    pub HNPTXFSIZ: u32,
    pub HNPTXSTS: u32,
    pub RESERVED1: [u8; 12usize],
    pub CID: u32,
    pub RESERVED2: [u8; 192usize],
    pub HPTXFSIZ: u32,
    pub DIEPTXF1: u32,
    pub DIEPTXF2: u32,
    pub DIEPTXF3: u32,
    pub DIEPTXF4: u32,
    pub DIEPTXF5: u32,
    pub RESERVED3: [u8; 744usize],
    pub HCFG: u32,
    pub HFIR: u32,
    pub HFNUM: u32,
    pub RESERVED4: [u8; 4usize],
    pub HPTXSTS: u32,
    pub HAINT: u32,
    pub HAINTMSK: u32,
    pub RESERVED5: [u8; 36usize],
    pub HPRT: u32,
    pub RESERVED6: [u8; 188usize],
    pub HCCHAR0: u32,
    pub RESERVED7: [u8; 4usize],
    pub HCINT0: u32,
    pub HCINTMSK0: u32,
    pub HCTSIZ0: u32,
    pub HCDMA0: u32,
    pub RESERVED8: [u8; 8usize],
    pub HCCHAR1: u32,
    pub RESERVED9: [u8; 4usize],
    pub HCINT1: u32,
    pub HCINTMSK1: u32,
    pub HCTSIZ1: u32,
    pub HCDMA1: u32,
    pub RESERVED10: [u8; 8usize],
    pub HCCHAR2: u32,
    pub RESERVED11: [u8; 4usize],
    pub HCINT2: u32,
    pub HCINTMSK2: u32,
    pub HCTSIZ2: u32,
    pub HCDMA2: u32,
    pub RESERVED12: [u8; 8usize],
    pub HCCHAR3: u32,
    pub RESERVED13: [u8; 4usize],
    pub HCINT3: u32,
    pub HCINTMSK3: u32,
    pub HCTSIZ3: u32,
    pub HCDMA3: u32,
    pub RESERVED14: [u8; 8usize],
    pub HCCHAR4: u32,
    pub RESERVED15: [u8; 4usize],
    pub HCINT4: u32,
    pub HCINTMSK4: u32,
    pub HCTSIZ4: u32,
    pub HCDMA4: u32,
    pub RESERVED16: [u8; 8usize],
    pub HCCHAR5: u32,
    pub RESERVED17: [u8; 4usize],
    pub HCINT5: u32,
    pub HCINTMSK5: u32,
    pub HCTSIZ5: u32,
    pub HCDMA5: u32,
    pub RESERVED18: [u8; 8usize],
    pub HCCHAR6: u32,
    pub RESERVED19: [u8; 4usize],
    pub HCINT6: u32,
    pub HCINTMSK6: u32,
    pub HCTSIZ6: u32,
    pub HCDMA6: u32,
    pub RESERVED20: [u8; 8usize],
    pub HCCHAR7: u32,
    pub RESERVED21: [u8; 4usize],
    pub HCINT7: u32,
    pub HCINTMSK7: u32,
    pub HCTSIZ7: u32,
    pub HCDMA7: u32,
    pub RESERVED22: [u8; 8usize],
    pub HCCHAR8: u32,
    pub RESERVED23: [u8; 4usize],
    pub HCINT8: u32,
    pub HCINTMSK8: u32,
    pub HCTSIZ8: u32,
    pub HCDMA8: u32,
    pub RESERVED24: [u8; 8usize],
    pub HCCHAR9: u32,
    pub RESERVED25: [u8; 4usize],
    pub HCINT9: u32,
    pub HCINTMSK9: u32,
    pub HCTSIZ9: u32,
    pub HCDMA9: u32,
    pub RESERVED26: [u8; 8usize],
    pub HCCHAR10: u32,
    pub RESERVED27: [u8; 4usize],
    pub HCINT10: u32,
    pub HCINTMSK10: u32,
    pub HCTSIZ10: u32,
    pub HCDMA10: u32,
    pub RESERVED28: [u8; 8usize],
    pub HCCHAR11: u32,
    pub RESERVED29: [u8; 4usize],
    pub HCINT11: u32,
    pub HCINTMSK11: u32,
    pub HCTSIZ11: u32,
    pub HCDMA11: u32,
    pub RESERVED30: [u8; 392usize],
    pub DCFG: u32,
    pub DCTL: u32,
    pub DSTS: u32,
    pub RESERVED31: [u8; 4usize],
    pub DIEPMSK: u32,
    pub DOEPMSK: u32,
    pub DAINT: u32,
    pub DAINTMSK: u32,
    pub RESERVED32: [u8; 20usize],
    pub DIEPEMPMSK: u32,
    pub RESERVED33: [u8; 200usize],
    pub DIEPCTL0: u32,
    pub RESERVED34: [u8; 4usize],
    pub DIEPINT0: u32,
    pub RESERVED35: [u8; 4usize],
    pub DIEPTSIZ0: u32,
    pub DIEPDMA0: u32,
    pub DTXFSTS0: u32,
    pub RESERVED36: [u8; 4usize],
    pub DIEPCTL1: u32,
    pub RESERVED37: [u8; 4usize],
    pub DIEPINT1: u32,
    pub RESERVED38: [u8; 4usize],
    pub DIEPTSIZ1: u32,
    pub DIEPDMA1: u32,
    pub DTXFSTS1: u32,
    pub RESERVED39: [u8; 4usize],
    pub DIEPCTL2: u32,
    pub RESERVED40: [u8; 4usize],
    pub DIEPINT2: u32,
    pub RESERVED41: [u8; 4usize],
    pub DIEPTSIZ2: u32,
    pub DIEPDMA2: u32,
    pub DTXFSTS2: u32,
    pub RESERVED42: [u8; 4usize],
    pub DIEPCTL3: u32,
    pub RESERVED43: [u8; 4usize],
    pub DIEPINT3: u32,
    pub RESERVED44: [u8; 4usize],
    pub DIEPTSIZ3: u32,
    pub DIEPDMA3: u32,
    pub DTXFSTS3: u32,
    pub RESERVED45: [u8; 4usize],
    pub DIEPCTL4: u32,
    pub RESERVED46: [u8; 4usize],
    pub DIEPINT4: u32,
    pub RESERVED47: [u8; 4usize],
    pub DIEPTSIZ4: u32,
    pub DIEPDMA4: u32,
    pub DTXFSTS4: u32,
    pub RESERVED48: [u8; 4usize],
    pub DIEPCTL5: u32,
    pub RESERVED49: [u8; 4usize],
    pub DIEPINT5: u32,
    pub RESERVED50: [u8; 4usize],
    pub DIEPTSIZ5: u32,
    pub DIEPDMA5: u32,
    pub DTXFSTS5: u32,
    pub RESERVED51: [u8; 324usize],
    pub DOEPCTL0: u32,
    pub RESERVED52: [u8; 4usize],
    pub DOEPINT0: u32,
    pub RESERVED53: [u8; 4usize],
    pub DOEPTSIZ0: u32,
    pub DOEPDMA0: u32,
    pub RESERVED54: [u8; 8usize],
    pub DOEPCTL1: u32,
    pub RESERVED55: [u8; 4usize],
    pub DOEPINT1: u32,
    pub RESERVED56: [u8; 4usize],
    pub DOEPTSIZ1: u32,
    pub DOEPDMA1: u32,
    pub RESERVED57: [u8; 8usize],
    pub DOEPCTL2: u32,
    pub RESERVED58: [u8; 4usize],
    pub DOEPINT2: u32,
    pub RESERVED59: [u8; 4usize],
    pub DOEPTSIZ2: u32,
    pub DOEPDMA2: u32,
    pub RESERVED60: [u8; 8usize],
    pub DOEPCTL3: u32,
    pub RESERVED61: [u8; 4usize],
    pub DOEPINT3: u32,
    pub RESERVED62: [u8; 4usize],
    pub DOEPTSIZ3: u32,
    pub DOEPDMA3: u32,
    pub RESERVED63: [u8; 8usize],
    pub DOEPCTL4: u32,
    pub RESERVED64: [u8; 4usize],
    pub DOEPINT4: u32,
    pub RESERVED65: [u8; 4usize],
    pub DOEPTSIZ4: u32,
    pub DOEPDMA4: u32,
    pub RESERVED66: [u8; 8usize],
    pub DOEPCTL5: u32,
    pub RESERVED67: [u8; 4usize],
    pub DOEPINT5: u32,
    pub RESERVED68: [u8; 4usize],
    pub DOEPTSIZ5: u32,
    pub DOEPDMA5: u32,
    pub RESERVED69: [u8; 584usize],
    pub GCCTL: u32,
}
#[doc = " @brief WDT"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_WDT_TypeDef {
    pub CR: u32,
    pub SR: u32,
    pub RR: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_str_bit_t {
    pub STRT: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_cr0_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub CLREN: u32,
    pub DFMT: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_cr1_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub RSCHSEL: u32,
    pub RESERVED1: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_trgsr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub TRGENA: u32,
    pub RESERVED1: [u32; 7usize],
    pub TRGENB: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_isr_bit_t {
    pub EOCAF: u32,
    pub EOCBF: u32,
    pub RESERVED0: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_icr_bit_t {
    pub EOCAIEN: u32,
    pub EOCBIEN: u32,
    pub RESERVED0: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_synccr_bit_t {
    pub SYNCEN: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_awdcr_bit_t {
    pub AWDEN: u32,
    pub RESERVED0: [u32; 3usize],
    pub AWDMD: u32,
    pub RESERVED1: [u32; 3usize],
    pub AWDIEN: u32,
    pub RESERVED2: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_pgainsr1_bit_t {
    pub PGAVSSEN: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aes_cr_bit_t {
    pub START: u32,
    pub MODE: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aos_intsfttrg_bit_t {
    pub STRG: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aos_pevntnfcr_bit_t {
    pub NFEN1: u32,
    pub RESERVED0: [u32; 7usize],
    pub NFEN2: u32,
    pub RESERVED1: [u32; 7usize],
    pub NFEN3: u32,
    pub RESERVED2: [u32; 7usize],
    pub NFEN4: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_cfg_stat_bit_t {
    pub BUSOFF: u32,
    pub TACTIVE: u32,
    pub RACTIVE: u32,
    pub TSSS: u32,
    pub TPSS: u32,
    pub LBMI: u32,
    pub LBME: u32,
    pub RESET: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_tcmd_bit_t {
    pub TSA: u32,
    pub TSALL: u32,
    pub TSONE: u32,
    pub TPA: u32,
    pub TPE: u32,
    pub RESERVED0: [u32; 1usize],
    pub LOM: u32,
    pub TBSEL: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_tctrl_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub TTTBM: u32,
    pub TSMODE: u32,
    pub TSNEXT: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_rctrl_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub RBALL: u32,
    pub RREL: u32,
    pub ROV: u32,
    pub ROM: u32,
    pub SACK: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_rtie_bit_t {
    pub TSFF: u32,
    pub EIE: u32,
    pub TSIE: u32,
    pub TPIE: u32,
    pub RAFIE: u32,
    pub RFIE: u32,
    pub ROIE: u32,
    pub RIE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_rtif_bit_t {
    pub AIF: u32,
    pub EIF: u32,
    pub TSIF: u32,
    pub TPIF: u32,
    pub RAFIF: u32,
    pub RFIF: u32,
    pub ROIF: u32,
    pub RIF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_errint_bit_t {
    pub BEIF: u32,
    pub BEIE: u32,
    pub ALIF: u32,
    pub ALIE: u32,
    pub EPIF: u32,
    pub EPIE: u32,
    pub EPASS: u32,
    pub EWARN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_acfctrl_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub SELMASK: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_acfen_bit_t {
    pub AE_1: u32,
    pub AE_2: u32,
    pub AE_3: u32,
    pub AE_4: u32,
    pub AE_5: u32,
    pub AE_6: u32,
    pub AE_7: u32,
    pub AE_8: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_acf_bit_t {
    pub RESERVED0: [u32; 29usize],
    pub AIDE: u32,
    pub AIDEE: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_tbslot_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub TBF: u32,
    pub TBE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_ttcfg_bit_t {
    pub TTEN: u32,
    pub RESERVED0: [u32; 2usize],
    pub TTIF: u32,
    pub TTIE: u32,
    pub TEIF: u32,
    pub WTIF: u32,
    pub WTIE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_ref_msg_bit_t {
    pub RESERVED0: [u32; 31usize],
    pub REF_IDE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_ctrl_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub IEN: u32,
    pub CVSEN: u32,
    pub RESERVED1: [u32; 3usize],
    pub OUTEN: u32,
    pub INV: u32,
    pub CMPOE: u32,
    pub CMPON: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_vltsel_bit_t {
    pub RVSL0: u32,
    pub RVSL1: u32,
    pub RVSL2: u32,
    pub RVSL3: u32,
    pub RESERVED0: [u32; 4usize],
    pub CVSL0: u32,
    pub CVSL1: u32,
    pub CVSL2: u32,
    pub CVSL3: u32,
    pub C4SL0: u32,
    pub C4SL1: u32,
    pub C4SL2: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_outmon_bit_t {
    pub OMON: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_common_dacr_bit_t {
    pub DA1EN: u32,
    pub DA2EN: u32,
    pub RESERVED0: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_common_rvadc_bit_t {
    pub DA1SW: u32,
    pub DA2SW: u32,
    pub RESERVED0: [u32; 2usize],
    pub VREFSW: u32,
    pub RESERVED1: [u32; 11usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_crc_cr_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub CR: u32,
    pub REFIN: u32,
    pub REFOUT: u32,
    pub XOROUT: u32,
    pub RESERVED1: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_crc_reslt_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub CRCFLAG_16: u32,
    pub RESERVED1: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_crc_flg_bit_t {
    pub CRCFLAG_32: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dbgc_mcudbgstat_bit_t {
    pub CDBGPWRUPREQ: u32,
    pub CDBGPWRUPACK: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dbgc_mcustpctl_bit_t {
    pub SWDTSTP: u32,
    pub WDTSTP: u32,
    pub RTCSTP: u32,
    pub RESERVED0: [u32; 11usize],
    pub TMR01STP: u32,
    pub TMR02STP: u32,
    pub RESERVED1: [u32; 4usize],
    pub TMR41STP: u32,
    pub TMR42STP: u32,
    pub TMR43STP: u32,
    pub TM61STP: u32,
    pub TM62STP: u32,
    pub TMR63STP: u32,
    pub TMRA1STP: u32,
    pub TMRA2STP: u32,
    pub TMRA3STP: u32,
    pub TMRA4STP: u32,
    pub TMRA5STP: u32,
    pub TMRA6STP: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dbgc_mcutracectl_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub TRACEIOEN: u32,
    pub RESERVED1: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_ctl_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub COMPTRG: u32,
    pub RESERVED1: [u32; 22usize],
    pub INTEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_flag_bit_t {
    pub FLAG_OP: u32,
    pub FLAG_LS2: u32,
    pub FLAG_EQ2: u32,
    pub FLAG_GT2: u32,
    pub FLAG_LS1: u32,
    pub FLAG_EQ1: u32,
    pub FLAG_GT1: u32,
    pub RESERVED0: [u32; 25usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_flagclr_bit_t {
    pub CLR_OP: u32,
    pub CLR_LS2: u32,
    pub CLR_EQ2: u32,
    pub CLR_GT2: u32,
    pub CLR_LS1: u32,
    pub CLR_EQ1: u32,
    pub CLR_GT1: u32,
    pub RESERVED0: [u32; 25usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_intevtsel_bit_t {
    pub SEL_OP: u32,
    pub SEL_LS2: u32,
    pub SEL_EQ2: u32,
    pub SEL_GT2: u32,
    pub SEL_LS1: u32,
    pub SEL_EQ1: u32,
    pub SEL_GT1: u32,
    pub RESERVED0: [u32; 25usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_en_bit_t {
    pub EN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intstat0_bit_t {
    pub TRNERR0: u32,
    pub TRNERR1: u32,
    pub TRNERR2: u32,
    pub TRNERR3: u32,
    pub RESERVED0: [u32; 12usize],
    pub REQERR0: u32,
    pub REQERR1: u32,
    pub REQERR2: u32,
    pub REQERR3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intstat1_bit_t {
    pub TC0: u32,
    pub TC1: u32,
    pub TC2: u32,
    pub TC3: u32,
    pub RESERVED0: [u32; 12usize],
    pub BTC0: u32,
    pub BTC1: u32,
    pub BTC2: u32,
    pub BTC3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intmask0_bit_t {
    pub MSKTRNERR0: u32,
    pub MSKTRNERR1: u32,
    pub MSKTRNERR2: u32,
    pub MSKTRNERR3: u32,
    pub RESERVED0: [u32; 12usize],
    pub MSKREQERR0: u32,
    pub MSKREQERR1: u32,
    pub MSKREQERR2: u32,
    pub MSKREQERR3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intmask1_bit_t {
    pub MSKTC0: u32,
    pub MSKTC1: u32,
    pub MSKTC2: u32,
    pub MSKTC3: u32,
    pub RESERVED0: [u32; 12usize],
    pub MSKBTC0: u32,
    pub MSKBTC1: u32,
    pub MSKBTC2: u32,
    pub MSKBTC3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intclr0_bit_t {
    pub CLRTRNERR0: u32,
    pub CLRTRNERR1: u32,
    pub CLRTRNERR2: u32,
    pub CLRTRNERR3: u32,
    pub RESERVED0: [u32; 12usize],
    pub CLRREQERR0: u32,
    pub CLRREQERR1: u32,
    pub CLRREQERR2: u32,
    pub CLRREQERR3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intclr1_bit_t {
    pub CLRTC0: u32,
    pub CLRTC1: u32,
    pub CLRTC2: u32,
    pub CLRTC3: u32,
    pub RESERVED0: [u32; 12usize],
    pub CLRBTC0: u32,
    pub CLRBTC1: u32,
    pub CLRBTC2: u32,
    pub CLRBTC3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_reqstat_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub RCFGREQ: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_chstat_bit_t {
    pub DMAACT: u32,
    pub RCFGACT: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_rcfgctl_bit_t {
    pub RCFGEN: u32,
    pub RCFGLLP: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_swreq_bit_t {
    pub SWREQ0: u32,
    pub SWREQ1: u32,
    pub SWREQ2: u32,
    pub SWREQ3: u32,
    pub SWREQ4: u32,
    pub SWREQ5: u32,
    pub SWREQ6: u32,
    pub SWREQ7: u32,
    pub RESERVED0: [u32; 7usize],
    pub SWRCFGREQ: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_chctl_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub SRPTEN: u32,
    pub DRPTEN: u32,
    pub SNSEQEN: u32,
    pub DNSEQEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub LLPEN: u32,
    pub LLPRUN: u32,
    pub IE: u32,
    pub RESERVED2: [u32; 19usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fstp_bit_t {
    pub FSTP: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_frmc_bit_t {
    pub SLPMD: u32,
    pub RESERVED0: [u32; 7usize],
    pub LVM: u32,
    pub RESERVED1: [u32; 7usize],
    pub CACHE: u32,
    pub RESERVED2: [u32; 7usize],
    pub CRST: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fwmc_bit_t {
    pub PEMODE: u32,
    pub RESERVED0: [u32; 7usize],
    pub BUSHLDCTL: u32,
    pub RESERVED1: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fsr_bit_t {
    pub PEWERR: u32,
    pub PEPRTERR: u32,
    pub PGSZERR: u32,
    pub PGMISMTCH: u32,
    pub OPTEND: u32,
    pub COLERR: u32,
    pub RESERVED0: [u32; 2usize],
    pub RDY: u32,
    pub RESERVED1: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fsclr_bit_t {
    pub PEWERRCLR: u32,
    pub PEPRTERRCLR: u32,
    pub PGSZERRCLR: u32,
    pub PGMISMTCHCLR: u32,
    pub OPTENDCLR: u32,
    pub COLERRCLR: u32,
    pub RESERVED0: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fite_bit_t {
    pub PEERRITE: u32,
    pub OPTENDITE: u32,
    pub COLERRITE: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fswp_bit_t {
    pub FSWP: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_mmf_remcr_bit_t {
    pub RESERVED0: [u32; 31usize],
    pub EN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_ctl_bit_t {
    pub PORTINEN: u32,
    pub CMPEN1: u32,
    pub CMPEN2: u32,
    pub CMPEN3: u32,
    pub RESERVED0: [u32; 1usize],
    pub OSCSTPEN: u32,
    pub PWMSEN0: u32,
    pub PWMSEN1: u32,
    pub PWMSEN2: u32,
    pub RESERVED1: [u32; 21usize],
    pub NFEN: u32,
    pub INVSEL: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_pwmlv_bit_t {
    pub PWMLV0: u32,
    pub PWMLV1: u32,
    pub PWMLV2: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_soe_bit_t {
    pub SOE: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_stat_bit_t {
    pub PORTINF: u32,
    pub PWMSF: u32,
    pub CMPF: u32,
    pub OSF: u32,
    pub PORTINST: u32,
    pub PWMST: u32,
    pub RESERVED0: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_statclr_bit_t {
    pub PORTINFCLR: u32,
    pub PWMSFCLR: u32,
    pub CMPFCLR: u32,
    pub OSFCLR: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_inten_bit_t {
    pub PORTININTEN: u32,
    pub PWMSINTEN: u32,
    pub CMPINTEN: u32,
    pub OSINTEN: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_str_bit_t {
    pub START: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_rccr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub INEXS: u32,
    pub RESERVED1: [u32; 7usize],
    pub EXREFE: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_rier_bit_t {
    pub ERRIE: u32,
    pub MENDIE: u32,
    pub OVFIE: u32,
    pub RESERVED0: [u32; 1usize],
    pub ERRINTRS: u32,
    pub RESERVED1: [u32; 2usize],
    pub ERRE: u32,
    pub RESERVED2: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_sr_bit_t {
    pub ERRF: u32,
    pub MENDF: u32,
    pub OVF: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_clr_bit_t {
    pub ERRFCLR: u32,
    pub MENDFCLR: u32,
    pub OVFCLR: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pidr_bit_t {
    pub PIN00: u32,
    pub PIN01: u32,
    pub PIN02: u32,
    pub PIN03: u32,
    pub PIN04: u32,
    pub PIN05: u32,
    pub PIN06: u32,
    pub PIN07: u32,
    pub PIN08: u32,
    pub PIN09: u32,
    pub PIN10: u32,
    pub PIN11: u32,
    pub PIN12: u32,
    pub PIN13: u32,
    pub PIN14: u32,
    pub PIN15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_podr_bit_t {
    pub POUT00: u32,
    pub POUT01: u32,
    pub POUT02: u32,
    pub POUT03: u32,
    pub POUT04: u32,
    pub POUT05: u32,
    pub POUT06: u32,
    pub POUT07: u32,
    pub POUT08: u32,
    pub POUT09: u32,
    pub POUT10: u32,
    pub POUT11: u32,
    pub POUT12: u32,
    pub POUT13: u32,
    pub POUT14: u32,
    pub POUT15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_poer_bit_t {
    pub POUTE00: u32,
    pub POUTE01: u32,
    pub POUTE02: u32,
    pub POUTE03: u32,
    pub POUTE04: u32,
    pub POUTE05: u32,
    pub POUTE06: u32,
    pub POUTE07: u32,
    pub POUTE08: u32,
    pub POUTE09: u32,
    pub POUTE10: u32,
    pub POUTE11: u32,
    pub POUTE12: u32,
    pub POUTE13: u32,
    pub POUTE14: u32,
    pub POUTE15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_posr_bit_t {
    pub POS00: u32,
    pub POS01: u32,
    pub POS02: u32,
    pub POS03: u32,
    pub POS04: u32,
    pub POS05: u32,
    pub POS06: u32,
    pub POS07: u32,
    pub POS08: u32,
    pub POS09: u32,
    pub POS10: u32,
    pub POS11: u32,
    pub POS12: u32,
    pub POS13: u32,
    pub POS14: u32,
    pub POS15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_porr_bit_t {
    pub POR00: u32,
    pub POR01: u32,
    pub POR02: u32,
    pub POR03: u32,
    pub POR04: u32,
    pub POR05: u32,
    pub POR06: u32,
    pub POR07: u32,
    pub POR08: u32,
    pub POR09: u32,
    pub POR10: u32,
    pub POR11: u32,
    pub POR12: u32,
    pub POR13: u32,
    pub POR14: u32,
    pub POR15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_potr_bit_t {
    pub POT00: u32,
    pub POT01: u32,
    pub POT02: u32,
    pub POT03: u32,
    pub POT04: u32,
    pub POT05: u32,
    pub POT06: u32,
    pub POT07: u32,
    pub POT08: u32,
    pub POT09: u32,
    pub POT10: u32,
    pub POT11: u32,
    pub POT12: u32,
    pub POT13: u32,
    pub POT14: u32,
    pub POT15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pidrh_bit_t {
    pub PIN00: u32,
    pub PIN01: u32,
    pub PIN02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_podrh_bit_t {
    pub POUT00: u32,
    pub POUT01: u32,
    pub POUT02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_poerh_bit_t {
    pub POUTE00: u32,
    pub POUTE01: u32,
    pub POUTE02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_posrh_bit_t {
    pub POS00: u32,
    pub POS01: u32,
    pub POS02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_porrh_bit_t {
    pub POR00: u32,
    pub POR01: u32,
    pub POR02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_potrh_bit_t {
    pub POT00: u32,
    pub POT01: u32,
    pub POT02: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pwpr_bit_t {
    pub WE: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pcr_bit_t {
    pub POUT: u32,
    pub POUTE: u32,
    pub NOD: u32,
    pub RESERVED0: [u32; 3usize],
    pub PUU: u32,
    pub RESERVED1: [u32; 1usize],
    pub PIN: u32,
    pub INVE: u32,
    pub RESERVED2: [u32; 2usize],
    pub INTE: u32,
    pub RESERVED3: [u32; 1usize],
    pub LTE: u32,
    pub DDIS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pfsr_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub BFE: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_hash_cr_bit_t {
    pub START: u32,
    pub FST_GRP: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr1_bit_t {
    pub PE: u32,
    pub SMBUS: u32,
    pub SMBALRTEN: u32,
    pub SMBDEFAULTEN: u32,
    pub SMBHOSTEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub GCEN: u32,
    pub RESTART: u32,
    pub START: u32,
    pub STOP: u32,
    pub ACK: u32,
    pub RESERVED1: [u32; 4usize],
    pub SWRST: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr2_bit_t {
    pub STARTIE: u32,
    pub SLADDR0IE: u32,
    pub SLADDR1IE: u32,
    pub TENDIE: u32,
    pub STOPIE: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLIE: u32,
    pub TEMPTYIE: u32,
    pub RESERVED1: [u32; 1usize],
    pub ARLOIE: u32,
    pub RESERVED2: [u32; 2usize],
    pub NACKIE: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTIE: u32,
    pub RESERVED4: [u32; 5usize],
    pub GENCALLIE: u32,
    pub SMBDEFAULTIE: u32,
    pub SMBHOSTIE: u32,
    pub SMBALRTIE: u32,
    pub RESERVED5: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr3_bit_t {
    pub TMOUTEN: u32,
    pub LTMOUT: u32,
    pub HTMOUT: u32,
    pub RESERVED0: [u32; 4usize],
    pub FACKEN: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr4_bit_t {
    pub RESERVED0: [u32; 10usize],
    pub BUSWAIT: u32,
    pub RESERVED1: [u32; 21usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_slr0_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub SLADDR0EN: u32,
    pub RESERVED1: [u32; 2usize],
    pub ADDRMOD0: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_slr1_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub SLADDR1EN: u32,
    pub RESERVED1: [u32; 2usize],
    pub ADDRMOD1: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_sr_bit_t {
    pub STARTF: u32,
    pub SLADDR0F: u32,
    pub SLADDR1F: u32,
    pub TENDF: u32,
    pub STOPF: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLF: u32,
    pub TEMPTYF: u32,
    pub RESERVED1: [u32; 1usize],
    pub ARLOF: u32,
    pub ACKRF: u32,
    pub RESERVED2: [u32; 1usize],
    pub NACKF: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTF: u32,
    pub RESERVED4: [u32; 1usize],
    pub MSL: u32,
    pub BUSY: u32,
    pub TRA: u32,
    pub RESERVED5: [u32; 1usize],
    pub GENCALLF: u32,
    pub SMBDEFAULTF: u32,
    pub SMBHOSTF: u32,
    pub SMBALRTF: u32,
    pub RESERVED6: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_clr_bit_t {
    pub STARTFCLR: u32,
    pub SLADDR0FCLR: u32,
    pub SLADDR1FCLR: u32,
    pub TENDFCLR: u32,
    pub STOPFCLR: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLFCLR: u32,
    pub TEMPTYFCLR: u32,
    pub RESERVED1: [u32; 1usize],
    pub ARLOFCLR: u32,
    pub RESERVED2: [u32; 2usize],
    pub NACKFCLR: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTFCLR: u32,
    pub RESERVED4: [u32; 5usize],
    pub GENCALLFCLR: u32,
    pub SMBDEFAULTFCLR: u32,
    pub SMBHOSTFCLR: u32,
    pub SMBALRTFCLR: u32,
    pub RESERVED5: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_fltr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub DNFEN: u32,
    pub ANFEN: u32,
    pub RESERVED1: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2s_ctrl_bit_t {
    pub TXE: u32,
    pub TXIE: u32,
    pub RXE: u32,
    pub RXIE: u32,
    pub EIE: u32,
    pub WMS: u32,
    pub ODD: u32,
    pub MCKOE: u32,
    pub RESERVED0: [u32; 8usize],
    pub FIFOR: u32,
    pub RESERVED1: [u32; 1usize],
    pub I2SPLLSEL: u32,
    pub SDOE: u32,
    pub LRCKOE: u32,
    pub CKOE: u32,
    pub DUPLEX: u32,
    pub CLKSEL: u32,
    pub RESERVED2: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2s_sr_bit_t {
    pub TXBA: u32,
    pub RXBA: u32,
    pub TXBE: u32,
    pub TXBF: u32,
    pub RXBE: u32,
    pub RXBF: u32,
    pub RESERVED0: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2s_er_bit_t {
    pub TXERR: u32,
    pub RXERR: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2s_cfgr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub CHLEN: u32,
    pub PCMSYNC: u32,
    pub RESERVED1: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_icg_icg0_bit_t {
    pub SWDTAUTS: u32,
    pub SWDTITS: u32,
    pub RESERVED0: [u32; 10usize],
    pub SWDTSLPOFF: u32,
    pub RESERVED1: [u32; 3usize],
    pub WDTAUTS: u32,
    pub WDTITS: u32,
    pub RESERVED2: [u32; 10usize],
    pub WDTSLPOFF: u32,
    pub RESERVED3: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_icg_icg1_bit_t {
    pub HRCFREQSEL: u32,
    pub RESERVED0: [u32; 7usize],
    pub HRCSTOP: u32,
    pub RESERVED1: [u32; 9usize],
    pub BORDIS: u32,
    pub RESERVED2: [u32; 9usize],
    pub NMITRG: u32,
    pub NMIEN: u32,
    pub NFEN: u32,
    pub NMIICGEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmicr_bit_t {
    pub NMITRG: u32,
    pub RESERVED0: [u32; 6usize],
    pub NFEN: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmienr_bit_t {
    pub NMIENR: u32,
    pub SWDTENR: u32,
    pub PVD1ENR: u32,
    pub PVD2ENR: u32,
    pub RESERVED0: [u32; 1usize],
    pub XTALSTPENR: u32,
    pub RESERVED1: [u32; 2usize],
    pub REPENR: u32,
    pub RECCENR: u32,
    pub BUSMENR: u32,
    pub WDTENR: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmifr_bit_t {
    pub NMIFR: u32,
    pub SWDTFR: u32,
    pub PVD1FR: u32,
    pub PVD2FR: u32,
    pub RESERVED0: [u32; 1usize],
    pub XTALSTPFR: u32,
    pub RESERVED1: [u32; 2usize],
    pub REPFR: u32,
    pub RECCFR: u32,
    pub BUSMFR: u32,
    pub WDTFR: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmicfr_bit_t {
    pub NMICFR: u32,
    pub SWDTCFR: u32,
    pub PVD1CFR: u32,
    pub PVD2CFR: u32,
    pub RESERVED0: [u32; 1usize],
    pub XTALSTPCFR: u32,
    pub RESERVED1: [u32; 2usize],
    pub REPCFR: u32,
    pub RECCCFR: u32,
    pub BUSMCFR: u32,
    pub WDTCFR: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eirqcr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub EFEN: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_wupen_bit_t {
    pub EIRQWUEN0: u32,
    pub EIRQWUEN1: u32,
    pub EIRQWUEN2: u32,
    pub EIRQWUEN3: u32,
    pub EIRQWUEN4: u32,
    pub EIRQWUEN5: u32,
    pub EIRQWUEN6: u32,
    pub EIRQWUEN7: u32,
    pub EIRQWUEN8: u32,
    pub EIRQWUEN9: u32,
    pub EIRQWUEN10: u32,
    pub EIRQWUEN11: u32,
    pub EIRQWUEN12: u32,
    pub EIRQWUEN13: u32,
    pub EIRQWUEN14: u32,
    pub EIRQWUEN15: u32,
    pub SWDTWUEN: u32,
    pub PVD1WUEN: u32,
    pub PVD2WUEN: u32,
    pub CMPI0WUEN: u32,
    pub WKTMWUEN: u32,
    pub RTCALMWUEN: u32,
    pub RTCPRDWUEN: u32,
    pub TMR0WUEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub RXWUEN: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eifr_bit_t {
    pub EIFR0: u32,
    pub EIFR1: u32,
    pub EIFR2: u32,
    pub EIFR3: u32,
    pub EIFR4: u32,
    pub EIFR5: u32,
    pub EIFR6: u32,
    pub EIFR7: u32,
    pub EIFR8: u32,
    pub EIFR9: u32,
    pub EIFR10: u32,
    pub EIFR11: u32,
    pub EIFR12: u32,
    pub EIFR13: u32,
    pub EIFR14: u32,
    pub EIFR15: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eifcr_bit_t {
    pub EIFCR0: u32,
    pub EIFCR1: u32,
    pub EIFCR2: u32,
    pub EIFCR3: u32,
    pub EIFCR4: u32,
    pub EIFCR5: u32,
    pub EIFCR6: u32,
    pub EIFCR7: u32,
    pub EIFCR8: u32,
    pub EIFCR9: u32,
    pub EIFCR10: u32,
    pub EIFCR11: u32,
    pub EIFCR12: u32,
    pub EIFCR13: u32,
    pub EIFCR14: u32,
    pub EIFCR15: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_vssel_bit_t {
    pub VSEL0: u32,
    pub VSEL1: u32,
    pub VSEL2: u32,
    pub VSEL3: u32,
    pub VSEL4: u32,
    pub VSEL5: u32,
    pub VSEL6: u32,
    pub VSEL7: u32,
    pub VSEL8: u32,
    pub VSEL9: u32,
    pub VSEL10: u32,
    pub VSEL11: u32,
    pub VSEL12: u32,
    pub VSEL13: u32,
    pub VSEL14: u32,
    pub VSEL15: u32,
    pub VSEL16: u32,
    pub VSEL17: u32,
    pub VSEL18: u32,
    pub VSEL19: u32,
    pub VSEL20: u32,
    pub VSEL21: u32,
    pub VSEL22: u32,
    pub VSEL23: u32,
    pub VSEL24: u32,
    pub VSEL25: u32,
    pub VSEL26: u32,
    pub VSEL27: u32,
    pub VSEL28: u32,
    pub VSEL29: u32,
    pub VSEL30: u32,
    pub VSEL31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_swier_bit_t {
    pub SWIE0: u32,
    pub SWIE1: u32,
    pub SWIE2: u32,
    pub SWIE3: u32,
    pub SWIE4: u32,
    pub SWIE5: u32,
    pub SWIE6: u32,
    pub SWIE7: u32,
    pub SWIE8: u32,
    pub SWIE9: u32,
    pub SWIE10: u32,
    pub SWIE11: u32,
    pub SWIE12: u32,
    pub SWIE13: u32,
    pub SWIE14: u32,
    pub SWIE15: u32,
    pub SWIE16: u32,
    pub SWIE17: u32,
    pub SWIE18: u32,
    pub SWIE19: u32,
    pub SWIE20: u32,
    pub SWIE21: u32,
    pub SWIE22: u32,
    pub SWIE23: u32,
    pub SWIE24: u32,
    pub SWIE25: u32,
    pub SWIE26: u32,
    pub SWIE27: u32,
    pub SWIE28: u32,
    pub SWIE29: u32,
    pub SWIE30: u32,
    pub SWIE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_evter_bit_t {
    pub EVTE0: u32,
    pub EVTE1: u32,
    pub EVTE2: u32,
    pub EVTE3: u32,
    pub EVTE4: u32,
    pub EVTE5: u32,
    pub EVTE6: u32,
    pub EVTE7: u32,
    pub EVTE8: u32,
    pub EVTE9: u32,
    pub EVTE10: u32,
    pub EVTE11: u32,
    pub EVTE12: u32,
    pub EVTE13: u32,
    pub EVTE14: u32,
    pub EVTE15: u32,
    pub EVTE16: u32,
    pub EVTE17: u32,
    pub EVTE18: u32,
    pub EVTE19: u32,
    pub EVTE20: u32,
    pub EVTE21: u32,
    pub EVTE22: u32,
    pub EVTE23: u32,
    pub EVTE24: u32,
    pub EVTE25: u32,
    pub EVTE26: u32,
    pub EVTE27: u32,
    pub EVTE28: u32,
    pub EVTE29: u32,
    pub EVTE30: u32,
    pub EVTE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_ier_bit_t {
    pub IER0: u32,
    pub IER1: u32,
    pub IER2: u32,
    pub IER3: u32,
    pub IER4: u32,
    pub IER5: u32,
    pub IER6: u32,
    pub IER7: u32,
    pub IER8: u32,
    pub IER9: u32,
    pub IER10: u32,
    pub IER11: u32,
    pub IER12: u32,
    pub IER13: u32,
    pub IER14: u32,
    pub IER15: u32,
    pub IER16: u32,
    pub IER17: u32,
    pub IER18: u32,
    pub IER19: u32,
    pub IER20: u32,
    pub IER21: u32,
    pub IER22: u32,
    pub IER23: u32,
    pub IER24: u32,
    pub IER25: u32,
    pub IER26: u32,
    pub IER27: u32,
    pub IER28: u32,
    pub IER29: u32,
    pub IER30: u32,
    pub IER31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_keyscan_ser_bit_t {
    pub SEN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_rgcr_bit_t {
    pub S2RGRP: u32,
    pub S2RGWP: u32,
    pub RESERVED0: [u32; 5usize],
    pub S2RGE: u32,
    pub S1RGRP: u32,
    pub S1RGWP: u32,
    pub RESERVED1: [u32; 5usize],
    pub S1RGE: u32,
    pub FRGRP: u32,
    pub FRGWP: u32,
    pub RESERVED2: [u32; 5usize],
    pub FRGE: u32,
    pub RESERVED3: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_cr_bit_t {
    pub SMPU2BRP: u32,
    pub SMPU2BWP: u32,
    pub RESERVED0: [u32; 5usize],
    pub SMPU2E: u32,
    pub SMPU1BRP: u32,
    pub SMPU1BWP: u32,
    pub RESERVED1: [u32; 5usize],
    pub SMPU1E: u32,
    pub FMPUBRP: u32,
    pub FMPUBWP: u32,
    pub RESERVED2: [u32; 5usize],
    pub FMPUE: u32,
    pub RESERVED3: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_sr_bit_t {
    pub SMPU2EAF: u32,
    pub RESERVED0: [u32; 7usize],
    pub SMPU1EAF: u32,
    pub RESERVED1: [u32; 7usize],
    pub FMPUEAF: u32,
    pub RESERVED2: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_eclr_bit_t {
    pub SMPU2ECLR: u32,
    pub RESERVED0: [u32; 7usize],
    pub SMPU1ECLR: u32,
    pub RESERVED1: [u32; 7usize],
    pub FMPUECLR: u32,
    pub RESERVED2: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_wp_bit_t {
    pub MPUWE: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_ippr_bit_t {
    pub AESRDP: u32,
    pub AESWRP: u32,
    pub HASHRDP: u32,
    pub HASHWRP: u32,
    pub TRNGRDP: u32,
    pub TRNGWRP: u32,
    pub CRCRDP: u32,
    pub CRCWRP: u32,
    pub EFMRDP: u32,
    pub EFMWRP: u32,
    pub RESERVED0: [u32; 2usize],
    pub WDTRDP: u32,
    pub WDTWRP: u32,
    pub SWDTRDP: u32,
    pub SWDTWRP: u32,
    pub BKSRAMRDP: u32,
    pub BKSRAMWRP: u32,
    pub RTCRDP: u32,
    pub RTCWRP: u32,
    pub DMPURDP: u32,
    pub DMPUWRP: u32,
    pub SRAMCRDP: u32,
    pub SRAMCWRP: u32,
    pub INTCRDP: u32,
    pub INTCWRP: u32,
    pub SYSCRDP: u32,
    pub SYSCWRP: u32,
    pub MSTPRDP: u32,
    pub MSTPWRP: u32,
    pub RESERVED1: [u32; 1usize],
    pub BUSERRE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_ots_ctl_bit_t {
    pub OTSST: u32,
    pub OTSCK: u32,
    pub OTSIE: u32,
    pub TSSTP: u32,
    pub RESERVED0: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_peric_usbfs_syctlreg_bit_t {
    pub DFB: u32,
    pub SOFEN: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_peric_sdioc_syctlreg_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub SELMMC1: u32,
    pub RESERVED1: [u32; 1usize],
    pub SELMMC2: u32,
    pub RESERVED2: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_cr_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub PFE: u32,
    pub PFSAE: u32,
    pub DCOME: u32,
    pub XIPE: u32,
    pub SPIMD3: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_fcr_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub FOUR_BIC: u32,
    pub RESERVED1: [u32; 1usize],
    pub SSNHD: u32,
    pub SSNLD: u32,
    pub WPOL: u32,
    pub RESERVED2: [u32; 8usize],
    pub DUTY: u32,
    pub RESERVED3: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_sr_bit_t {
    pub BUSY: u32,
    pub RESERVED0: [u32; 5usize],
    pub XIPF: u32,
    pub RAER: u32,
    pub RESERVED1: [u32; 6usize],
    pub PFFUL: u32,
    pub PFAN: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_clr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub RAERCLR: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_rstf0_bit_t {
    pub PORF: u32,
    pub PINRF: u32,
    pub BORF: u32,
    pub PVD1RF: u32,
    pub PVD2RF: u32,
    pub WDRF: u32,
    pub SWDRF: u32,
    pub PDRF: u32,
    pub SWRF: u32,
    pub MPUERF: u32,
    pub RAPERF: u32,
    pub RAECRF: u32,
    pub CKFERF: u32,
    pub XTALERF: u32,
    pub MULTIRF: u32,
    pub CLRF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr0_bit_t {
    pub RESET: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr1_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub AMPM: u32,
    pub ALMFCLR: u32,
    pub ONEHZOE: u32,
    pub ONEHZSEL: u32,
    pub START: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr2_bit_t {
    pub RWREQ: u32,
    pub RWEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub ALMF: u32,
    pub RESERVED1: [u32; 1usize],
    pub PRDIE: u32,
    pub ALMIE: u32,
    pub ALME: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr3_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub LRCEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub RCKSEL: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_errcrh_bit_t {
    pub COMP8: u32,
    pub RESERVED0: [u32; 6usize],
    pub COMPEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_transmode_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub BCE: u32,
    pub RESERVED1: [u32; 2usize],
    pub DDIR: u32,
    pub MULB: u32,
    pub RESERVED2: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_cmd_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub CCE: u32,
    pub ICE: u32,
    pub DAT: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_pstat_bit_t {
    pub CIC: u32,
    pub CID: u32,
    pub DA: u32,
    pub RESERVED0: [u32; 5usize],
    pub WTA: u32,
    pub RTA: u32,
    pub BWE: u32,
    pub BRE: u32,
    pub RESERVED1: [u32; 4usize],
    pub CIN: u32,
    pub CSS: u32,
    pub CDL: u32,
    pub WPL: u32,
    pub RESERVED2: [u32; 4usize],
    pub CMDL: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_hostcon_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub DW: u32,
    pub HSEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub EXDW: u32,
    pub CDTL: u32,
    pub CDSS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_pwrcon_bit_t {
    pub PWON: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_blkgpcon_bit_t {
    pub SABGR: u32,
    pub CR: u32,
    pub RWC: u32,
    pub IABG: u32,
    pub RESERVED0: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_clkcon_bit_t {
    pub ICE: u32,
    pub RESERVED0: [u32; 1usize],
    pub CE: u32,
    pub RESERVED1: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_sftrst_bit_t {
    pub RSTA: u32,
    pub RSTC: u32,
    pub RSTD: u32,
    pub RESERVED0: [u32; 5usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_norintst_bit_t {
    pub CC: u32,
    pub TC: u32,
    pub BGE: u32,
    pub RESERVED0: [u32; 1usize],
    pub BWR: u32,
    pub BRR: u32,
    pub CIST: u32,
    pub CRM: u32,
    pub CINT: u32,
    pub RESERVED1: [u32; 6usize],
    pub EI: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_errintst_bit_t {
    pub CTOE: u32,
    pub CCE: u32,
    pub CEBE: u32,
    pub CIE: u32,
    pub DTOE: u32,
    pub DCE: u32,
    pub DEBE: u32,
    pub RESERVED0: [u32; 1usize],
    pub ACE: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_norintsten_bit_t {
    pub CCEN: u32,
    pub TCEN: u32,
    pub BGEEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub BWREN: u32,
    pub BRREN: u32,
    pub CISTEN: u32,
    pub CRMEN: u32,
    pub CINTEN: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_errintsten_bit_t {
    pub CTOEEN: u32,
    pub CCEEN: u32,
    pub CEBEEN: u32,
    pub CIEEN: u32,
    pub DTOEEN: u32,
    pub DCEEN: u32,
    pub DEBEEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub ACEEN: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_norintsgen_bit_t {
    pub CCSEN: u32,
    pub TCSEN: u32,
    pub BGESEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub BWRSEN: u32,
    pub BRRSEN: u32,
    pub CISTSEN: u32,
    pub CRMSEN: u32,
    pub CINTSEN: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_errintsgen_bit_t {
    pub CTOESEN: u32,
    pub CCESEN: u32,
    pub CEBESEN: u32,
    pub CIESEN: u32,
    pub DTOESEN: u32,
    pub DCESEN: u32,
    pub DEBESEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub ACESEN: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_atcerrst_bit_t {
    pub NE: u32,
    pub TOE: u32,
    pub CE: u32,
    pub EBE: u32,
    pub IE: u32,
    pub RESERVED0: [u32; 2usize],
    pub CMDE: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_fea_bit_t {
    pub FNE: u32,
    pub FTOE: u32,
    pub FCE: u32,
    pub FEBE: u32,
    pub FIE: u32,
    pub RESERVED0: [u32; 2usize],
    pub FCMDE: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_fee_bit_t {
    pub FCTOE: u32,
    pub FCCE: u32,
    pub FCEBE: u32,
    pub FCIE: u32,
    pub FDTOE: u32,
    pub FDCE: u32,
    pub FDEBE: u32,
    pub RESERVED0: [u32; 1usize],
    pub FACE: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cr1_bit_t {
    pub SPIMDS: u32,
    pub TXMDS: u32,
    pub RESERVED0: [u32; 1usize],
    pub MSTR: u32,
    pub SPLPBK: u32,
    pub SPLPBK2: u32,
    pub SPE: u32,
    pub CSUSPE: u32,
    pub EIE: u32,
    pub TXIE: u32,
    pub RXIE: u32,
    pub IDIE: u32,
    pub MODFE: u32,
    pub PATE: u32,
    pub PAOE: u32,
    pub PAE: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cfg1_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub SPRDTD: u32,
    pub RESERVED1: [u32; 1usize],
    pub SS0PV: u32,
    pub SS1PV: u32,
    pub SS2PV: u32,
    pub SS3PV: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_sr_bit_t {
    pub OVRERF: u32,
    pub IDLNF: u32,
    pub MODFERF: u32,
    pub PERF: u32,
    pub UDRERF: u32,
    pub TDEF: u32,
    pub RESERVED0: [u32; 1usize],
    pub RDFF: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cfg2_bit_t {
    pub CPHA: u32,
    pub CPOL: u32,
    pub RESERVED0: [u32; 10usize],
    pub LSBF: u32,
    pub MIDIE: u32,
    pub MSSDLE: u32,
    pub MSSIE: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_wtpr_bit_t {
    pub WTPRC: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_ckcr_bit_t {
    pub PYOAD: u32,
    pub RESERVED0: [u32; 15usize],
    pub ECCOAD: u32,
    pub RESERVED1: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_ckpr_bit_t {
    pub CKPRC: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_cksr_bit_t {
    pub SRAM3_1ERR: u32,
    pub SRAM3_2ERR: u32,
    pub SRAM12_PYERR: u32,
    pub SRAMH_PYERR: u32,
    pub SRAMR_PYERR: u32,
    pub RESERVED0: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_swdt_sr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub UDF: u32,
    pub REF: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr0_bconr_bit_t {
    pub CSTA: u32,
    pub CAPMDA: u32,
    pub INTENA: u32,
    pub RESERVED0: [u32; 5usize],
    pub SYNSA: u32,
    pub SYNCLKA: u32,
    pub ASYNCLKA: u32,
    pub RESERVED1: [u32; 1usize],
    pub HSTAA: u32,
    pub HSTPA: u32,
    pub HCLEA: u32,
    pub HICPA: u32,
    pub CSTB: u32,
    pub CAPMDB: u32,
    pub INTENB: u32,
    pub RESERVED2: [u32; 5usize],
    pub SYNSB: u32,
    pub SYNCLKB: u32,
    pub ASYNCLKB: u32,
    pub RESERVED3: [u32; 1usize],
    pub HSTAB: u32,
    pub HSTPB: u32,
    pub HCLEB: u32,
    pub HICPB: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr0_stflr_bit_t {
    pub CMFA: u32,
    pub RESERVED0: [u32; 15usize],
    pub CMFB: u32,
    pub RESERVED1: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocsr_bit_t {
    pub OCEH: u32,
    pub OCEL: u32,
    pub OCPH: u32,
    pub OCPL: u32,
    pub OCIEH: u32,
    pub OCIEL: u32,
    pub OCFH: u32,
    pub OCFL: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocer_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub LMCH: u32,
    pub LMCL: u32,
    pub LMMH: u32,
    pub LMML: u32,
    pub MCECH: u32,
    pub MCECL: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocmrh_bit_t {
    pub OCFDCH: u32,
    pub OCFPKH: u32,
    pub OCFUCH: u32,
    pub OCFZRH: u32,
    pub RESERVED0: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocmrl_bit_t {
    pub OCFDCL: u32,
    pub OCFPKL: u32,
    pub OCFUCL: u32,
    pub OCFZRL: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ccsr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub CLEAR: u32,
    pub MODE: u32,
    pub STOP: u32,
    pub BUFEN: u32,
    pub IRQPEN: u32,
    pub IRQPF: u32,
    pub RESERVED1: [u32; 3usize],
    pub IRQZEN: u32,
    pub IRQZF: u32,
    pub ECKEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_rcsr_bit_t {
    pub RTIDU: u32,
    pub RTIDV: u32,
    pub RTIDW: u32,
    pub RESERVED0: [u32; 1usize],
    pub RTIFU: u32,
    pub RTICU: u32,
    pub RTEU: u32,
    pub RTSU: u32,
    pub RTIFV: u32,
    pub RTICV: u32,
    pub RTEV: u32,
    pub RTSV: u32,
    pub RTIFW: u32,
    pub RTICW: u32,
    pub RTEW: u32,
    pub RTSW: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scsr_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub LMC: u32,
    pub RESERVED1: [u32; 2usize],
    pub EVTMS: u32,
    pub EVTDS: u32,
    pub RESERVED2: [u32; 2usize],
    pub DEN: u32,
    pub PEN: u32,
    pub UEN: u32,
    pub ZEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scmr_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub MZCE: u32,
    pub MPCE: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ecsr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub HOLD: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_gconr_bit_t {
    pub START: u32,
    pub RESERVED0: [u32; 7usize],
    pub DIR: u32,
    pub RESERVED1: [u32; 7usize],
    pub ZMSKREV: u32,
    pub ZMSKPOS: u32,
    pub RESERVED2: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_iconr_bit_t {
    pub INTENA: u32,
    pub INTENB: u32,
    pub INTENC: u32,
    pub INTEND: u32,
    pub INTENE: u32,
    pub INTENF: u32,
    pub INTENOVF: u32,
    pub INTENUDF: u32,
    pub INTENDTE: u32,
    pub RESERVED0: [u32; 7usize],
    pub INTENSAU: u32,
    pub INTENSAD: u32,
    pub INTENSBU: u32,
    pub INTENSBD: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_pconr_bit_t {
    pub CAPMDA: u32,
    pub STACA: u32,
    pub STPCA: u32,
    pub STASTPSA: u32,
    pub RESERVED0: [u32; 4usize],
    pub OUTENA: u32,
    pub RESERVED1: [u32; 7usize],
    pub CAPMDB: u32,
    pub STACB: u32,
    pub STPCB: u32,
    pub STASTPSB: u32,
    pub RESERVED2: [u32; 4usize],
    pub OUTENB: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_bconr_bit_t {
    pub BENA: u32,
    pub BSEA: u32,
    pub BENB: u32,
    pub BSEB: u32,
    pub RESERVED0: [u32; 4usize],
    pub BENP: u32,
    pub BSEP: u32,
    pub RESERVED1: [u32; 6usize],
    pub BENSPA: u32,
    pub BSESPA: u32,
    pub RESERVED2: [u32; 2usize],
    pub BTRUSPA: u32,
    pub BTRDSPA: u32,
    pub RESERVED3: [u32; 2usize],
    pub BENSPB: u32,
    pub BSESPB: u32,
    pub RESERVED4: [u32; 2usize],
    pub BTRUSPB: u32,
    pub BTRDSPB: u32,
    pub RESERVED5: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_dconr_bit_t {
    pub DTCEN: u32,
    pub RESERVED0: [u32; 3usize],
    pub DTBENU: u32,
    pub DTBEND: u32,
    pub RESERVED1: [u32; 2usize],
    pub SEPA: u32,
    pub RESERVED2: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_fconr_bit_t {
    pub NOFIENGA: u32,
    pub RESERVED0: [u32; 3usize],
    pub NOFIENGB: u32,
    pub RESERVED1: [u32; 11usize],
    pub NOFIENTA: u32,
    pub RESERVED2: [u32; 3usize],
    pub NOFIENTB: u32,
    pub RESERVED3: [u32; 11usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_vperr_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub SPPERIA: u32,
    pub SPPERIB: u32,
    pub RESERVED1: [u32; 22usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_stflr_bit_t {
    pub CMAF: u32,
    pub CMBF: u32,
    pub CMCF: u32,
    pub CMDF: u32,
    pub CMEF: u32,
    pub CMFF: u32,
    pub OVFF: u32,
    pub UDFF: u32,
    pub DTEF: u32,
    pub CMSAUF: u32,
    pub CMSADF: u32,
    pub CMSBUF: u32,
    pub CMSBDF: u32,
    pub RESERVED0: [u32; 18usize],
    pub DIRF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hstar_bit_t {
    pub HSTA0: u32,
    pub HSTA1: u32,
    pub RESERVED0: [u32; 2usize],
    pub HSTA4: u32,
    pub HSTA5: u32,
    pub HSTA6: u32,
    pub HSTA7: u32,
    pub HSTA8: u32,
    pub HSTA9: u32,
    pub HSTA10: u32,
    pub HSTA11: u32,
    pub RESERVED1: [u32; 19usize],
    pub STAS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hstpr_bit_t {
    pub HSTP0: u32,
    pub HSTP1: u32,
    pub RESERVED0: [u32; 2usize],
    pub HSTP4: u32,
    pub HSTP5: u32,
    pub HSTP6: u32,
    pub HSTP7: u32,
    pub HSTP8: u32,
    pub HSTP9: u32,
    pub HSTP10: u32,
    pub HSTP11: u32,
    pub RESERVED1: [u32; 19usize],
    pub STPS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hclrr_bit_t {
    pub HCLE0: u32,
    pub HCLE1: u32,
    pub RESERVED0: [u32; 2usize],
    pub HCLE4: u32,
    pub HCLE5: u32,
    pub HCLE6: u32,
    pub HCLE7: u32,
    pub HCLE8: u32,
    pub HCLE9: u32,
    pub HCLE10: u32,
    pub HCLE11: u32,
    pub RESERVED1: [u32; 19usize],
    pub CLES: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcpar_bit_t {
    pub HCPA0: u32,
    pub HCPA1: u32,
    pub RESERVED0: [u32; 2usize],
    pub HCPA4: u32,
    pub HCPA5: u32,
    pub HCPA6: u32,
    pub HCPA7: u32,
    pub HCPA8: u32,
    pub HCPA9: u32,
    pub HCPA10: u32,
    pub HCPA11: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcpbr_bit_t {
    pub HCPB0: u32,
    pub HCPB1: u32,
    pub RESERVED0: [u32; 2usize],
    pub HCPB4: u32,
    pub HCPB5: u32,
    pub HCPB6: u32,
    pub HCPB7: u32,
    pub HCPB8: u32,
    pub HCPB9: u32,
    pub HCPB10: u32,
    pub HCPB11: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcupr_bit_t {
    pub HCUP0: u32,
    pub HCUP1: u32,
    pub HCUP2: u32,
    pub HCUP3: u32,
    pub HCUP4: u32,
    pub HCUP5: u32,
    pub HCUP6: u32,
    pub HCUP7: u32,
    pub HCUP8: u32,
    pub HCUP9: u32,
    pub HCUP10: u32,
    pub HCUP11: u32,
    pub RESERVED0: [u32; 4usize],
    pub HCUP16: u32,
    pub HCUP17: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcdor_bit_t {
    pub HCDO0: u32,
    pub HCDO1: u32,
    pub HCDO2: u32,
    pub HCDO3: u32,
    pub HCDO4: u32,
    pub HCDO5: u32,
    pub HCDO6: u32,
    pub HCDO7: u32,
    pub HCDO8: u32,
    pub HCDO9: u32,
    pub HCDO10: u32,
    pub HCDO11: u32,
    pub RESERVED0: [u32; 4usize],
    pub HCDO16: u32,
    pub HCDO17: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sstar_bit_t {
    pub SSTA1: u32,
    pub SSTA2: u32,
    pub SSTA3: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sstpr_bit_t {
    pub SSTP1: u32,
    pub SSTP2: u32,
    pub SSTP3: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sclrr_bit_t {
    pub SCLE1: u32,
    pub SCLE2: u32,
    pub SCLE3: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bcstrl_bit_t {
    pub START: u32,
    pub DIR: u32,
    pub MODE: u32,
    pub SYNST: u32,
    pub RESERVED0: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bcstrh_bit_t {
    pub OVSTP: u32,
    pub RESERVED0: [u32; 3usize],
    pub ITENOVF: u32,
    pub ITENUDF: u32,
    pub OVFF: u32,
    pub UDFF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hconr_bit_t {
    pub HSTA0: u32,
    pub HSTA1: u32,
    pub HSTA2: u32,
    pub RESERVED0: [u32; 1usize],
    pub HSTP0: u32,
    pub HSTP1: u32,
    pub HSTP2: u32,
    pub RESERVED1: [u32; 1usize],
    pub HCLE0: u32,
    pub HCLE1: u32,
    pub HCLE2: u32,
    pub RESERVED2: [u32; 1usize],
    pub HCLE3: u32,
    pub HCLE4: u32,
    pub HCLE5: u32,
    pub HCLE6: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hcupr_bit_t {
    pub HCUP0: u32,
    pub HCUP1: u32,
    pub HCUP2: u32,
    pub HCUP3: u32,
    pub HCUP4: u32,
    pub HCUP5: u32,
    pub HCUP6: u32,
    pub HCUP7: u32,
    pub HCUP8: u32,
    pub HCUP9: u32,
    pub HCUP10: u32,
    pub HCUP11: u32,
    pub HCUP12: u32,
    pub RESERVED0: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hcdor_bit_t {
    pub HCDO0: u32,
    pub HCDO1: u32,
    pub HCDO2: u32,
    pub HCDO3: u32,
    pub HCDO4: u32,
    pub HCDO5: u32,
    pub HCDO6: u32,
    pub HCDO7: u32,
    pub HCDO8: u32,
    pub HCDO9: u32,
    pub HCDO10: u32,
    pub HCDO11: u32,
    pub HCDO12: u32,
    pub RESERVED0: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_iconr_bit_t {
    pub ITEN1: u32,
    pub ITEN2: u32,
    pub ITEN3: u32,
    pub ITEN4: u32,
    pub ITEN5: u32,
    pub ITEN6: u32,
    pub ITEN7: u32,
    pub ITEN8: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_econr_bit_t {
    pub ETEN1: u32,
    pub ETEN2: u32,
    pub ETEN3: u32,
    pub ETEN4: u32,
    pub ETEN5: u32,
    pub ETEN6: u32,
    pub ETEN7: u32,
    pub ETEN8: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_fconr_bit_t {
    pub NOFIENTG: u32,
    pub RESERVED0: [u32; 7usize],
    pub NOFIENCA: u32,
    pub RESERVED1: [u32; 3usize],
    pub NOFIENCB: u32,
    pub RESERVED2: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_stflr_bit_t {
    pub CMPF1: u32,
    pub CMPF2: u32,
    pub CMPF3: u32,
    pub CMPF4: u32,
    pub CMPF5: u32,
    pub CMPF6: u32,
    pub CMPF7: u32,
    pub CMPF8: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bconr_bit_t {
    pub BEN: u32,
    pub BSE0: u32,
    pub BSE1: u32,
    pub RESERVED0: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_cconr_bit_t {
    pub CAPMD: u32,
    pub RESERVED0: [u32; 3usize],
    pub HICP0: u32,
    pub HICP1: u32,
    pub HICP2: u32,
    pub RESERVED1: [u32; 1usize],
    pub HICP3: u32,
    pub HICP4: u32,
    pub RESERVED2: [u32; 2usize],
    pub NOFIENCP: u32,
    pub RESERVED3: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_pconr_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub OUTEN: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_trng_cr_bit_t {
    pub EN: u32,
    pub RUN: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_trng_mr_bit_t {
    pub LOAD: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_sr_bit_t {
    pub PE: u32,
    pub FE: u32,
    pub RESERVED0: [u32; 1usize],
    pub ORE: u32,
    pub RESERVED1: [u32; 1usize],
    pub RXNE: u32,
    pub TC: u32,
    pub TXE: u32,
    pub RTOF: u32,
    pub RESERVED2: [u32; 7usize],
    pub MPB: u32,
    pub RESERVED3: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_tdr_bit_t {
    pub RESERVED0: [u32; 9usize],
    pub MPID: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr1_bit_t {
    pub RTOE: u32,
    pub RTOIE: u32,
    pub RE: u32,
    pub TE: u32,
    pub SLME: u32,
    pub RIE: u32,
    pub TCIE: u32,
    pub TXEIE: u32,
    pub RESERVED0: [u32; 1usize],
    pub PS: u32,
    pub PCE: u32,
    pub RESERVED1: [u32; 1usize],
    pub M: u32,
    pub RESERVED2: [u32; 2usize],
    pub OVER8: u32,
    pub CPE: u32,
    pub CFE: u32,
    pub RESERVED3: [u32; 1usize],
    pub CORE: u32,
    pub CRTOF: u32,
    pub RESERVED4: [u32; 3usize],
    pub MS: u32,
    pub RESERVED5: [u32; 3usize],
    pub ML: u32,
    pub FBME: u32,
    pub NFE: u32,
    pub SBS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr2_bit_t {
    pub MPE: u32,
    pub RESERVED0: [u32; 12usize],
    pub STOP: u32,
    pub RESERVED1: [u32; 18usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr3_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub SCEN: u32,
    pub RESERVED1: [u32; 3usize],
    pub CTSE: u32,
    pub RESERVED2: [u32; 22usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gvbuscfg_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub VBUSOVEN: u32,
    pub VBUSVAL: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gahbcfg_bit_t {
    pub GINTMSK: u32,
    pub RESERVED0: [u32; 4usize],
    pub DMAEN: u32,
    pub RESERVED1: [u32; 1usize],
    pub TXFELVL: u32,
    pub PTXFELVL: u32,
    pub RESERVED2: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gusbcfg_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub PHYSEL: u32,
    pub RESERVED1: [u32; 22usize],
    pub FHMOD: u32,
    pub FDMOD: u32,
    pub RESERVED2: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_grstctl_bit_t {
    pub CSRST: u32,
    pub HSRST: u32,
    pub FCRST: u32,
    pub RESERVED0: [u32; 1usize],
    pub RXFFLSH: u32,
    pub TXFFLSH: u32,
    pub RESERVED1: [u32; 24usize],
    pub DMAREQ: u32,
    pub AHBIDL: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gintsts_bit_t {
    pub CMOD: u32,
    pub MMIS: u32,
    pub RESERVED0: [u32; 1usize],
    pub SOF: u32,
    pub RXFNE: u32,
    pub NPTXFE: u32,
    pub GINAKEFF: u32,
    pub GONAKEFF: u32,
    pub RESERVED1: [u32; 2usize],
    pub ESUSP: u32,
    pub USBSUSP: u32,
    pub USBRST: u32,
    pub ENUMDNE: u32,
    pub ISOODRP: u32,
    pub EOPF: u32,
    pub RESERVED2: [u32; 2usize],
    pub IEPINT: u32,
    pub OEPINT: u32,
    pub IISOIXFR: u32,
    pub IPXFR_INCOMPISOOUT: u32,
    pub DATAFSUSP: u32,
    pub RESERVED3: [u32; 1usize],
    pub HPRTINT: u32,
    pub HCINT: u32,
    pub PTXFE: u32,
    pub RESERVED4: [u32; 1usize],
    pub CIDSCHG: u32,
    pub DISCINT: u32,
    pub VBUSVINT: u32,
    pub WKUINT: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gintmsk_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub MMISM: u32,
    pub RESERVED1: [u32; 1usize],
    pub SOFM: u32,
    pub RXFNEM: u32,
    pub NPTXFEM: u32,
    pub GINAKEFFM: u32,
    pub GONAKEFFM: u32,
    pub RESERVED2: [u32; 2usize],
    pub ESUSPM: u32,
    pub USBSUSPM: u32,
    pub USBRSTM: u32,
    pub ENUMDNEM: u32,
    pub ISOODRPM: u32,
    pub EOPFM: u32,
    pub RESERVED3: [u32; 2usize],
    pub IEPIM: u32,
    pub OEPIM: u32,
    pub IISOIXFRM: u32,
    pub IPXFRM_INCOMPISOOUTM: u32,
    pub DATAFSUSPM: u32,
    pub RESERVED4: [u32; 1usize],
    pub HPRTIM: u32,
    pub HCIM: u32,
    pub PTXFEM: u32,
    pub RESERVED5: [u32; 1usize],
    pub CIDSCHGM: u32,
    pub DISCIM: u32,
    pub VBUSVIM: u32,
    pub WKUIM: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_hcfg_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub FSLSS: u32,
    pub RESERVED1: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_hprt_bit_t {
    pub PCSTS: u32,
    pub PCDET: u32,
    pub PENA: u32,
    pub PENCHNG: u32,
    pub RESERVED0: [u32; 2usize],
    pub PRES: u32,
    pub PSUSP: u32,
    pub PRST: u32,
    pub RESERVED1: [u32; 3usize],
    pub PWPR: u32,
    pub RESERVED2: [u32; 19usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_hcchar_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub EPDIR: u32,
    pub RESERVED1: [u32; 1usize],
    pub LSDEV: u32,
    pub RESERVED2: [u32; 11usize],
    pub ODDFRM: u32,
    pub CHDIS: u32,
    pub CHENA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_hcint_bit_t {
    pub XFRC: u32,
    pub CHH: u32,
    pub RESERVED0: [u32; 1usize],
    pub STALL: u32,
    pub NAK: u32,
    pub ACK: u32,
    pub RESERVED1: [u32; 1usize],
    pub TXERR: u32,
    pub BBERR: u32,
    pub FRMOR: u32,
    pub DTERR: u32,
    pub RESERVED2: [u32; 21usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_hcintmsk_bit_t {
    pub XFRCM: u32,
    pub CHHM: u32,
    pub RESERVED0: [u32; 1usize],
    pub STALLM: u32,
    pub NAKM: u32,
    pub ACKM: u32,
    pub RESERVED1: [u32; 1usize],
    pub TXERRM: u32,
    pub BBERRM: u32,
    pub FRMORM: u32,
    pub DTERRM: u32,
    pub RESERVED2: [u32; 21usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_dcfg_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub NZLSOHSK: u32,
    pub RESERVED1: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_dctl_bit_t {
    pub RWUSIG: u32,
    pub SDIS: u32,
    pub GINSTS: u32,
    pub GONSTS: u32,
    pub RESERVED0: [u32; 3usize],
    pub SGINAK: u32,
    pub CGINAK: u32,
    pub SGONAK: u32,
    pub CGONAK: u32,
    pub POPRGDNE: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_dsts_bit_t {
    pub SUSPSTS: u32,
    pub RESERVED0: [u32; 2usize],
    pub EERR: u32,
    pub RESERVED1: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_diepmsk_bit_t {
    pub XFRCM: u32,
    pub EPDM: u32,
    pub RESERVED0: [u32; 1usize],
    pub TOM: u32,
    pub TTXFEMSK: u32,
    pub INEPNMM: u32,
    pub INEPNEM: u32,
    pub RESERVED1: [u32; 25usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_doepmsk_bit_t {
    pub XFRCM: u32,
    pub EPDM: u32,
    pub RESERVED0: [u32; 1usize],
    pub STUPM: u32,
    pub OTEPDM: u32,
    pub RESERVED1: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_diepctl0_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub USBAEP: u32,
    pub RESERVED1: [u32; 1usize],
    pub NAKSTS: u32,
    pub RESERVED2: [u32; 3usize],
    pub STALL: u32,
    pub RESERVED3: [u32; 4usize],
    pub CNAK: u32,
    pub SNAK: u32,
    pub RESERVED4: [u32; 2usize],
    pub EPDIS: u32,
    pub EPENA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_diepint_bit_t {
    pub XFRC: u32,
    pub EPDISD: u32,
    pub RESERVED0: [u32; 1usize],
    pub TOC: u32,
    pub TTXFE: u32,
    pub RESERVED1: [u32; 1usize],
    pub INEPNE: u32,
    pub TXFE: u32,
    pub RESERVED2: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_diepctl_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub USBAEP: u32,
    pub EONUM_DPID: u32,
    pub NAKSTS: u32,
    pub RESERVED1: [u32; 3usize],
    pub STALL: u32,
    pub RESERVED2: [u32; 4usize],
    pub CNAK: u32,
    pub SNAK: u32,
    pub SD0PID_SEVNFRM: u32,
    pub SODDFRM: u32,
    pub EPDIS: u32,
    pub EPENA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_doepctl0_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub USBAEP: u32,
    pub RESERVED1: [u32; 1usize],
    pub NAKSTS: u32,
    pub RESERVED2: [u32; 2usize],
    pub SNPM: u32,
    pub STALL: u32,
    pub RESERVED3: [u32; 4usize],
    pub CNAK: u32,
    pub SNAK: u32,
    pub RESERVED4: [u32; 2usize],
    pub EPDIS: u32,
    pub EPENA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_doepint_bit_t {
    pub XFRC: u32,
    pub EPDISD: u32,
    pub RESERVED0: [u32; 1usize],
    pub STUP: u32,
    pub OTEPDIS: u32,
    pub RESERVED1: [u32; 1usize],
    pub B2BSTUP: u32,
    pub RESERVED2: [u32; 25usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_doeptsiz0_bit_t {
    pub RESERVED0: [u32; 19usize],
    pub PKTCNT: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_doepctl_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub USBAEP: u32,
    pub DPID: u32,
    pub NAKSTS: u32,
    pub RESERVED1: [u32; 2usize],
    pub SNPM: u32,
    pub STALL: u32,
    pub RESERVED2: [u32; 4usize],
    pub CNAK: u32,
    pub SNAK: u32,
    pub SD0PID: u32,
    pub SD1PID: u32,
    pub EPDIS: u32,
    pub EPENA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usbfs_gcctl_bit_t {
    pub STPPCLK: u32,
    pub GATEHCLK: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_wdt_cr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub SLPOFF: u32,
    pub RESERVED1: [u32; 14usize],
    pub ITS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_wdt_sr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub UDF: u32,
    pub REF: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_ADC_TypeDef {
    pub STR_b: stc_adc_str_bit_t,
    pub RESERVED0: [u32; 8usize],
    pub CR0_b: stc_adc_cr0_bit_t,
    pub CR1_b: stc_adc_cr1_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub TRGSR_b: stc_adc_trgsr_bit_t,
    pub RESERVED2: [u32; 464usize],
    pub ISR_b: stc_adc_isr_bit_t,
    pub ICR_b: stc_adc_icr_bit_t,
    pub RESERVED3: [u32; 32usize],
    pub SYNCCR_b: stc_adc_synccr_bit_t,
    pub RESERVED4: [u32; 656usize],
    pub AWDCR_b: stc_adc_awdcr_bit_t,
    pub RESERVED5: [u32; 352usize],
    pub PGAINSR1_b: stc_adc_pgainsr1_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_AES_TypeDef {
    pub CR_b: stc_aes_cr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_AOS_TypeDef {
    pub INTSFTTRG_b: stc_aos_intsfttrg_bit_t,
    pub RESERVED0: [u32; 2912usize],
    pub PEVNTNFCR_b: stc_aos_pevntnfcr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CAN_TypeDef {
    pub RESERVED0: [u32; 1280usize],
    pub CFG_STAT_b: stc_can_cfg_stat_bit_t,
    pub TCMD_b: stc_can_tcmd_bit_t,
    pub TCTRL_b: stc_can_tctrl_bit_t,
    pub RCTRL_b: stc_can_rctrl_bit_t,
    pub RTIE_b: stc_can_rtie_bit_t,
    pub RTIF_b: stc_can_rtif_bit_t,
    pub ERRINT_b: stc_can_errint_bit_t,
    pub RESERVED1: [u32; 104usize],
    pub ACFCTRL_b: stc_can_acfctrl_bit_t,
    pub RESERVED2: [u32; 8usize],
    pub ACFEN_b: stc_can_acfen_bit_t,
    pub RESERVED3: [u32; 8usize],
    pub ACF_b: stc_can_acf_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub TBSLOT_b: stc_can_tbslot_bit_t,
    pub TTCFG_b: stc_can_ttcfg_bit_t,
    pub REF_MSG_b: stc_can_ref_msg_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CMP_TypeDef {
    pub CTRL_b: stc_cmp_ctrl_bit_t,
    pub VLTSEL_b: stc_cmp_vltsel_bit_t,
    pub OUTMON_b: stc_cmp_outmon_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CMP_COMMON_TypeDef {
    pub RESERVED0: [u32; 2112usize],
    pub DACR_b: stc_cmp_common_dacr_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub RVADC_b: stc_cmp_common_rvadc_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CRC_TypeDef {
    pub CR_b: stc_crc_cr_bit_t,
    pub RESLT_b: stc_crc_reslt_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub FLG_b: stc_crc_flg_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DBGC_TypeDef {
    pub RESERVED0: [u32; 224usize],
    pub MCUDBGSTAT_b: stc_dbgc_mcudbgstat_bit_t,
    pub MCUSTPCTL_b: stc_dbgc_mcustpctl_bit_t,
    pub MCUTRACECTL_b: stc_dbgc_mcutracectl_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DCU_TypeDef {
    pub CTL_b: stc_dcu_ctl_bit_t,
    pub FLAG_b: stc_dcu_flag_bit_t,
    pub RESERVED0: [u32; 96usize],
    pub FLAGCLR_b: stc_dcu_flagclr_bit_t,
    pub INTEVTSEL_b: stc_dcu_intevtsel_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DMA_TypeDef {
    pub EN_b: stc_dma_en_bit_t,
    pub INTSTAT0_b: stc_dma_intstat0_bit_t,
    pub INTSTAT1_b: stc_dma_intstat1_bit_t,
    pub INTMASK0_b: stc_dma_intmask0_bit_t,
    pub INTMASK1_b: stc_dma_intmask1_bit_t,
    pub INTCLR0_b: stc_dma_intclr0_bit_t,
    pub INTCLR1_b: stc_dma_intclr1_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub REQSTAT_b: stc_dma_reqstat_bit_t,
    pub CHSTAT_b: stc_dma_chstat_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub RCFGCTL_b: stc_dma_rcfgctl_bit_t,
    pub SWREQ_b: stc_dma_swreq_bit_t,
    pub RESERVED2: [u32; 320usize],
    pub CHCTL0_b: stc_dma_chctl_bit_t,
    pub RESERVED3: [u32; 480usize],
    pub CHCTL1_b: stc_dma_chctl_bit_t,
    pub RESERVED4: [u32; 480usize],
    pub CHCTL2_b: stc_dma_chctl_bit_t,
    pub RESERVED5: [u32; 480usize],
    pub CHCTL3_b: stc_dma_chctl_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_EFM_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub FSTP_b: stc_efm_fstp_bit_t,
    pub FRMC_b: stc_efm_frmc_bit_t,
    pub FWMC_b: stc_efm_fwmc_bit_t,
    pub FSR_b: stc_efm_fsr_bit_t,
    pub FSCLR_b: stc_efm_fsclr_bit_t,
    pub FITE_b: stc_efm_fite_bit_t,
    pub FSWP_b: stc_efm_fswp_bit_t,
    pub RESERVED1: [u32; 1824usize],
    pub MMF_REMCR0_b: stc_efm_mmf_remcr_bit_t,
    pub MMF_REMCR1_b: stc_efm_mmf_remcr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_EMB_TypeDef {
    pub CTL_b: stc_emb_ctl_bit_t,
    pub PWMLV_b: stc_emb_pwmlv_bit_t,
    pub SOE_b: stc_emb_soe_bit_t,
    pub STAT_b: stc_emb_stat_bit_t,
    pub STATCLR_b: stc_emb_statclr_bit_t,
    pub INTEN_b: stc_emb_inten_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_FCM_TypeDef {
    pub RESERVED0: [u32; 96usize],
    pub STR_b: stc_fcm_str_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub RCCR_b: stc_fcm_rccr_bit_t,
    pub RIER_b: stc_fcm_rier_bit_t,
    pub SR_b: stc_fcm_sr_bit_t,
    pub CLR_b: stc_fcm_clr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_GPIO_TypeDef {
    pub PIDRA_b: stc_gpio_pidr_bit_t,
    pub RESERVED0: [u32; 16usize],
    pub PODRA_b: stc_gpio_podr_bit_t,
    pub POERA_b: stc_gpio_poer_bit_t,
    pub POSRA_b: stc_gpio_posr_bit_t,
    pub PORRA_b: stc_gpio_porr_bit_t,
    pub POTRA_b: stc_gpio_potr_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub PIDRB_b: stc_gpio_pidr_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub PODRB_b: stc_gpio_podr_bit_t,
    pub POERB_b: stc_gpio_poer_bit_t,
    pub POSRB_b: stc_gpio_posr_bit_t,
    pub PORRB_b: stc_gpio_porr_bit_t,
    pub POTRB_b: stc_gpio_potr_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub PIDRC_b: stc_gpio_pidr_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub PODRC_b: stc_gpio_podr_bit_t,
    pub POERC_b: stc_gpio_poer_bit_t,
    pub POSRC_b: stc_gpio_posr_bit_t,
    pub PORRC_b: stc_gpio_porr_bit_t,
    pub POTRC_b: stc_gpio_potr_bit_t,
    pub RESERVED5: [u32; 16usize],
    pub PIDRD_b: stc_gpio_pidr_bit_t,
    pub RESERVED6: [u32; 16usize],
    pub PODRD_b: stc_gpio_podr_bit_t,
    pub POERD_b: stc_gpio_poer_bit_t,
    pub POSRD_b: stc_gpio_posr_bit_t,
    pub PORRD_b: stc_gpio_porr_bit_t,
    pub POTRD_b: stc_gpio_potr_bit_t,
    pub RESERVED7: [u32; 16usize],
    pub PIDRE_b: stc_gpio_pidr_bit_t,
    pub RESERVED8: [u32; 16usize],
    pub PODRE_b: stc_gpio_podr_bit_t,
    pub POERE_b: stc_gpio_poer_bit_t,
    pub POSRE_b: stc_gpio_posr_bit_t,
    pub PORRE_b: stc_gpio_porr_bit_t,
    pub POTRE_b: stc_gpio_potr_bit_t,
    pub RESERVED9: [u32; 16usize],
    pub PIDRH_b: stc_gpio_pidrh_bit_t,
    pub RESERVED10: [u32; 16usize],
    pub PODRH_b: stc_gpio_podrh_bit_t,
    pub POERH_b: stc_gpio_poerh_bit_t,
    pub POSRH_b: stc_gpio_posrh_bit_t,
    pub PORRH_b: stc_gpio_porrh_bit_t,
    pub POTRH_b: stc_gpio_potrh_bit_t,
    pub RESERVED11: [u32; 7408usize],
    pub PWPR_b: stc_gpio_pwpr_bit_t,
    pub RESERVED12: [u32; 16usize],
    pub PCRA0_b: stc_gpio_pcr_bit_t,
    pub PFSRA0_b: stc_gpio_pfsr_bit_t,
    pub PCRA1_b: stc_gpio_pcr_bit_t,
    pub PFSRA1_b: stc_gpio_pfsr_bit_t,
    pub PCRA2_b: stc_gpio_pcr_bit_t,
    pub PFSRA2_b: stc_gpio_pfsr_bit_t,
    pub PCRA3_b: stc_gpio_pcr_bit_t,
    pub PFSRA3_b: stc_gpio_pfsr_bit_t,
    pub PCRA4_b: stc_gpio_pcr_bit_t,
    pub PFSRA4_b: stc_gpio_pfsr_bit_t,
    pub PCRA5_b: stc_gpio_pcr_bit_t,
    pub PFSRA5_b: stc_gpio_pfsr_bit_t,
    pub PCRA6_b: stc_gpio_pcr_bit_t,
    pub PFSRA6_b: stc_gpio_pfsr_bit_t,
    pub PCRA7_b: stc_gpio_pcr_bit_t,
    pub PFSRA7_b: stc_gpio_pfsr_bit_t,
    pub PCRA8_b: stc_gpio_pcr_bit_t,
    pub PFSRA8_b: stc_gpio_pfsr_bit_t,
    pub PCRA9_b: stc_gpio_pcr_bit_t,
    pub PFSRA9_b: stc_gpio_pfsr_bit_t,
    pub PCRA10_b: stc_gpio_pcr_bit_t,
    pub PFSRA10_b: stc_gpio_pfsr_bit_t,
    pub PCRA11_b: stc_gpio_pcr_bit_t,
    pub PFSRA11_b: stc_gpio_pfsr_bit_t,
    pub PCRA12_b: stc_gpio_pcr_bit_t,
    pub PFSRA12_b: stc_gpio_pfsr_bit_t,
    pub PCRA13_b: stc_gpio_pcr_bit_t,
    pub PFSRA13_b: stc_gpio_pfsr_bit_t,
    pub PCRA14_b: stc_gpio_pcr_bit_t,
    pub PFSRA14_b: stc_gpio_pfsr_bit_t,
    pub PCRA15_b: stc_gpio_pcr_bit_t,
    pub PFSRA15_b: stc_gpio_pfsr_bit_t,
    pub PCRB0_b: stc_gpio_pcr_bit_t,
    pub PFSRB0_b: stc_gpio_pfsr_bit_t,
    pub PCRB1_b: stc_gpio_pcr_bit_t,
    pub PFSRB1_b: stc_gpio_pfsr_bit_t,
    pub PCRB2_b: stc_gpio_pcr_bit_t,
    pub PFSRB2_b: stc_gpio_pfsr_bit_t,
    pub PCRB3_b: stc_gpio_pcr_bit_t,
    pub PFSRB3_b: stc_gpio_pfsr_bit_t,
    pub PCRB4_b: stc_gpio_pcr_bit_t,
    pub PFSRB4_b: stc_gpio_pfsr_bit_t,
    pub PCRB5_b: stc_gpio_pcr_bit_t,
    pub PFSRB5_b: stc_gpio_pfsr_bit_t,
    pub PCRB6_b: stc_gpio_pcr_bit_t,
    pub PFSRB6_b: stc_gpio_pfsr_bit_t,
    pub PCRB7_b: stc_gpio_pcr_bit_t,
    pub PFSRB7_b: stc_gpio_pfsr_bit_t,
    pub PCRB8_b: stc_gpio_pcr_bit_t,
    pub PFSRB8_b: stc_gpio_pfsr_bit_t,
    pub PCRB9_b: stc_gpio_pcr_bit_t,
    pub PFSRB9_b: stc_gpio_pfsr_bit_t,
    pub PCRB10_b: stc_gpio_pcr_bit_t,
    pub PFSRB10_b: stc_gpio_pfsr_bit_t,
    pub PCRB11_b: stc_gpio_pcr_bit_t,
    pub PFSRB11_b: stc_gpio_pfsr_bit_t,
    pub PCRB12_b: stc_gpio_pcr_bit_t,
    pub PFSRB12_b: stc_gpio_pfsr_bit_t,
    pub PCRB13_b: stc_gpio_pcr_bit_t,
    pub PFSRB13_b: stc_gpio_pfsr_bit_t,
    pub PCRB14_b: stc_gpio_pcr_bit_t,
    pub PFSRB14_b: stc_gpio_pfsr_bit_t,
    pub PCRB15_b: stc_gpio_pcr_bit_t,
    pub PFSRB15_b: stc_gpio_pfsr_bit_t,
    pub PCRC0_b: stc_gpio_pcr_bit_t,
    pub PFSRC0_b: stc_gpio_pfsr_bit_t,
    pub PCRC1_b: stc_gpio_pcr_bit_t,
    pub PFSRC1_b: stc_gpio_pfsr_bit_t,
    pub PCRC2_b: stc_gpio_pcr_bit_t,
    pub PFSRC2_b: stc_gpio_pfsr_bit_t,
    pub PCRC3_b: stc_gpio_pcr_bit_t,
    pub PFSRC3_b: stc_gpio_pfsr_bit_t,
    pub PCRC4_b: stc_gpio_pcr_bit_t,
    pub PFSRC4_b: stc_gpio_pfsr_bit_t,
    pub PCRC5_b: stc_gpio_pcr_bit_t,
    pub PFSRC5_b: stc_gpio_pfsr_bit_t,
    pub PCRC6_b: stc_gpio_pcr_bit_t,
    pub PFSRC6_b: stc_gpio_pfsr_bit_t,
    pub PCRC7_b: stc_gpio_pcr_bit_t,
    pub PFSRC7_b: stc_gpio_pfsr_bit_t,
    pub PCRC8_b: stc_gpio_pcr_bit_t,
    pub PFSRC8_b: stc_gpio_pfsr_bit_t,
    pub PCRC9_b: stc_gpio_pcr_bit_t,
    pub PFSRC9_b: stc_gpio_pfsr_bit_t,
    pub PCRC10_b: stc_gpio_pcr_bit_t,
    pub PFSRC10_b: stc_gpio_pfsr_bit_t,
    pub PCRC11_b: stc_gpio_pcr_bit_t,
    pub PFSRC11_b: stc_gpio_pfsr_bit_t,
    pub PCRC12_b: stc_gpio_pcr_bit_t,
    pub PFSRC12_b: stc_gpio_pfsr_bit_t,
    pub PCRC13_b: stc_gpio_pcr_bit_t,
    pub PFSRC13_b: stc_gpio_pfsr_bit_t,
    pub PCRC14_b: stc_gpio_pcr_bit_t,
    pub PFSRC14_b: stc_gpio_pfsr_bit_t,
    pub PCRC15_b: stc_gpio_pcr_bit_t,
    pub PFSRC15_b: stc_gpio_pfsr_bit_t,
    pub PCRD0_b: stc_gpio_pcr_bit_t,
    pub PFSRD0_b: stc_gpio_pfsr_bit_t,
    pub PCRD1_b: stc_gpio_pcr_bit_t,
    pub PFSRD1_b: stc_gpio_pfsr_bit_t,
    pub PCRD2_b: stc_gpio_pcr_bit_t,
    pub PFSRD2_b: stc_gpio_pfsr_bit_t,
    pub PCRD3_b: stc_gpio_pcr_bit_t,
    pub PFSRD3_b: stc_gpio_pfsr_bit_t,
    pub PCRD4_b: stc_gpio_pcr_bit_t,
    pub PFSRD4_b: stc_gpio_pfsr_bit_t,
    pub PCRD5_b: stc_gpio_pcr_bit_t,
    pub PFSRD5_b: stc_gpio_pfsr_bit_t,
    pub PCRD6_b: stc_gpio_pcr_bit_t,
    pub PFSRD6_b: stc_gpio_pfsr_bit_t,
    pub PCRD7_b: stc_gpio_pcr_bit_t,
    pub PFSRD7_b: stc_gpio_pfsr_bit_t,
    pub PCRD8_b: stc_gpio_pcr_bit_t,
    pub PFSRD8_b: stc_gpio_pfsr_bit_t,
    pub PCRD9_b: stc_gpio_pcr_bit_t,
    pub PFSRD9_b: stc_gpio_pfsr_bit_t,
    pub PCRD10_b: stc_gpio_pcr_bit_t,
    pub PFSRD10_b: stc_gpio_pfsr_bit_t,
    pub PCRD11_b: stc_gpio_pcr_bit_t,
    pub PFSRD11_b: stc_gpio_pfsr_bit_t,
    pub PCRD12_b: stc_gpio_pcr_bit_t,
    pub PFSRD12_b: stc_gpio_pfsr_bit_t,
    pub PCRD13_b: stc_gpio_pcr_bit_t,
    pub PFSRD13_b: stc_gpio_pfsr_bit_t,
    pub PCRD14_b: stc_gpio_pcr_bit_t,
    pub PFSRD14_b: stc_gpio_pfsr_bit_t,
    pub PCRD15_b: stc_gpio_pcr_bit_t,
    pub PFSRD15_b: stc_gpio_pfsr_bit_t,
    pub PCRE0_b: stc_gpio_pcr_bit_t,
    pub PFSRE0_b: stc_gpio_pfsr_bit_t,
    pub PCRE1_b: stc_gpio_pcr_bit_t,
    pub PFSRE1_b: stc_gpio_pfsr_bit_t,
    pub PCRE2_b: stc_gpio_pcr_bit_t,
    pub PFSRE2_b: stc_gpio_pfsr_bit_t,
    pub PCRE3_b: stc_gpio_pcr_bit_t,
    pub PFSRE3_b: stc_gpio_pfsr_bit_t,
    pub PCRE4_b: stc_gpio_pcr_bit_t,
    pub PFSRE4_b: stc_gpio_pfsr_bit_t,
    pub PCRE5_b: stc_gpio_pcr_bit_t,
    pub PFSRE5_b: stc_gpio_pfsr_bit_t,
    pub PCRE6_b: stc_gpio_pcr_bit_t,
    pub PFSRE6_b: stc_gpio_pfsr_bit_t,
    pub PCRE7_b: stc_gpio_pcr_bit_t,
    pub PFSRE7_b: stc_gpio_pfsr_bit_t,
    pub PCRE8_b: stc_gpio_pcr_bit_t,
    pub PFSRE8_b: stc_gpio_pfsr_bit_t,
    pub PCRE9_b: stc_gpio_pcr_bit_t,
    pub PFSRE9_b: stc_gpio_pfsr_bit_t,
    pub PCRE10_b: stc_gpio_pcr_bit_t,
    pub PFSRE10_b: stc_gpio_pfsr_bit_t,
    pub PCRE11_b: stc_gpio_pcr_bit_t,
    pub PFSRE11_b: stc_gpio_pfsr_bit_t,
    pub PCRE12_b: stc_gpio_pcr_bit_t,
    pub PFSRE12_b: stc_gpio_pfsr_bit_t,
    pub PCRE13_b: stc_gpio_pcr_bit_t,
    pub PFSRE13_b: stc_gpio_pfsr_bit_t,
    pub PCRE14_b: stc_gpio_pcr_bit_t,
    pub PFSRE14_b: stc_gpio_pfsr_bit_t,
    pub PCRE15_b: stc_gpio_pcr_bit_t,
    pub PFSRE15_b: stc_gpio_pfsr_bit_t,
    pub PCRH0_b: stc_gpio_pcr_bit_t,
    pub PFSRH0_b: stc_gpio_pfsr_bit_t,
    pub PCRH1_b: stc_gpio_pcr_bit_t,
    pub PFSRH1_b: stc_gpio_pfsr_bit_t,
    pub PCRH2_b: stc_gpio_pcr_bit_t,
    pub PFSRH2_b: stc_gpio_pfsr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_HASH_TypeDef {
    pub CR_b: stc_hash_cr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_I2C_TypeDef {
    pub CR1_b: stc_i2c_cr1_bit_t,
    pub CR2_b: stc_i2c_cr2_bit_t,
    pub CR3_b: stc_i2c_cr3_bit_t,
    pub CR4_b: stc_i2c_cr4_bit_t,
    pub SLR0_b: stc_i2c_slr0_bit_t,
    pub SLR1_b: stc_i2c_slr1_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub SR_b: stc_i2c_sr_bit_t,
    pub CLR_b: stc_i2c_clr_bit_t,
    pub RESERVED1: [u32; 96usize],
    pub FLTR_b: stc_i2c_fltr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_I2S_TypeDef {
    pub CTRL_b: stc_i2s_ctrl_bit_t,
    pub SR_b: stc_i2s_sr_bit_t,
    pub ER_b: stc_i2s_er_bit_t,
    pub CFGR_b: stc_i2s_cfgr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_ICG_TypeDef {
    pub ICG0_b: stc_icg_icg0_bit_t,
    pub ICG1_b: stc_icg_icg1_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_INTC_TypeDef {
    pub NMICR_b: stc_intc_nmicr_bit_t,
    pub NMIENR_b: stc_intc_nmienr_bit_t,
    pub NMIFR_b: stc_intc_nmifr_bit_t,
    pub NMICFR_b: stc_intc_nmicfr_bit_t,
    pub EIRQCR0_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR1_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR2_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR3_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR4_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR5_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR6_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR7_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR8_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR9_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR10_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR11_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR12_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR13_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR14_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR15_b: stc_intc_eirqcr_bit_t,
    pub WUPEN_b: stc_intc_wupen_bit_t,
    pub EIFR_b: stc_intc_eifr_bit_t,
    pub EIFCR_b: stc_intc_eifcr_bit_t,
    pub RESERVED0: [u32; 4096usize],
    pub VSSEL128_b: stc_intc_vssel_bit_t,
    pub VSSEL129_b: stc_intc_vssel_bit_t,
    pub VSSEL130_b: stc_intc_vssel_bit_t,
    pub VSSEL131_b: stc_intc_vssel_bit_t,
    pub VSSEL132_b: stc_intc_vssel_bit_t,
    pub VSSEL133_b: stc_intc_vssel_bit_t,
    pub VSSEL134_b: stc_intc_vssel_bit_t,
    pub VSSEL135_b: stc_intc_vssel_bit_t,
    pub VSSEL136_b: stc_intc_vssel_bit_t,
    pub VSSEL137_b: stc_intc_vssel_bit_t,
    pub VSSEL138_b: stc_intc_vssel_bit_t,
    pub VSSEL139_b: stc_intc_vssel_bit_t,
    pub VSSEL140_b: stc_intc_vssel_bit_t,
    pub VSSEL141_b: stc_intc_vssel_bit_t,
    pub VSSEL142_b: stc_intc_vssel_bit_t,
    pub VSSEL143_b: stc_intc_vssel_bit_t,
    pub SWIER_b: stc_intc_swier_bit_t,
    pub EVTER_b: stc_intc_evter_bit_t,
    pub IER_b: stc_intc_ier_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_KEYSCAN_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub SER_b: stc_keyscan_ser_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_MPU_TypeDef {
    pub RESERVED0: [u32; 512usize],
    pub RGCR0_b: stc_mpu_rgcr_bit_t,
    pub RGCR1_b: stc_mpu_rgcr_bit_t,
    pub RGCR2_b: stc_mpu_rgcr_bit_t,
    pub RGCR3_b: stc_mpu_rgcr_bit_t,
    pub RGCR4_b: stc_mpu_rgcr_bit_t,
    pub RGCR5_b: stc_mpu_rgcr_bit_t,
    pub RGCR6_b: stc_mpu_rgcr_bit_t,
    pub RGCR7_b: stc_mpu_rgcr_bit_t,
    pub RGCR8_b: stc_mpu_rgcr_bit_t,
    pub RGCR9_b: stc_mpu_rgcr_bit_t,
    pub RGCR10_b: stc_mpu_rgcr_bit_t,
    pub RGCR11_b: stc_mpu_rgcr_bit_t,
    pub RGCR12_b: stc_mpu_rgcr_bit_t,
    pub RGCR13_b: stc_mpu_rgcr_bit_t,
    pub RGCR14_b: stc_mpu_rgcr_bit_t,
    pub RGCR15_b: stc_mpu_rgcr_bit_t,
    pub CR_b: stc_mpu_cr_bit_t,
    pub SR_b: stc_mpu_sr_bit_t,
    pub ECLR_b: stc_mpu_eclr_bit_t,
    pub WP_b: stc_mpu_wp_bit_t,
    pub RESERVED1: [u32; 130144usize],
    pub IPPR_b: stc_mpu_ippr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_OTS_TypeDef {
    pub CTL_b: stc_ots_ctl_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_PERIC_TypeDef {
    pub USBFS_SYCTLREG_b: stc_peric_usbfs_syctlreg_bit_t,
    pub SDIOC_SYCTLREG_b: stc_peric_sdioc_syctlreg_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_QSPI_TypeDef {
    pub CR_b: stc_qspi_cr_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub FCR_b: stc_qspi_fcr_bit_t,
    pub SR_b: stc_qspi_sr_bit_t,
    pub RESERVED1: [u32; 160usize],
    pub CLR_b: stc_qspi_clr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_RMU_TypeDef {
    pub RSTF0_b: stc_rmu_rstf0_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_RTC_TypeDef {
    pub CR0_b: stc_rtc_cr0_bit_t,
    pub RESERVED0: [u32; 24usize],
    pub CR1_b: stc_rtc_cr1_bit_t,
    pub RESERVED1: [u32; 24usize],
    pub CR2_b: stc_rtc_cr2_bit_t,
    pub RESERVED2: [u32; 24usize],
    pub CR3_b: stc_rtc_cr3_bit_t,
    pub RESERVED3: [u32; 344usize],
    pub ERRCRH_b: stc_rtc_errcrh_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SDIOC_TypeDef {
    pub RESERVED0: [u32; 96usize],
    pub TRANSMODE_b: stc_sdioc_transmode_bit_t,
    pub CMD_b: stc_sdioc_cmd_bit_t,
    pub RESERVED1: [u32; 160usize],
    pub PSTAT_b: stc_sdioc_pstat_bit_t,
    pub HOSTCON_b: stc_sdioc_hostcon_bit_t,
    pub PWRCON_b: stc_sdioc_pwrcon_bit_t,
    pub BLKGPCON_b: stc_sdioc_blkgpcon_bit_t,
    pub RESERVED2: [u32; 8usize],
    pub CLKCON_b: stc_sdioc_clkcon_bit_t,
    pub RESERVED3: [u32; 8usize],
    pub SFTRST_b: stc_sdioc_sftrst_bit_t,
    pub NORINTST_b: stc_sdioc_norintst_bit_t,
    pub ERRINTST_b: stc_sdioc_errintst_bit_t,
    pub NORINTSTEN_b: stc_sdioc_norintsten_bit_t,
    pub ERRINTSTEN_b: stc_sdioc_errintsten_bit_t,
    pub NORINTSGEN_b: stc_sdioc_norintsgen_bit_t,
    pub ERRINTSGEN_b: stc_sdioc_errintsgen_bit_t,
    pub ATCERRST_b: stc_sdioc_atcerrst_bit_t,
    pub RESERVED4: [u32; 144usize],
    pub FEA_b: stc_sdioc_fea_bit_t,
    pub FEE_b: stc_sdioc_fee_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SPI_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub CR1_b: stc_spi_cr1_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub CFG1_b: stc_spi_cfg1_bit_t,
    pub RESERVED2: [u32; 32usize],
    pub SR_b: stc_spi_sr_bit_t,
    pub CFG2_b: stc_spi_cfg2_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SRAMC_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub WTPR_b: stc_sramc_wtpr_bit_t,
    pub CKCR_b: stc_sramc_ckcr_bit_t,
    pub CKPR_b: stc_sramc_ckpr_bit_t,
    pub CKSR_b: stc_sramc_cksr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SWDT_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub SR_b: stc_swdt_sr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR0_TypeDef {
    pub RESERVED0: [u32; 128usize],
    pub BCONR_b: stc_tmr0_bconr_bit_t,
    pub STFLR_b: stc_tmr0_stflr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR4_TypeDef {
    pub RESERVED0: [u32; 192usize],
    pub OCSRU_b: stc_tmr4_ocsr_bit_t,
    pub OCERU_b: stc_tmr4_ocer_bit_t,
    pub OCSRV_b: stc_tmr4_ocsr_bit_t,
    pub OCERV_b: stc_tmr4_ocer_bit_t,
    pub OCSRW_b: stc_tmr4_ocsr_bit_t,
    pub OCERW_b: stc_tmr4_ocer_bit_t,
    pub OCMRUH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub OCMRUL_b: stc_tmr4_ocmrl_bit_t,
    pub OCMRVH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub OCMRVL_b: stc_tmr4_ocmrl_bit_t,
    pub OCMRWH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub OCMRWL_b: stc_tmr4_ocmrl_bit_t,
    pub RESERVED4: [u32; 96usize],
    pub CCSR_b: stc_tmr4_ccsr_bit_t,
    pub RESERVED5: [u32; 720usize],
    pub RCSR_b: stc_tmr4_rcsr_bit_t,
    pub RESERVED6: [u32; 272usize],
    pub SCSRUH_b: stc_tmr4_scsr_bit_t,
    pub SCMRUH_b: stc_tmr4_scmr_bit_t,
    pub SCSRUL_b: stc_tmr4_scsr_bit_t,
    pub SCMRUL_b: stc_tmr4_scmr_bit_t,
    pub SCSRVH_b: stc_tmr4_scsr_bit_t,
    pub SCMRVH_b: stc_tmr4_scmr_bit_t,
    pub SCSRVL_b: stc_tmr4_scsr_bit_t,
    pub SCMRVL_b: stc_tmr4_scmr_bit_t,
    pub SCSRWH_b: stc_tmr4_scsr_bit_t,
    pub SCMRWH_b: stc_tmr4_scmr_bit_t,
    pub SCSRWL_b: stc_tmr4_scsr_bit_t,
    pub SCMRWL_b: stc_tmr4_scmr_bit_t,
    pub RESERVED7: [u32; 128usize],
    pub ECSR_b: stc_tmr4_ecsr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR6_TypeDef {
    pub RESERVED0: [u32; 640usize],
    pub GCONR_b: stc_tmr6_gconr_bit_t,
    pub ICONR_b: stc_tmr6_iconr_bit_t,
    pub PCONR_b: stc_tmr6_pconr_bit_t,
    pub BCONR_b: stc_tmr6_bconr_bit_t,
    pub DCONR_b: stc_tmr6_dconr_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub FCONR_b: stc_tmr6_fconr_bit_t,
    pub VPERR_b: stc_tmr6_vperr_bit_t,
    pub STFLR_b: stc_tmr6_stflr_bit_t,
    pub HSTAR_b: stc_tmr6_hstar_bit_t,
    pub HSTPR_b: stc_tmr6_hstpr_bit_t,
    pub HCLRR_b: stc_tmr6_hclrr_bit_t,
    pub HCPAR_b: stc_tmr6_hcpar_bit_t,
    pub HCPBR_b: stc_tmr6_hcpbr_bit_t,
    pub HCUPR_b: stc_tmr6_hcupr_bit_t,
    pub HCDOR_b: stc_tmr6_hcdor_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR6_COMMON_TypeDef {
    pub RESERVED0: [u32; 1952usize],
    pub SSTAR_b: stc_tmr6_common_sstar_bit_t,
    pub SSTPR_b: stc_tmr6_common_sstpr_bit_t,
    pub SCLRR_b: stc_tmr6_common_sclrr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMRA_TypeDef {
    pub RESERVED0: [u32; 1024usize],
    pub BCSTRL_b: stc_tmra_bcstrl_bit_t,
    pub BCSTRH_b: stc_tmra_bcstrh_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub HCONR_b: stc_tmra_hconr_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub HCUPR_b: stc_tmra_hcupr_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub HCDOR_b: stc_tmra_hcdor_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub ICONR_b: stc_tmra_iconr_bit_t,
    pub RESERVED5: [u32; 16usize],
    pub ECONR_b: stc_tmra_econr_bit_t,
    pub RESERVED6: [u32; 16usize],
    pub FCONR_b: stc_tmra_fconr_bit_t,
    pub RESERVED7: [u32; 16usize],
    pub STFLR_b: stc_tmra_stflr_bit_t,
    pub RESERVED8: [u32; 272usize],
    pub BCONR1_b: stc_tmra_bconr_bit_t,
    pub RESERVED9: [u32; 48usize],
    pub BCONR2_b: stc_tmra_bconr_bit_t,
    pub RESERVED10: [u32; 48usize],
    pub BCONR3_b: stc_tmra_bconr_bit_t,
    pub RESERVED11: [u32; 48usize],
    pub BCONR4_b: stc_tmra_bconr_bit_t,
    pub RESERVED12: [u32; 304usize],
    pub CCONR1_b: stc_tmra_cconr_bit_t,
    pub RESERVED13: [u32; 16usize],
    pub CCONR2_b: stc_tmra_cconr_bit_t,
    pub RESERVED14: [u32; 16usize],
    pub CCONR3_b: stc_tmra_cconr_bit_t,
    pub RESERVED15: [u32; 16usize],
    pub CCONR4_b: stc_tmra_cconr_bit_t,
    pub RESERVED16: [u32; 16usize],
    pub CCONR5_b: stc_tmra_cconr_bit_t,
    pub RESERVED17: [u32; 16usize],
    pub CCONR6_b: stc_tmra_cconr_bit_t,
    pub RESERVED18: [u32; 16usize],
    pub CCONR7_b: stc_tmra_cconr_bit_t,
    pub RESERVED19: [u32; 16usize],
    pub CCONR8_b: stc_tmra_cconr_bit_t,
    pub RESERVED20: [u32; 272usize],
    pub PCONR1_b: stc_tmra_pconr_bit_t,
    pub RESERVED21: [u32; 16usize],
    pub PCONR2_b: stc_tmra_pconr_bit_t,
    pub RESERVED22: [u32; 16usize],
    pub PCONR3_b: stc_tmra_pconr_bit_t,
    pub RESERVED23: [u32; 16usize],
    pub PCONR4_b: stc_tmra_pconr_bit_t,
    pub RESERVED24: [u32; 16usize],
    pub PCONR5_b: stc_tmra_pconr_bit_t,
    pub RESERVED25: [u32; 16usize],
    pub PCONR6_b: stc_tmra_pconr_bit_t,
    pub RESERVED26: [u32; 16usize],
    pub PCONR7_b: stc_tmra_pconr_bit_t,
    pub RESERVED27: [u32; 16usize],
    pub PCONR8_b: stc_tmra_pconr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TRNG_TypeDef {
    pub CR_b: stc_trng_cr_bit_t,
    pub MR_b: stc_trng_mr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_USART_TypeDef {
    pub SR_b: stc_usart_sr_bit_t,
    pub TDR_b: stc_usart_tdr_bit_t,
    pub RESERVED0: [u32; 48usize],
    pub CR1_b: stc_usart_cr1_bit_t,
    pub CR2_b: stc_usart_cr2_bit_t,
    pub CR3_b: stc_usart_cr3_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_USBFS_TypeDef {
    pub GVBUSCFG_b: stc_usbfs_gvbuscfg_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub GAHBCFG_b: stc_usbfs_gahbcfg_bit_t,
    pub GUSBCFG_b: stc_usbfs_gusbcfg_bit_t,
    pub GRSTCTL_b: stc_usbfs_grstctl_bit_t,
    pub GINTSTS_b: stc_usbfs_gintsts_bit_t,
    pub GINTMSK_b: stc_usbfs_gintmsk_bit_t,
    pub RESERVED1: [u32; 7968usize],
    pub HCFG_b: stc_usbfs_hcfg_bit_t,
    pub RESERVED2: [u32; 480usize],
    pub HPRT_b: stc_usbfs_hprt_bit_t,
    pub RESERVED3: [u32; 1504usize],
    pub HCCHAR0_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED4: [u32; 32usize],
    pub HCINT0_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK0_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED5: [u32; 128usize],
    pub HCCHAR1_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED6: [u32; 32usize],
    pub HCINT1_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK1_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED7: [u32; 128usize],
    pub HCCHAR2_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED8: [u32; 32usize],
    pub HCINT2_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK2_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED9: [u32; 128usize],
    pub HCCHAR3_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED10: [u32; 32usize],
    pub HCINT3_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK3_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED11: [u32; 128usize],
    pub HCCHAR4_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED12: [u32; 32usize],
    pub HCINT4_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK4_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED13: [u32; 128usize],
    pub HCCHAR5_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED14: [u32; 32usize],
    pub HCINT5_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK5_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED15: [u32; 128usize],
    pub HCCHAR6_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED16: [u32; 32usize],
    pub HCINT6_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK6_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED17: [u32; 128usize],
    pub HCCHAR7_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED18: [u32; 32usize],
    pub HCINT7_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK7_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED19: [u32; 128usize],
    pub HCCHAR8_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED20: [u32; 32usize],
    pub HCINT8_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK8_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED21: [u32; 128usize],
    pub HCCHAR9_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED22: [u32; 32usize],
    pub HCINT9_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK9_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED23: [u32; 128usize],
    pub HCCHAR10_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED24: [u32; 32usize],
    pub HCINT10_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK10_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED25: [u32; 128usize],
    pub HCCHAR11_b: stc_usbfs_hcchar_bit_t,
    pub RESERVED26: [u32; 32usize],
    pub HCINT11_b: stc_usbfs_hcint_bit_t,
    pub HCINTMSK11_b: stc_usbfs_hcintmsk_bit_t,
    pub RESERVED27: [u32; 3200usize],
    pub DCFG_b: stc_usbfs_dcfg_bit_t,
    pub DCTL_b: stc_usbfs_dctl_bit_t,
    pub DSTS_b: stc_usbfs_dsts_bit_t,
    pub RESERVED28: [u32; 32usize],
    pub DIEPMSK_b: stc_usbfs_diepmsk_bit_t,
    pub DOEPMSK_b: stc_usbfs_doepmsk_bit_t,
    pub RESERVED29: [u32; 1856usize],
    pub DIEPCTL0_b: stc_usbfs_diepctl0_bit_t,
    pub RESERVED30: [u32; 32usize],
    pub DIEPINT0_b: stc_usbfs_diepint_bit_t,
    pub RESERVED31: [u32; 160usize],
    pub DIEPCTL1_b: stc_usbfs_diepctl_bit_t,
    pub RESERVED32: [u32; 32usize],
    pub DIEPINT1_b: stc_usbfs_diepint_bit_t,
    pub RESERVED33: [u32; 160usize],
    pub DIEPCTL2_b: stc_usbfs_diepctl_bit_t,
    pub RESERVED34: [u32; 32usize],
    pub DIEPINT2_b: stc_usbfs_diepint_bit_t,
    pub RESERVED35: [u32; 160usize],
    pub DIEPCTL3_b: stc_usbfs_diepctl_bit_t,
    pub RESERVED36: [u32; 32usize],
    pub DIEPINT3_b: stc_usbfs_diepint_bit_t,
    pub RESERVED37: [u32; 160usize],
    pub DIEPCTL4_b: stc_usbfs_diepctl_bit_t,
    pub RESERVED38: [u32; 32usize],
    pub DIEPINT4_b: stc_usbfs_diepint_bit_t,
    pub RESERVED39: [u32; 160usize],
    pub DIEPCTL5_b: stc_usbfs_diepctl_bit_t,
    pub RESERVED40: [u32; 32usize],
    pub DIEPINT5_b: stc_usbfs_diepint_bit_t,
    pub RESERVED41: [u32; 2720usize],
    pub DOEPCTL0_b: stc_usbfs_doepctl0_bit_t,
    pub RESERVED42: [u32; 32usize],
    pub DOEPINT0_b: stc_usbfs_doepint_bit_t,
    pub RESERVED43: [u32; 32usize],
    pub DOEPTSIZ0_b: stc_usbfs_doeptsiz0_bit_t,
    pub RESERVED44: [u32; 96usize],
    pub DOEPCTL1_b: stc_usbfs_doepctl_bit_t,
    pub RESERVED45: [u32; 32usize],
    pub DOEPINT1_b: stc_usbfs_doepint_bit_t,
    pub RESERVED46: [u32; 160usize],
    pub DOEPCTL2_b: stc_usbfs_doepctl_bit_t,
    pub RESERVED47: [u32; 32usize],
    pub DOEPINT2_b: stc_usbfs_doepint_bit_t,
    pub RESERVED48: [u32; 160usize],
    pub DOEPCTL3_b: stc_usbfs_doepctl_bit_t,
    pub RESERVED49: [u32; 32usize],
    pub DOEPINT3_b: stc_usbfs_doepint_bit_t,
    pub RESERVED50: [u32; 160usize],
    pub DOEPCTL4_b: stc_usbfs_doepctl_bit_t,
    pub RESERVED51: [u32; 32usize],
    pub DOEPINT4_b: stc_usbfs_doepint_bit_t,
    pub RESERVED52: [u32; 160usize],
    pub DOEPCTL5_b: stc_usbfs_doepctl_bit_t,
    pub RESERVED53: [u32; 32usize],
    pub DOEPINT5_b: stc_usbfs_doepint_bit_t,
    pub RESERVED54: [u32; 4768usize],
    pub GCCTL_b: stc_usbfs_gcctl_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_WDT_TypeDef {
    pub CR_b: stc_wdt_cr_bit_t,
    pub SR_b: stc_wdt_sr_bit_t,
}
unsafe extern "C" {
    #[doc = "< System clock frequency (Core clock)"]
    pub static mut SystemCoreClock: u32;
    #[doc = "< HRC frequency"]
    pub static mut HRC_VALUE: u32;
    #[doc = " Global function prototypes (definition in C source)\n/\n/**\n @addtogroup HC32F460_System_Global_Functions\n @{"]
    pub fn SystemInit();
    pub fn SystemCoreClockUpdate();
}