hc32f460_driver_sys 0.1.0

Provide driver function binding for HDSC's HC32F460 MCU.
Documentation
/* automatically generated by rust-bindgen 0.72.1 */

pub const SRAM_SRAMH: u32 = 4;
pub const SRAM_SRAM12: u32 = 1;
pub const SRAM_SRAM3: u32 = 2;
pub const SRAM_SRAMR: u32 = 8;
pub const SRAM_SRAM_ALL: u32 = 15;
pub const SRAM_ECC_SRAM3: u32 = 1;
pub const SRAM_ECC_SRAM_ALL: u32 = 1;
pub const SRAM_WAIT_CYCLE0: u32 = 0;
pub const SRAM_WAIT_CYCLE1: u32 = 1;
pub const SRAM_WAIT_CYCLE2: u32 = 2;
pub const SRAM_WAIT_CYCLE3: u32 = 3;
pub const SRAM_WAIT_CYCLE4: u32 = 4;
pub const SRAM_WAIT_CYCLE5: u32 = 5;
pub const SRAM_WAIT_CYCLE6: u32 = 6;
pub const SRAM_WAIT_CYCLE7: u32 = 7;
pub const SRAM_EXP_TYPE_NMI: u32 = 0;
pub const SRAM_EXP_TYPE_RST: u32 = 1;
pub const SRAM_CHECK_SRAM3: u32 = 65536;
pub const SRAM_CHECK_SRAMH_1_2_B: u32 = 1;
pub const SRAM_CHECK_SRAM_ALL: u32 = 65537;
pub const SRAM_SRAM3_ECC_INVD: u32 = 0;
pub const SRAM_SRAM3_ECC_MD1: u32 = 16777216;
pub const SRAM_SRAM3_ECC_MD2: u32 = 33554432;
pub const SRAM_SRAM3_ECC_MD3: u32 = 50331648;
pub const SRAM_ECC_MD_INVD: u32 = 0;
pub const SRAM_FLAG_SRAM3_1ERR: u32 = 1;
pub const SRAM_FLAG_SRAM3_2ERR: u32 = 2;
pub const SRAM_FLAG_SRAM12_PYERR: u32 = 4;
pub const SRAM_FLAG_SRAMH_PYERR: u32 = 8;
pub const SRAM_FLAG_SRAMR_PYERR: u32 = 16;
pub const SRAM_FLAG_ALL: u32 = 31;
pub const SRAM_REG_LOCK_KEY: u32 = 118;
pub const SRAM_REG_UNLOCK_KEY: u32 = 119;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
unsafe extern "C" {
    pub fn SRAM_Init();
    pub fn SRAM_DeInit();
    pub fn SRAM_SetWaitCycle(u32SramSel: u32, u32WriteCycle: u32, u32ReadCycle: u32);
    pub fn SRAM_SetEccMode(u32EccSram: u32, u32EccMode: u32);
    pub fn SRAM_SetExceptionType(u32CheckSram: u32, u32ExceptionType: u32);
    pub fn SRAM_GetStatus(u32Flag: u32) -> en_flag_status_t;
    pub fn SRAM_ClearStatus(u32Flag: u32);
}