pub const DMA_CH0: u32 = 0;
pub const DMA_CH1: u32 = 1;
pub const DMA_CH2: u32 = 2;
pub const DMA_CH3: u32 = 3;
pub const DMA_MX_CH0: u32 = 1;
pub const DMA_MX_CH1: u32 = 2;
pub const DMA_MX_CH2: u32 = 4;
pub const DMA_MX_CH3: u32 = 8;
pub const DMA_MX_CH_ALL: u32 = 15;
pub const DMA_FLAG_REQ_ERR_CH0: u32 = 65536;
pub const DMA_FLAG_REQ_ERR_CH1: u32 = 131072;
pub const DMA_FLAG_REQ_ERR_CH2: u32 = 262144;
pub const DMA_FLAG_REQ_ERR_CH3: u32 = 524288;
pub const DMA_FLAG_TRANS_ERR_CH0: u32 = 1;
pub const DMA_FLAG_TRANS_ERR_CH1: u32 = 2;
pub const DMA_FLAG_TRANS_ERR_CH2: u32 = 4;
pub const DMA_FLAG_TRANS_ERR_CH3: u32 = 8;
pub const DMA_FLAG_BTC_CH0: u32 = 65536;
pub const DMA_FLAG_BTC_CH1: u32 = 131072;
pub const DMA_FLAG_BTC_CH2: u32 = 262144;
pub const DMA_FLAG_BTC_CH3: u32 = 524288;
pub const DMA_FLAG_TC_CH0: u32 = 1;
pub const DMA_FLAG_TC_CH1: u32 = 2;
pub const DMA_FLAG_TC_CH2: u32 = 4;
pub const DMA_FLAG_TC_CH3: u32 = 8;
pub const DMA_INT_REQ_ERR_CH0: u32 = 65536;
pub const DMA_INT_REQ_ERR_CH1: u32 = 131072;
pub const DMA_INT_REQ_ERR_CH2: u32 = 262144;
pub const DMA_INT_REQ_ERR_CH3: u32 = 524288;
pub const DMA_INT_TRANS_ERR_CH0: u32 = 1;
pub const DMA_INT_TRANS_ERR_CH1: u32 = 2;
pub const DMA_INT_TRANS_ERR_CH2: u32 = 4;
pub const DMA_INT_TRANS_ERR_CH3: u32 = 8;
pub const DMA_INT_BTC_CH0: u32 = 65536;
pub const DMA_INT_BTC_CH1: u32 = 131072;
pub const DMA_INT_BTC_CH2: u32 = 262144;
pub const DMA_INT_BTC_CH3: u32 = 524288;
pub const DMA_INT_TC_CH0: u32 = 1;
pub const DMA_INT_TC_CH1: u32 = 2;
pub const DMA_INT_TC_CH2: u32 = 4;
pub const DMA_INT_TC_CH3: u32 = 8;
pub const DMA_FLAG_ERR_MASK: u32 = 983055;
pub const DMA_FLAG_TRANS_MASK: u32 = 983055;
pub const DMA_INT_ERR_MASK: u32 = 983055;
pub const DMA_INT_TRANS_MASK: u32 = 983055;
pub const DMA_STAT_REQ_RECONFIG: u32 = 32768;
pub const DMA_STAT_REQ_CH0: u32 = 1;
pub const DMA_STAT_REQ_CH1: u32 = 2;
pub const DMA_STAT_REQ_CH2: u32 = 4;
pub const DMA_STAT_REQ_CH3: u32 = 8;
pub const DMA_STAT_REQ_MASK: u32 = 32783;
pub const DMA_STAT_TRANS_CH0: u32 = 65536;
pub const DMA_STAT_TRANS_CH1: u32 = 131072;
pub const DMA_STAT_TRANS_CH2: u32 = 262144;
pub const DMA_STAT_TRANS_CH3: u32 = 524288;
pub const DMA_STAT_TRANS_DMA: u32 = 1;
pub const DMA_STAT_TRANS_RECONFIG: u32 = 2;
pub const DMA_STAT_TRANS_MASK: u32 = 983043;
pub const DMA_DATAWIDTH_8BIT: u32 = 0;
pub const DMA_DATAWIDTH_16BIT: u32 = 256;
pub const DMA_DATAWIDTH_32BIT: u32 = 512;
pub const DMA_LLP_DISABLE: u32 = 0;
pub const DMA_LLP_ENABLE: u32 = 1024;
pub const DMA_LLP_WAIT: u32 = 0;
pub const DMA_LLP_RUN: u32 = 2048;
pub const DMA_SRC_ADDR_FIX: u32 = 0;
pub const DMA_SRC_ADDR_INC: u32 = 1;
pub const DMA_SRC_ADDR_DEC: u32 = 2;
pub const DMA_DEST_ADDR_FIX: u32 = 0;
pub const DMA_DEST_ADDR_INC: u32 = 4;
pub const DMA_DEST_ADDR_DEC: u32 = 8;
pub const DMA_INT_ENABLE: u32 = 4096;
pub const DMA_INT_DISABLE: u32 = 0;
pub const DMA_RPT_NONE: u32 = 0;
pub const DMA_RPT_SRC: u32 = 16;
pub const DMA_RPT_DEST: u32 = 32;
pub const DMA_RPT_BOTH: u32 = 48;
pub const DMA_NON_SEQ_NONE: u32 = 0;
pub const DMA_NON_SEQ_SRC: u32 = 64;
pub const DMA_NON_SEQ_DEST: u32 = 128;
pub const DMA_NON_SEQ_BOTH: u32 = 192;
pub const DMA_RC_CNT_KEEP: u32 = 0;
pub const DMA_RC_CNT_SRC: u32 = 1048576;
pub const DMA_RC_CNT_DEST: u32 = 2097152;
pub const DMA_RC_DEST_ADDR_KEEP: u32 = 0;
pub const DMA_RC_DEST_ADDR_NS: u32 = 262144;
pub const DMA_RC_DEST_ADDR_RPT: u32 = 524288;
pub const DMA_RC_SRC_ADDR_KEEP: u32 = 0;
pub const DMA_RC_SRC_ADDR_NS: u32 = 65536;
pub const DMA_RC_SRC_ADDR_RPT: u32 = 131072;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief DMA"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct CM_DMA_TypeDef {
pub EN: u32,
pub INTSTAT0: u32,
pub INTSTAT1: u32,
pub INTMASK0: u32,
pub INTMASK1: u32,
pub INTCLR0: u32,
pub INTCLR1: u32,
pub CHEN: u32,
pub REQSTAT: u32,
pub CHSTAT: u32,
pub RESERVED0: [u8; 4usize],
pub RCFGCTL: u32,
pub SWREQ: u32,
pub RESERVED1: [u8; 12usize],
pub SAR0: u32,
pub DAR0: u32,
pub DTCTL0: u32,
pub __bindgen_anon_1: CM_DMA_TypeDef__bindgen_ty_1,
pub __bindgen_anon_2: CM_DMA_TypeDef__bindgen_ty_2,
pub __bindgen_anon_3: CM_DMA_TypeDef__bindgen_ty_3,
pub LLP0: u32,
pub CHCTL0: u32,
pub MONSAR0: u32,
pub MONDAR0: u32,
pub MONDTCTL0: u32,
pub MONRPT0: u32,
pub MONSNSEQCTL0: u32,
pub MONDNSEQCTL0: u32,
pub RESERVED2: [u8; 8usize],
pub SAR1: u32,
pub DAR1: u32,
pub DTCTL1: u32,
pub __bindgen_anon_4: CM_DMA_TypeDef__bindgen_ty_4,
pub __bindgen_anon_5: CM_DMA_TypeDef__bindgen_ty_5,
pub __bindgen_anon_6: CM_DMA_TypeDef__bindgen_ty_6,
pub LLP1: u32,
pub CHCTL1: u32,
pub MONSAR1: u32,
pub MONDAR1: u32,
pub MONDTCTL1: u32,
pub MONRPT1: u32,
pub MONSNSEQCTL1: u32,
pub MONDNSEQCTL1: u32,
pub RESERVED3: [u8; 8usize],
pub SAR2: u32,
pub DAR2: u32,
pub DTCTL2: u32,
pub __bindgen_anon_7: CM_DMA_TypeDef__bindgen_ty_7,
pub __bindgen_anon_8: CM_DMA_TypeDef__bindgen_ty_8,
pub __bindgen_anon_9: CM_DMA_TypeDef__bindgen_ty_9,
pub LLP2: u32,
pub CHCTL2: u32,
pub MONSAR2: u32,
pub MONDAR2: u32,
pub MONDTCTL2: u32,
pub MONRPT2: u32,
pub MONSNSEQCTL2: u32,
pub MONDNSEQCTL2: u32,
pub RESERVED4: [u8; 8usize],
pub SAR3: u32,
pub DAR3: u32,
pub DTCTL3: u32,
pub __bindgen_anon_10: CM_DMA_TypeDef__bindgen_ty_10,
pub __bindgen_anon_11: CM_DMA_TypeDef__bindgen_ty_11,
pub __bindgen_anon_12: CM_DMA_TypeDef__bindgen_ty_12,
pub LLP3: u32,
pub CHCTL3: u32,
pub MONSAR3: u32,
pub MONDAR3: u32,
pub MONDTCTL3: u32,
pub MONRPT3: u32,
pub MONSNSEQCTL3: u32,
pub MONDNSEQCTL3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_1 {
pub RPT0: u32,
pub RPTB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_2 {
pub SNSEQCTL0: u32,
pub SNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_3 {
pub DNSEQCTL0: u32,
pub DNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_4 {
pub RPT1: u32,
pub RPTB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_5 {
pub SNSEQCTL1: u32,
pub SNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_6 {
pub DNSEQCTL1: u32,
pub DNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_7 {
pub RPT2: u32,
pub RPTB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_8 {
pub SNSEQCTL2: u32,
pub SNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_9 {
pub DNSEQCTL2: u32,
pub DNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_10 {
pub RPT3: u32,
pub RPTB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_11 {
pub SNSEQCTL3: u32,
pub SNSEQCTLB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_12 {
pub DNSEQCTL3: u32,
pub DNSEQCTLB3: u32,
}
#[doc = " @brief DMA basic configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_init_t {
#[doc = "< Specifies the DMA interrupt function.\nThis parameter can be a value of @ref DMA_Int_Config"]
pub u32IntEn: u32,
#[doc = "< Specifies the DMA source address."]
pub u32SrcAddr: u32,
#[doc = "< Specifies the DMA destination address."]
pub u32DestAddr: u32,
#[doc = "< Specifies the DMA transfer data width.\nThis parameter can be a value of @ref DMA_DataWidth_Sel"]
pub u32DataWidth: u32,
#[doc = "< Specifies the DMA block size."]
pub u32BlockSize: u32,
#[doc = "< Specifies the DMA transfer count."]
pub u32TransCount: u32,
#[doc = "< Specifies the source address increment mode.\nThis parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode"]
pub u32SrcAddrInc: u32,
#[doc = "< Specifies the destination address increment mode.\nThis parameter can be a value of @ref DMA_DesAddr_Incremented_Mode"]
pub u32DestAddrInc: u32,
}
#[doc = " @brief DMA repeat mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_repeat_init_t {
#[doc = "< Specifies the DMA source repeat function.\nThis parameter can be a value of @ref DMA_Repeat_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source repeat size."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA destination repeat size."]
pub u32DestCount: u32,
}
#[doc = " @brief DMA non-sequence mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_nonseq_init_t {
#[doc = "< Specifies the DMA source non-sequence function.\nThis parameter can be a value of @ref DMA_NonSeq_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source non-sequence function count."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA source non-sequence function offset."]
pub u32SrcOffset: u32,
#[doc = "< Specifies the DMA destination non-sequence function count."]
pub u32DestCount: u32,
#[doc = "< Specifies the DMA destination non-sequence function offset."]
pub u32DestOffset: u32,
}
#[doc = " @brief DMA Link List Pointer (LLP) mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_llp_init_t {
#[doc = "< Specifies the DMA LLP function.\nThis parameter can be a value of @ref DMA_Llp_En"]
pub u32State: u32,
#[doc = "< Specifies the DMA LLP auto or wait REQ.\nThis parameter can be a value of @ref DMA_Llp_Mode"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA list pointer address for LLP function."]
pub u32Addr: u32,
}
#[doc = " @brief DMA re-config function configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_reconfig_init_t {
#[doc = "< Specifies the DMA reconfig function count mode.\nThis parameter can be a value of @ref DMA_Reconfig_Count_Sel"]
pub u32CountMode: u32,
#[doc = "< Specifies the DMA reconfig function destination address mode.\nThis parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel"]
pub u32DestAddrMode: u32,
#[doc = "< Specifies the DMA reconfig function source address mode.\nThis parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel"]
pub u32SrcAddrMode: u32,
}
#[doc = " @brief DMA re-config non-sequence mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_rc_nonseq_init_t {
#[doc = "< Specifies the DMA source non-sequence function.\nThis parameter can be a value of @ref DMA_NonSeq_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source non-sequence function count."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA source non-sequence function distance."]
pub u32SrcDist: u32,
#[doc = "< Specifies the DMA destination non-sequence function count."]
pub u32DestCount: u32,
#[doc = "< Specifies the DMA destination non-sequence function distance."]
pub u32DestDist: u32,
}
#[doc = " @brief Dma LLP(linked list pointer) descriptor structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_llp_descriptor_t {
#[doc = "< LLP source address"]
pub SARx: u32,
#[doc = "< LLP destination address"]
pub DARx: u32,
#[doc = "< LLP transfer count and block size"]
pub DTCTLx: u32,
#[doc = "< LLP source & destination repeat size"]
pub RPTx: u32,
#[doc = "< LLP source non-seq count and offset"]
pub SNSEQCTLx: u32,
#[doc = "< LLP destination non-seq count and offset"]
pub DNSEQCTLx: u32,
#[doc = "< LLP next list pointer"]
pub LLPx: u32,
#[doc = "< LLP channel control"]
pub CHCTLx: u32,
}
unsafe extern "C" {
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup DMA_Global_Functions\n @{"]
pub fn DMA_Cmd(DMAx: *mut CM_DMA_TypeDef, enNewState: en_functional_state_t);
pub fn DMA_ErrIntCmd(
DMAx: *mut CM_DMA_TypeDef,
u32ErrInt: u32,
enNewState: en_functional_state_t,
);
pub fn DMA_GetErrStatus(DMAx: *const CM_DMA_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn DMA_ClearErrStatus(DMAx: *mut CM_DMA_TypeDef, u32Flag: u32);
pub fn DMA_TransCompleteIntCmd(
DMAx: *mut CM_DMA_TypeDef,
u32TransCompleteInt: u32,
enNewState: en_functional_state_t,
);
pub fn DMA_GetTransCompleteStatus(
DMAx: *const CM_DMA_TypeDef,
u32Flag: u32,
) -> en_flag_status_t;
pub fn DMA_ClearTransCompleteStatus(DMAx: *mut CM_DMA_TypeDef, u32Flag: u32);
pub fn DMA_ChCmd(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, enNewState: en_functional_state_t)
-> i32;
pub fn DMA_GetRequestStatus(DMAx: *const CM_DMA_TypeDef, u32Status: u32) -> en_flag_status_t;
pub fn DMA_GetTransStatus(DMAx: *const CM_DMA_TypeDef, u32Status: u32) -> en_flag_status_t;
pub fn DMA_SetSrcAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32) -> i32;
pub fn DMA_SetDestAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32) -> i32;
pub fn DMA_SetTransCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u16Count: u16) -> i32;
pub fn DMA_SetBlockSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u16Size: u16) -> i32;
pub fn DMA_SetDataWidth(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32DataWidth: u32) -> i32;
pub fn DMA_SetSrcRepeatSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Size: u32) -> i32;
pub fn DMA_SetDestRepeatSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Size: u32) -> i32;
pub fn DMA_SetNonSeqSrcCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Count: u32) -> i32;
pub fn DMA_SetNonSeqDestCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Count: u32) -> i32;
pub fn DMA_SetNonSeqSrcOffset(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Offset: u32) -> i32;
pub fn DMA_SetNonSeqDestOffset(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Offset: u32) -> i32;
pub fn DMA_SetLlpAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32);
pub fn DMA_StructInit(pstcDmaInit: *mut stc_dma_init_t) -> i32;
pub fn DMA_Init(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, pstcDmaInit: *const stc_dma_init_t)
-> i32;
pub fn DMA_DeInit(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8);
pub fn DMA_RepeatStructInit(pstcDmaRepeatInit: *mut stc_dma_repeat_init_t) -> i32;
pub fn DMA_RepeatInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRepeatInit: *const stc_dma_repeat_init_t,
) -> i32;
pub fn DMA_NonSeqStructInit(pstcDmaNonSeqInit: *mut stc_dma_nonseq_init_t) -> i32;
pub fn DMA_NonSeqInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaNonSeqInit: *const stc_dma_nonseq_init_t,
) -> i32;
pub fn DMA_LlpStructInit(pstcDmaLlpInit: *mut stc_dma_llp_init_t) -> i32;
pub fn DMA_LlpInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaLlpInit: *const stc_dma_llp_init_t,
) -> i32;
pub fn DMA_LlpCmd(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, enNewState: en_functional_state_t);
pub fn DMA_ReconfigStructInit(pstcDmaRCInit: *mut stc_dma_reconfig_init_t) -> i32;
pub fn DMA_ReconfigInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRCInit: *const stc_dma_reconfig_init_t,
) -> i32;
pub fn DMA_ReconfigCmd(DMAx: *mut CM_DMA_TypeDef, enNewState: en_functional_state_t);
pub fn DMA_ReconfigLlpCmd(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
enNewState: en_functional_state_t,
);
pub fn DMA_ReconfigNonSeqStructInit(pstcDmaRcNonSeqInit: *mut stc_dma_rc_nonseq_init_t) -> i32;
pub fn DMA_ReconfigNonSeqInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRcNonSeqInit: *const stc_dma_rc_nonseq_init_t,
) -> i32;
pub fn DMA_GetSrcAddr(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetDestAddr(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetTransCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetBlockSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetSrcRepeatSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetDestRepeatSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqSrcCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqDestCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqSrcOffset(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqDestOffset(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_MxChSWTrigger(DMAx: *mut CM_DMA_TypeDef, u8MxCh: u8);
pub fn DMA_SWReconfig(DMAx: *mut CM_DMA_TypeDef);
}