#[doc = "Register `SOC_CLK_CTRL0` reader"]
pub type R = crate::R<SOC_CLK_CTRL0_SPEC>;
#[doc = "Register `SOC_CLK_CTRL0` writer"]
pub type W = crate::W<SOC_CLK_CTRL0_SPEC>;
#[doc = "Field `CORE0_CLIC_CLK_EN` reader - Reserved"]
pub type CORE0_CLIC_CLK_EN_R = crate::BitReader;
#[doc = "Field `CORE0_CLIC_CLK_EN` writer - Reserved"]
pub type CORE0_CLIC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CORE1_CLIC_CLK_EN` reader - Reserved"]
pub type CORE1_CLIC_CLK_EN_R = crate::BitReader;
#[doc = "Field `CORE1_CLIC_CLK_EN` writer - Reserved"]
pub type CORE1_CLIC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MISC_CPU_CLK_EN` reader - Reserved"]
pub type MISC_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `MISC_CPU_CLK_EN` writer - Reserved"]
pub type MISC_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CORE0_CPU_CLK_EN` reader - Reserved"]
pub type CORE0_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `CORE0_CPU_CLK_EN` writer - Reserved"]
pub type CORE0_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CORE1_CPU_CLK_EN` reader - Reserved"]
pub type CORE1_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `CORE1_CPU_CLK_EN` writer - Reserved"]
pub type CORE1_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCM_CPU_CLK_EN` reader - Reserved"]
pub type TCM_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `TCM_CPU_CLK_EN` writer - Reserved"]
pub type TCM_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BUSMON_CPU_CLK_EN` reader - Reserved"]
pub type BUSMON_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `BUSMON_CPU_CLK_EN` writer - Reserved"]
pub type BUSMON_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_CPU_CLK_EN` reader - Reserved"]
pub type L1CACHE_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_CPU_CLK_EN` writer - Reserved"]
pub type L1CACHE_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_D_CPU_CLK_EN` reader - Reserved"]
pub type L1CACHE_D_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_D_CPU_CLK_EN` writer - Reserved"]
pub type L1CACHE_D_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_I0_CPU_CLK_EN` reader - Reserved"]
pub type L1CACHE_I0_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_I0_CPU_CLK_EN` writer - Reserved"]
pub type L1CACHE_I0_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_I1_CPU_CLK_EN` reader - Reserved"]
pub type L1CACHE_I1_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_I1_CPU_CLK_EN` writer - Reserved"]
pub type L1CACHE_I1_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRACE_CPU_CLK_EN` reader - Reserved"]
pub type TRACE_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `TRACE_CPU_CLK_EN` writer - Reserved"]
pub type TRACE_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_CPU_CLK_EN` reader - Reserved"]
pub type ICM_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `ICM_CPU_CLK_EN` writer - Reserved"]
pub type ICM_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_CPU_CLK_EN` reader - Reserved"]
pub type GDMA_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `GDMA_CPU_CLK_EN` writer - Reserved"]
pub type GDMA_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VPU_CPU_CLK_EN` reader - Reserved"]
pub type VPU_CPU_CLK_EN_R = crate::BitReader;
#[doc = "Field `VPU_CPU_CLK_EN` writer - Reserved"]
pub type VPU_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_MEM_CLK_EN` reader - Reserved"]
pub type L1CACHE_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_MEM_CLK_EN` writer - Reserved"]
pub type L1CACHE_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_D_MEM_CLK_EN` reader - Reserved"]
pub type L1CACHE_D_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_D_MEM_CLK_EN` writer - Reserved"]
pub type L1CACHE_D_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_I0_MEM_CLK_EN` reader - Reserved"]
pub type L1CACHE_I0_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_I0_MEM_CLK_EN` writer - Reserved"]
pub type L1CACHE_I0_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L1CACHE_I1_MEM_CLK_EN` reader - Reserved"]
pub type L1CACHE_I1_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L1CACHE_I1_MEM_CLK_EN` writer - Reserved"]
pub type L1CACHE_I1_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2CACHE_MEM_CLK_EN` reader - Reserved"]
pub type L2CACHE_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2CACHE_MEM_CLK_EN` writer - Reserved"]
pub type L2CACHE_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2MEM_MEM_CLK_EN` reader - Reserved"]
pub type L2MEM_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2MEM_MEM_CLK_EN` writer - Reserved"]
pub type L2MEM_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2MEMMON_MEM_CLK_EN` reader - Reserved"]
pub type L2MEMMON_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2MEMMON_MEM_CLK_EN` writer - Reserved"]
pub type L2MEMMON_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_MEM_CLK_EN` reader - Reserved"]
pub type ICM_MEM_CLK_EN_R = crate::BitReader;
#[doc = "Field `ICM_MEM_CLK_EN` writer - Reserved"]
pub type ICM_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MISC_SYS_CLK_EN` reader - Reserved"]
pub type MISC_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `MISC_SYS_CLK_EN` writer - Reserved"]
pub type MISC_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRACE_SYS_CLK_EN` reader - Reserved"]
pub type TRACE_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `TRACE_SYS_CLK_EN` writer - Reserved"]
pub type TRACE_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2CACHE_SYS_CLK_EN` reader - Reserved"]
pub type L2CACHE_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2CACHE_SYS_CLK_EN` writer - Reserved"]
pub type L2CACHE_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2MEM_SYS_CLK_EN` reader - Reserved"]
pub type L2MEM_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2MEM_SYS_CLK_EN` writer - Reserved"]
pub type L2MEM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `L2MEMMON_SYS_CLK_EN` reader - Reserved"]
pub type L2MEMMON_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `L2MEMMON_SYS_CLK_EN` writer - Reserved"]
pub type L2MEMMON_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCMMON_SYS_CLK_EN` reader - Reserved"]
pub type TCMMON_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `TCMMON_SYS_CLK_EN` writer - Reserved"]
pub type TCMMON_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_SYS_CLK_EN` reader - Reserved"]
pub type ICM_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `ICM_SYS_CLK_EN` writer - Reserved"]
pub type ICM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_SYS_CLK_EN` reader - Reserved"]
pub type FLASH_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `FLASH_SYS_CLK_EN` writer - Reserved"]
pub type FLASH_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSRAM_SYS_CLK_EN` reader - Reserved"]
pub type PSRAM_SYS_CLK_EN_R = crate::BitReader;
#[doc = "Field `PSRAM_SYS_CLK_EN` writer - Reserved"]
pub type PSRAM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Reserved"]
#[inline(always)]
pub fn core0_clic_clk_en(&self) -> CORE0_CLIC_CLK_EN_R {
CORE0_CLIC_CLK_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Reserved"]
#[inline(always)]
pub fn core1_clic_clk_en(&self) -> CORE1_CLIC_CLK_EN_R {
CORE1_CLIC_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Reserved"]
#[inline(always)]
pub fn misc_cpu_clk_en(&self) -> MISC_CPU_CLK_EN_R {
MISC_CPU_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Reserved"]
#[inline(always)]
pub fn core0_cpu_clk_en(&self) -> CORE0_CPU_CLK_EN_R {
CORE0_CPU_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Reserved"]
#[inline(always)]
pub fn core1_cpu_clk_en(&self) -> CORE1_CPU_CLK_EN_R {
CORE1_CPU_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Reserved"]
#[inline(always)]
pub fn tcm_cpu_clk_en(&self) -> TCM_CPU_CLK_EN_R {
TCM_CPU_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Reserved"]
#[inline(always)]
pub fn busmon_cpu_clk_en(&self) -> BUSMON_CPU_CLK_EN_R {
BUSMON_CPU_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Reserved"]
#[inline(always)]
pub fn l1cache_cpu_clk_en(&self) -> L1CACHE_CPU_CLK_EN_R {
L1CACHE_CPU_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Reserved"]
#[inline(always)]
pub fn l1cache_d_cpu_clk_en(&self) -> L1CACHE_D_CPU_CLK_EN_R {
L1CACHE_D_CPU_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Reserved"]
#[inline(always)]
pub fn l1cache_i0_cpu_clk_en(&self) -> L1CACHE_I0_CPU_CLK_EN_R {
L1CACHE_I0_CPU_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Reserved"]
#[inline(always)]
pub fn l1cache_i1_cpu_clk_en(&self) -> L1CACHE_I1_CPU_CLK_EN_R {
L1CACHE_I1_CPU_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Reserved"]
#[inline(always)]
pub fn trace_cpu_clk_en(&self) -> TRACE_CPU_CLK_EN_R {
TRACE_CPU_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Reserved"]
#[inline(always)]
pub fn icm_cpu_clk_en(&self) -> ICM_CPU_CLK_EN_R {
ICM_CPU_CLK_EN_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Reserved"]
#[inline(always)]
pub fn gdma_cpu_clk_en(&self) -> GDMA_CPU_CLK_EN_R {
GDMA_CPU_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Reserved"]
#[inline(always)]
pub fn vpu_cpu_clk_en(&self) -> VPU_CPU_CLK_EN_R {
VPU_CPU_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Reserved"]
#[inline(always)]
pub fn l1cache_mem_clk_en(&self) -> L1CACHE_MEM_CLK_EN_R {
L1CACHE_MEM_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Reserved"]
#[inline(always)]
pub fn l1cache_d_mem_clk_en(&self) -> L1CACHE_D_MEM_CLK_EN_R {
L1CACHE_D_MEM_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Reserved"]
#[inline(always)]
pub fn l1cache_i0_mem_clk_en(&self) -> L1CACHE_I0_MEM_CLK_EN_R {
L1CACHE_I0_MEM_CLK_EN_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Reserved"]
#[inline(always)]
pub fn l1cache_i1_mem_clk_en(&self) -> L1CACHE_I1_MEM_CLK_EN_R {
L1CACHE_I1_MEM_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Reserved"]
#[inline(always)]
pub fn l2cache_mem_clk_en(&self) -> L2CACHE_MEM_CLK_EN_R {
L2CACHE_MEM_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Reserved"]
#[inline(always)]
pub fn l2mem_mem_clk_en(&self) -> L2MEM_MEM_CLK_EN_R {
L2MEM_MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Reserved"]
#[inline(always)]
pub fn l2memmon_mem_clk_en(&self) -> L2MEMMON_MEM_CLK_EN_R {
L2MEMMON_MEM_CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Reserved"]
#[inline(always)]
pub fn icm_mem_clk_en(&self) -> ICM_MEM_CLK_EN_R {
ICM_MEM_CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Reserved"]
#[inline(always)]
pub fn misc_sys_clk_en(&self) -> MISC_SYS_CLK_EN_R {
MISC_SYS_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Reserved"]
#[inline(always)]
pub fn trace_sys_clk_en(&self) -> TRACE_SYS_CLK_EN_R {
TRACE_SYS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Reserved"]
#[inline(always)]
pub fn l2cache_sys_clk_en(&self) -> L2CACHE_SYS_CLK_EN_R {
L2CACHE_SYS_CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Reserved"]
#[inline(always)]
pub fn l2mem_sys_clk_en(&self) -> L2MEM_SYS_CLK_EN_R {
L2MEM_SYS_CLK_EN_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Reserved"]
#[inline(always)]
pub fn l2memmon_sys_clk_en(&self) -> L2MEMMON_SYS_CLK_EN_R {
L2MEMMON_SYS_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Reserved"]
#[inline(always)]
pub fn tcmmon_sys_clk_en(&self) -> TCMMON_SYS_CLK_EN_R {
TCMMON_SYS_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - Reserved"]
#[inline(always)]
pub fn icm_sys_clk_en(&self) -> ICM_SYS_CLK_EN_R {
ICM_SYS_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Reserved"]
#[inline(always)]
pub fn flash_sys_clk_en(&self) -> FLASH_SYS_CLK_EN_R {
FLASH_SYS_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Reserved"]
#[inline(always)]
pub fn psram_sys_clk_en(&self) -> PSRAM_SYS_CLK_EN_R {
PSRAM_SYS_CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOC_CLK_CTRL0")
.field(
"core0_clic_clk_en",
&format_args!("{}", self.core0_clic_clk_en().bit()),
)
.field(
"core1_clic_clk_en",
&format_args!("{}", self.core1_clic_clk_en().bit()),
)
.field(
"misc_cpu_clk_en",
&format_args!("{}", self.misc_cpu_clk_en().bit()),
)
.field(
"core0_cpu_clk_en",
&format_args!("{}", self.core0_cpu_clk_en().bit()),
)
.field(
"core1_cpu_clk_en",
&format_args!("{}", self.core1_cpu_clk_en().bit()),
)
.field(
"tcm_cpu_clk_en",
&format_args!("{}", self.tcm_cpu_clk_en().bit()),
)
.field(
"busmon_cpu_clk_en",
&format_args!("{}", self.busmon_cpu_clk_en().bit()),
)
.field(
"l1cache_cpu_clk_en",
&format_args!("{}", self.l1cache_cpu_clk_en().bit()),
)
.field(
"l1cache_d_cpu_clk_en",
&format_args!("{}", self.l1cache_d_cpu_clk_en().bit()),
)
.field(
"l1cache_i0_cpu_clk_en",
&format_args!("{}", self.l1cache_i0_cpu_clk_en().bit()),
)
.field(
"l1cache_i1_cpu_clk_en",
&format_args!("{}", self.l1cache_i1_cpu_clk_en().bit()),
)
.field(
"trace_cpu_clk_en",
&format_args!("{}", self.trace_cpu_clk_en().bit()),
)
.field(
"icm_cpu_clk_en",
&format_args!("{}", self.icm_cpu_clk_en().bit()),
)
.field(
"gdma_cpu_clk_en",
&format_args!("{}", self.gdma_cpu_clk_en().bit()),
)
.field(
"vpu_cpu_clk_en",
&format_args!("{}", self.vpu_cpu_clk_en().bit()),
)
.field(
"l1cache_mem_clk_en",
&format_args!("{}", self.l1cache_mem_clk_en().bit()),
)
.field(
"l1cache_d_mem_clk_en",
&format_args!("{}", self.l1cache_d_mem_clk_en().bit()),
)
.field(
"l1cache_i0_mem_clk_en",
&format_args!("{}", self.l1cache_i0_mem_clk_en().bit()),
)
.field(
"l1cache_i1_mem_clk_en",
&format_args!("{}", self.l1cache_i1_mem_clk_en().bit()),
)
.field(
"l2cache_mem_clk_en",
&format_args!("{}", self.l2cache_mem_clk_en().bit()),
)
.field(
"l2mem_mem_clk_en",
&format_args!("{}", self.l2mem_mem_clk_en().bit()),
)
.field(
"l2memmon_mem_clk_en",
&format_args!("{}", self.l2memmon_mem_clk_en().bit()),
)
.field(
"icm_mem_clk_en",
&format_args!("{}", self.icm_mem_clk_en().bit()),
)
.field(
"misc_sys_clk_en",
&format_args!("{}", self.misc_sys_clk_en().bit()),
)
.field(
"trace_sys_clk_en",
&format_args!("{}", self.trace_sys_clk_en().bit()),
)
.field(
"l2cache_sys_clk_en",
&format_args!("{}", self.l2cache_sys_clk_en().bit()),
)
.field(
"l2mem_sys_clk_en",
&format_args!("{}", self.l2mem_sys_clk_en().bit()),
)
.field(
"l2memmon_sys_clk_en",
&format_args!("{}", self.l2memmon_sys_clk_en().bit()),
)
.field(
"tcmmon_sys_clk_en",
&format_args!("{}", self.tcmmon_sys_clk_en().bit()),
)
.field(
"icm_sys_clk_en",
&format_args!("{}", self.icm_sys_clk_en().bit()),
)
.field(
"flash_sys_clk_en",
&format_args!("{}", self.flash_sys_clk_en().bit()),
)
.field(
"psram_sys_clk_en",
&format_args!("{}", self.psram_sys_clk_en().bit()),
)
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<SOC_CLK_CTRL0_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bit 0 - Reserved"]
#[inline(always)]
#[must_use]
pub fn core0_clic_clk_en(&mut self) -> CORE0_CLIC_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
CORE0_CLIC_CLK_EN_W::new(self, 0)
}
#[doc = "Bit 1 - Reserved"]
#[inline(always)]
#[must_use]
pub fn core1_clic_clk_en(&mut self) -> CORE1_CLIC_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
CORE1_CLIC_CLK_EN_W::new(self, 1)
}
#[doc = "Bit 2 - Reserved"]
#[inline(always)]
#[must_use]
pub fn misc_cpu_clk_en(&mut self) -> MISC_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
MISC_CPU_CLK_EN_W::new(self, 2)
}
#[doc = "Bit 3 - Reserved"]
#[inline(always)]
#[must_use]
pub fn core0_cpu_clk_en(&mut self) -> CORE0_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
CORE0_CPU_CLK_EN_W::new(self, 3)
}
#[doc = "Bit 4 - Reserved"]
#[inline(always)]
#[must_use]
pub fn core1_cpu_clk_en(&mut self) -> CORE1_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
CORE1_CPU_CLK_EN_W::new(self, 4)
}
#[doc = "Bit 5 - Reserved"]
#[inline(always)]
#[must_use]
pub fn tcm_cpu_clk_en(&mut self) -> TCM_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
TCM_CPU_CLK_EN_W::new(self, 5)
}
#[doc = "Bit 6 - Reserved"]
#[inline(always)]
#[must_use]
pub fn busmon_cpu_clk_en(&mut self) -> BUSMON_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
BUSMON_CPU_CLK_EN_W::new(self, 6)
}
#[doc = "Bit 7 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_cpu_clk_en(&mut self) -> L1CACHE_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_CPU_CLK_EN_W::new(self, 7)
}
#[doc = "Bit 8 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_d_cpu_clk_en(&mut self) -> L1CACHE_D_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_D_CPU_CLK_EN_W::new(self, 8)
}
#[doc = "Bit 9 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_i0_cpu_clk_en(&mut self) -> L1CACHE_I0_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_I0_CPU_CLK_EN_W::new(self, 9)
}
#[doc = "Bit 10 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_i1_cpu_clk_en(&mut self) -> L1CACHE_I1_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_I1_CPU_CLK_EN_W::new(self, 10)
}
#[doc = "Bit 11 - Reserved"]
#[inline(always)]
#[must_use]
pub fn trace_cpu_clk_en(&mut self) -> TRACE_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
TRACE_CPU_CLK_EN_W::new(self, 11)
}
#[doc = "Bit 12 - Reserved"]
#[inline(always)]
#[must_use]
pub fn icm_cpu_clk_en(&mut self) -> ICM_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
ICM_CPU_CLK_EN_W::new(self, 12)
}
#[doc = "Bit 13 - Reserved"]
#[inline(always)]
#[must_use]
pub fn gdma_cpu_clk_en(&mut self) -> GDMA_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
GDMA_CPU_CLK_EN_W::new(self, 13)
}
#[doc = "Bit 14 - Reserved"]
#[inline(always)]
#[must_use]
pub fn vpu_cpu_clk_en(&mut self) -> VPU_CPU_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
VPU_CPU_CLK_EN_W::new(self, 14)
}
#[doc = "Bit 15 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_mem_clk_en(&mut self) -> L1CACHE_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_MEM_CLK_EN_W::new(self, 15)
}
#[doc = "Bit 16 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_d_mem_clk_en(&mut self) -> L1CACHE_D_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_D_MEM_CLK_EN_W::new(self, 16)
}
#[doc = "Bit 17 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_i0_mem_clk_en(&mut self) -> L1CACHE_I0_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_I0_MEM_CLK_EN_W::new(self, 17)
}
#[doc = "Bit 18 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l1cache_i1_mem_clk_en(&mut self) -> L1CACHE_I1_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L1CACHE_I1_MEM_CLK_EN_W::new(self, 18)
}
#[doc = "Bit 19 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2cache_mem_clk_en(&mut self) -> L2CACHE_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2CACHE_MEM_CLK_EN_W::new(self, 19)
}
#[doc = "Bit 20 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2mem_mem_clk_en(&mut self) -> L2MEM_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2MEM_MEM_CLK_EN_W::new(self, 20)
}
#[doc = "Bit 21 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2memmon_mem_clk_en(&mut self) -> L2MEMMON_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2MEMMON_MEM_CLK_EN_W::new(self, 21)
}
#[doc = "Bit 22 - Reserved"]
#[inline(always)]
#[must_use]
pub fn icm_mem_clk_en(&mut self) -> ICM_MEM_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
ICM_MEM_CLK_EN_W::new(self, 22)
}
#[doc = "Bit 23 - Reserved"]
#[inline(always)]
#[must_use]
pub fn misc_sys_clk_en(&mut self) -> MISC_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
MISC_SYS_CLK_EN_W::new(self, 23)
}
#[doc = "Bit 24 - Reserved"]
#[inline(always)]
#[must_use]
pub fn trace_sys_clk_en(&mut self) -> TRACE_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
TRACE_SYS_CLK_EN_W::new(self, 24)
}
#[doc = "Bit 25 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2cache_sys_clk_en(&mut self) -> L2CACHE_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2CACHE_SYS_CLK_EN_W::new(self, 25)
}
#[doc = "Bit 26 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2mem_sys_clk_en(&mut self) -> L2MEM_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2MEM_SYS_CLK_EN_W::new(self, 26)
}
#[doc = "Bit 27 - Reserved"]
#[inline(always)]
#[must_use]
pub fn l2memmon_sys_clk_en(&mut self) -> L2MEMMON_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
L2MEMMON_SYS_CLK_EN_W::new(self, 27)
}
#[doc = "Bit 28 - Reserved"]
#[inline(always)]
#[must_use]
pub fn tcmmon_sys_clk_en(&mut self) -> TCMMON_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
TCMMON_SYS_CLK_EN_W::new(self, 28)
}
#[doc = "Bit 29 - Reserved"]
#[inline(always)]
#[must_use]
pub fn icm_sys_clk_en(&mut self) -> ICM_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
ICM_SYS_CLK_EN_W::new(self, 29)
}
#[doc = "Bit 30 - Reserved"]
#[inline(always)]
#[must_use]
pub fn flash_sys_clk_en(&mut self) -> FLASH_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
FLASH_SYS_CLK_EN_W::new(self, 30)
}
#[doc = "Bit 31 - Reserved"]
#[inline(always)]
#[must_use]
pub fn psram_sys_clk_en(&mut self) -> PSRAM_SYS_CLK_EN_W<SOC_CLK_CTRL0_SPEC> {
PSRAM_SYS_CLK_EN_W::new(self, 31)
}
}
#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOC_CLK_CTRL0_SPEC;
impl crate::RegisterSpec for SOC_CLK_CTRL0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`soc_clk_ctrl0::R`](R) reader structure"]
impl crate::Readable for SOC_CLK_CTRL0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`soc_clk_ctrl0::W`](W) writer structure"]
impl crate::Writable for SOC_CLK_CTRL0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOC_CLK_CTRL0 to value 0xe6df_97af"]
impl crate::Resettable for SOC_CLK_CTRL0_SPEC {
const RESET_VALUE: u32 = 0xe6df_97af;
}