use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
blocks: &[Block {
name: "Afio",
extends: None,
description: Some("Alternate function I/O."),
items: &[
BlockItem {
name: "ecr",
description: Some("Event Control Register (AFIO_ECR)."),
array: None,
byte_offset: 0x0,
inner: BlockItemInner::Register(Register {
access: Access::ReadWrite,
bit_size: 32,
fieldset: Some("Ecr"),
}),
},
BlockItem {
name: "pcfr1",
description: Some("AF remap and debug I/O configuration register 1 (AFIO_PCFR1)."),
array: None,
byte_offset: 0x4,
inner: BlockItemInner::Register(Register {
access: Access::ReadWrite,
bit_size: 32,
fieldset: Some("Pcfr1"),
}),
},
BlockItem {
name: "exticr",
description: Some("External interrupt configuration register 1 (AFIO_EXTICR1)."),
array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
byte_offset: 0x8,
inner: BlockItemInner::Register(Register {
access: Access::ReadWrite,
bit_size: 32,
fieldset: Some("Exticr"),
}),
},
BlockItem {
name: "cr",
description: Some("AFIO control register (AFIO_CR)."),
array: None,
byte_offset: 0x18,
inner: BlockItemInner::Register(Register {
access: Access::ReadWrite,
bit_size: 32,
fieldset: Some("Cr"),
}),
},
BlockItem {
name: "pcfr2",
description: Some("AF remap and debug I/O configuration register (AFIO_PCFR2)."),
array: None,
byte_offset: 0x1c,
inner: BlockItemInner::Register(Register {
access: Access::ReadWrite,
bit_size: 32,
fieldset: Some("Pcfr2"),
}),
},
],
}],
fieldsets: &[
FieldSet {
name: "Cr",
extends: None,
description: Some("AFIO control register (AFIO_CR)."),
bit_size: 32,
fields: &[
Field {
name: "usbpd_in_hvt",
description: Some("PD pin PB6/PD7 High threshold input mode."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udp_bc_vsrc",
description: Some("PA12/UDP pin BC source voltage enable."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udm_bc_vsrc",
description: Some("PA11/UDM pin BC source voltage enable."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udp_bc_cmpe",
description: Some("PA12/UDP pin BC protocol comparator enable."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udm_bc_cmpe",
description: Some("PA11/UDM pin BC protocol comparator enable."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udp_bc_cmpo",
description: Some("PA12/UDP pin BC protocol comparator status."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "udm_bc_cmpo",
description: Some("PA11/UDM pin BC protocol comparator status."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
bit_size: 1,
array: None,
enumm: None,
},
],
},
FieldSet {
name: "Ecr",
extends: None,
description: Some("Event Control Register (AFIO_ECR)."),
bit_size: 32,
fields: &[
Field {
name: "pin",
description: Some("Pin selection."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
bit_size: 4,
array: None,
enumm: None,
},
Field {
name: "port",
description: Some("Port selection."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
bit_size: 3,
array: None,
enumm: None,
},
Field {
name: "evoe",
description: Some("Event Output Enable."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
bit_size: 1,
array: None,
enumm: None,
},
],
},
FieldSet {
name: "Exticr",
extends: None,
description: Some("External interrupt configuration register 4 (AFIO_EXTICR4)."),
bit_size: 32,
fields: &[Field {
name: "exti",
description: Some("EXTI12 configuration."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
bit_size: 4,
array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
enumm: None,
}],
},
FieldSet {
name: "Pcfr1",
extends: None,
description: Some("AF remap and debug I/O configuration register 1 (AFIO_PCFR1)."),
bit_size: 32,
fields: &[
Field {
name: "spi1_rm",
description: Some("SPI1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "i2c1_rm",
description: Some("I2C1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "usart1_rm",
description: Some("USART1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "usart2_rm",
description: Some("USART2 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "usart3_rm",
description: Some("USART3 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
bit_size: 2,
array: None,
enumm: None,
},
Field {
name: "tim1_rm",
description: Some("TIM1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
bit_size: 2,
array: None,
enumm: None,
},
Field {
name: "tim2_rm",
description: Some("TIM2 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
bit_size: 2,
array: None,
enumm: None,
},
Field {
name: "tim3_rm",
description: Some("TIM3 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "tim4_rm",
description: Some("TIM4 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "can_rm",
description: Some("CAN remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
bit_size: 2,
array: None,
enumm: None,
},
Field {
name: "pd01_rm",
description: Some("Port D0/Port D1 mapping on OSCIN/OSCOUT."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "sw_cfg",
description: Some("Serial wire JTAG configuration."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
bit_size: 3,
array: None,
enumm: None,
},
],
},
FieldSet {
name: "Pcfr2",
extends: None,
description: Some("AF remap and debug I/O configuration register (AFIO_PCFR2)."),
bit_size: 32,
fields: &[
Field {
name: "usart4_rm",
description: Some("USART4 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "usart2_rm_h",
description: Some("USART2 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "usart1_rm_h",
description: Some("USART1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
bit_size: 2,
array: None,
enumm: None,
},
Field {
name: "tim2_rm_h",
description: Some("TIM2 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "tim1_rm_h",
description: Some("TIM1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "i2c1_rm_h",
description: Some("I2C1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "spi1_rm_h",
description: Some("SPI1 remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
bit_size: 1,
array: None,
enumm: None,
},
Field {
name: "lptim_rm",
description: Some("LPTIM remapping."),
bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
bit_size: 1,
array: None,
enumm: None,
},
],
},
],
enums: &[],
};