calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

// -p group2invoke -p dead-group-removal
import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main() -> () {
  cells {
    r = std_reg(32);
    add = std_add(32);
    lt = std_lt(32);
  }
  wires {
    // simple transformation
    group write_r {
      r.in = 32'd1;
      r.write_en = 1'd1;
      write_r[done] = r.done;
    }
    // transform w/ comb group
    group add_write_r{
      r.in = add.out;
      r.write_en = 1'd1;
      add_write_r[done] = r.done;
      add.left = 32'd2;
      add.right = 32'd3;
    }
    // multiple guarded assignments to r.in
    group g{
      r.write_en = 1'd1;
      r.in = 1'd0 ? 32'd1;
      r.in = 1'd0 ? 32'd2;
      g[done] = r.done;
    }
    // need comb group that has multiple combinational cells
    group guard2{
      lt.left = 32'd2;
      lt.right = 32'd4;
      add.left = 32'd2;
      add.right = lt.out ? r.out;
      r.write_en = 1'd1;
      r.in = add.out;
      guard2[done] = r.done;
    }
    group read_write_same {
      r.write_en = 1'd1;
      r.in = r.out;
      read_write_same[done] = r.done;
    }
  }
  control {
    seq{
      write_r;
      g;
      @foo add_write_r;
      @bar guard2;
      read_write_same;
    }
  }
}