calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r = std_reg(32);
    a = std_reg(32);
  }
  wires {
    group chain {
      r.write_en = !r.done ? 1'd1;
      r.in = 32'd2;
      a.in = 32'd7;
      a.write_en = r.done;
      chain[done] = a.done;
    }
  }
  control {
    chain;
  }
}