calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r = std_reg(32);
    add = std_add(32);
    lt = std_lt(32);
    @generated in_guarded_wire = std_wire(32);
  }
  wires {
    comb group comb_invoke {
      add.left = 32'd2;
      add.right = 32'd3;
    }
    comb group comb_invoke0 {
      in_guarded_wire.in = 1'd0 ? 32'd1;
      in_guarded_wire.in = 1'd0 ? 32'd2;
    }
    comb group comb_invoke1 {
      lt.left = 32'd2;
      lt.right = 32'd4;
      add.left = 32'd2;
      add.right = lt.out ? r.out;
    }
  }
  control {
    seq {
      invoke r(
        in = 32'd1
      )();
      invoke r(
        in = in_guarded_wire.out
      )() with comb_invoke0;
      @foo invoke r(
        in = add.out
      )() with comb_invoke;
      @bar invoke r(
        in = add.out
      )() with comb_invoke1;
      invoke r(
        in = r.out
      )();
    }
  }
}