calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    e = std_eq(32);
    r = std_reg(1);
  }
  wires {
    group wait {
      r.write_en = e.out ? 1'd1;
      r.in = e.out;
      wait[done] = r.done;
    }
  }
  control {
    wait;
  }
}